1 #ifndef CYGONCE_MCF5272_SERIAL_H
2 #define CYGONCE_MCF5272_SERIAL_H
4 //==========================================================================
6 // devs/serial/coldfire/mcf5272/mcf5272_serial.h
8 // ColdFire MCF5272 serial I/O module definitions.
10 //==========================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2006 eCosCentric Ltd.
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18 // the terms of the GNU General Public License as published by the Free
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22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
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39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //==========================================================================
42 //#####DESCRIPTIONBEGIN####
44 // Author(s): Enrico Piria, Wade Jensen
47 // Purpose: MCF5272 serial I/O module definitions.
50 //####DESCRIPTIONEND####
51 //==========================================================================
54 #include <pkgconf/io_serial_coldfire_mcf5272.h>
56 // Bit level definitions and macros
57 #define MCF5272_UART_UMR1_RXRTS (0x80)
58 #define MCF5272_UART_UMR1_RXIRQ (0x40)
59 #define MCF5272_UART_UMR1_ERR (0x20)
60 #define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C)
61 #define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18)
62 #define MCF5272_UART_UMR1_PM_NONE (0x10)
63 #define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C)
64 #define MCF5272_UART_UMR1_PM_FORCE_LO (0x08)
65 #define MCF5272_UART_UMR1_PM_ODD (0x04)
66 #define MCF5272_UART_UMR1_PM_EVEN (0x00)
67 #define MCF5272_UART_UMR1_BC_5 (0x00)
68 #define MCF5272_UART_UMR1_BC_6 (0x01)
69 #define MCF5272_UART_UMR1_BC_7 (0x02)
70 #define MCF5272_UART_UMR1_BC_8 (0x03)
72 #define MCF5272_UART_UMR2_CM_NORMAL (0x00)
73 #define MCF5272_UART_UMR2_CM_ECHO (0x40)
74 #define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80)
75 #define MCF5272_UART_UMR2_CM_REMOTE_LOO (0xC0)
76 #define MCF5272_UART_UMR2_TXRTS (0x20)
77 #define MCF5272_UART_UMR2_TXCTS (0x10)
78 #define MCF5272_UART_UMR2_STOP_BITS_1 (0x07)
79 #define MCF5272_UART_UMR2_STOP_BITS_15 (0x08)
80 #define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F)
82 #define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f)
84 #define MCF5272_UART_USR_RB (0x80)
85 #define MCF5272_UART_USR_FE (0x40)
86 #define MCF5272_UART_USR_PE (0x20)
87 #define MCF5272_UART_USR_OE (0x10)
88 #define MCF5272_UART_USR_TXEMP (0x08)
89 #define MCF5272_UART_USR_TXRDY (0x04)
90 #define MCF5272_UART_USR_FFULL (0x02)
91 #define MCF5272_UART_USR_RXRDY (0x01)
94 #define MCF5272_UART_UCSR_RCS(a) (((a) & 0x0f) << 4)
96 #define MCF5272_UART_UCSR_TCS(a) ((a) & 0x0f)
99 #define MCF5272_UART_UCR_NONE (0x00)
100 #define MCF5272_UART_UCR_ENAB (0x80)
101 #define MCF5272_UART_UCR_STOP_BREAK (0x70)
102 #define MCF5272_UART_UCR_START_BREAK (0x60)
103 #define MCF5272_UART_UCR_RESET_BKCHGINT (0x50)
104 #define MCF5272_UART_UCR_RESET_ERROR (0x40)
105 #define MCF5272_UART_UCR_RESET_TX (0x30)
106 #define MCF5272_UART_UCR_RESET_RX (0x20)
107 #define MCF5272_UART_UCR_RESET_MR (0x10)
108 #define MCF5272_UART_UCR_TX_DISABLED (0x08)
109 #define MCF5272_UART_UCR_TX_ENABLED (0x04)
110 #define MCF5272_UART_UCR_RX_DISABLED (0x02)
111 #define MCF5272_UART_UCR_RX_ENABLED (0x01)
113 #define MCF5272_UART_UCR_TXRXEN \
114 (MCF5272_UART_UCR_TX_ENABLED | MCF5272_UART_UCR_RX_ENABLED)
116 #define MCF5272_UART_UCCR_COS (0x10)
117 #define MCF5272_UART_UCCR_CTS (0x01)
119 #define MCF5272_UART_UACR_BRG (0x80)
120 #define MCF5272_UART_UACR_CTMS_TIMER (0x60)
121 #define MCF5272_UART_UACR_IEC (0x01)
123 #define MCF5272_UART_UISR_COS (0x80)
124 #define MCF5272_UART_UISR_ABC (0x40)
125 #define MCF5272_UART_UISR_DB (0x04)
126 #define MCF5272_UART_UISR_RXRDY (0x02)
127 #define MCF5272_UART_UISR_TXRDY (0x01)
129 #define MCF5272_UART_UIMR_COS (0x80)
130 #define MCF5272_UART_UIMR_ABC (0x40)
131 #define MCF5272_UART_UIMR_DB (0x04)
132 #define MCF5272_UART_UIMR_FFULL_RXRDY (0x02)
133 #define MCF5272_UART_UIMR_TXRDY (0x01)
135 #define MCF5272_UART_UOP0_RTS (0x01)
136 #define MCF5272_UART_UOP1_RTS (0x01)
138 // ---------------------------------------------------------------------------
139 // End of mcf5272_serial.h
140 #endif // CYGONCE_MCF5272_SERIAL_H