1 #ifndef _SER_MCF5272_H_
2 #define _SER_MCF5272_H_
3 //==========================================================================
4 //####ECOSGPLCOPYRIGHTBEGIN####
5 // -------------------------------------------
6 // This file is part of eCos, the Embedded Configurable Operating System.
7 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
9 // eCos is free software; you can redistribute it and/or modify it under
10 // the terms of the GNU General Public License as published by the Free
11 // Software Foundation; either version 2 or (at your option) any later version.
13 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
14 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 // You should have received a copy of the GNU General Public License along
19 // with eCos; if not, write to the Free Software Foundation, Inc.,
20 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 // As a special exception, if other files instantiate templates or use macros
23 // or inline functions from this file, or you compile this file and link it
24 // with other works to produce a work based on this file, this file does not
25 // by itself cause the resulting work to be covered by the GNU General Public
26 // License. However the source code for this file must still be made available
27 // in accordance with section (3) of the GNU General Public License.
29 // This exception does not invalidate any other reasons why a work based on
30 // this file might be covered by the GNU General Public License.
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33 // at http://sources.redhat.com/ecos/ecos-license/
34 // -------------------------------------------
35 //####ECOSGPLCOPYRIGHTEND####
36 //==========================================================================
38 #include <pkgconf/io_serial_mcf5272_uart.h>
40 /* Bit level definitions and macros */
41 #define MCF5272_UART_UMR1_RXRTS (0x80)
42 #define MCF5272_UART_UMR1_RXIRQ (0x40)
43 #define MCF5272_UART_UMR1_ERR (0x20)
44 #define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C)
45 #define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18)
46 #define MCF5272_UART_UMR1_PM_NONE (0x10)
47 #define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C)
48 #define MCF5272_UART_UMR1_PM_FORCE_LO (0x08)
49 #define MCF5272_UART_UMR1_PM_ODD (0x04)
50 #define MCF5272_UART_UMR1_PM_EVEN (0x00)
51 #define MCF5272_UART_UMR1_BC_5 (0x00)
52 #define MCF5272_UART_UMR1_BC_6 (0x01)
53 #define MCF5272_UART_UMR1_BC_7 (0x02)
54 #define MCF5272_UART_UMR1_BC_8 (0x03)
56 #define MCF5272_UART_UMR2_CM_NORMAL (0x00)
57 #define MCF5272_UART_UMR2_CM_ECHO (0x40)
58 #define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80)
59 #define MCF5272_UART_UMR2_CM_REMOTE_LOOP (0xC0)
60 #define MCF5272_UART_UMR2_TXRTS (0x20)
61 #define MCF5272_UART_UMR2_TXCTS (0x10)
62 #define MCF5272_UART_UMR2_STOP_BITS_1 (0x07)
63 #define MCF5272_UART_UMR2_STOP_BITS_15 (0x08)
64 #define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F)
65 #define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f) /* Stop Bit Length */
67 //#define MCF5272_UART_USR_RB (0x80)
68 //#define MCF5272_UART_USR_FE (0x40)
69 //#define MCF5272_UART_USR_PE (0x20)
70 //#define MCF5272_UART_USR_OE (0x10)
71 //#define MCF5272_UART_USR_TXEMP (0x08)
72 //#define MCF5272_UART_USR_TXRDY (0x04)
73 #define MCF5272_UART_USR_FFULL (0x02)
74 #define MCF5272_UART_USR_RXRDY (0x01)
76 #define MCF5272_UART_UCSR_RCS(a) (((a)&0x0f)<<4) /* Rx Clk Select */
77 #define MCF5272_UART_UCSR_TCS(a) ((a)&0x0f) /* Tx Clk Select */
80 #define MCF5272_UART_UCR_NONE (0x00)
81 #define MCF5272_UART_UCR_ENAB (0x80)
82 #define MCF5272_UART_UCR_STOP_BREAK (0x70)
83 #define MCF5272_UART_UCR_START_BREAK (0x60)
84 #define MCF5272_UART_UCR_RESET_BKCHGINT (0x50)
85 #define MCF5272_UART_UCR_RESET_ERROR (0x40)
86 #define MCF5272_UART_UCR_RESET_TX (0x30)
87 #define MCF5272_UART_UCR_RESET_RX (0x20)
88 #define MCF5272_UART_UCR_RESET_MR (0x10)
89 #define MCF5272_UART_UCR_TX_DISABLED (0x08)
90 #define MCF5272_UART_UCR_TX_ENABLED (0x04)
91 #define MCF5272_UART_UCR_RX_DISABLED (0x02)
92 #define MCF5272_UART_UCR_RX_ENABLED (0x01)
94 #define MCF5272_UART_UCCR_COS (0x10)
95 #define MCF5272_UART_UCCR_CTS (0x01)
97 #define MCF5272_UART_UACR_BRG (0x80)
98 #define MCF5272_UART_UACR_CTMS_TIMER (0x60)
99 #define MCF5272_UART_UACR_IEC (0x01)
101 #define MCF5272_UART_UISR_COS (0x80)
102 #define MCF5272_UART_UISR_ABC (0x40)
103 #define MCF5272_UART_UISR_DB (0x04)
104 #define MCF5272_UART_UISR_RXRDY (0x02)
105 #define MCF5272_UART_UISR_TXRDY (0x01)
107 #define MCF5272_UART_UIMR_COS (0x80)
108 #define MCF5272_UART_UIMR_ABC (0x40)
109 #define MCF5272_UART_UIMR_DB (0x04)
110 #define MCF5272_UART_UIMR_FFULL (0x02)
111 #define MCF5272_UART_UIMR_TXRDY (0x01)
113 typedef unsigned char uint8; /* 8 bits */
114 typedef unsigned short int uint16; /* 16 bits */
115 typedef unsigned long int uint32; /* 32 bits */
117 typedef signed char int8; /* 8 bits */
118 typedef signed short int int16; /* 16 bits */
119 typedef signed long int int32; /* 32 bits */
121 #ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0
122 unsigned long MCF5272_uart_get_channel_0_baud_rate(void);
123 #endif /* CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL0 */
125 #ifdef CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1
126 unsigned long MCF5272_uart_get_channel_1_baud_rate(void);
127 #endif /* CYGPKG_IO_SERIAL_MCF5272_UART_CHANNEL1 */
129 #endif /* _SER_MCF5272_H_ */