packages/devs/serial/sh/sci/v2_0/src/sh_sci_serial.c

   1 //==========================================================================
   2 //
   3 //      io/serial/sh/sh_sci_serial.c
   4 //
   5 //      SH Serial SCI I/O Interface Module (interrupt driven)
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //==========================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):   jskov
  44 // Contributors:gthomas, jskov
  45 // Date:        1999-05-24
  46 // Purpose:     SH Serial I/O module (interrupt driven version)
  47 // Description:
  48 //
  49 // Note: Since interrupt sources from the same SCI channel share the same
  50 //       interrupt level, there is no risk of races when altering the
  51 //       channel's control register from ISRs and DSRs. However, when
  52 //       altering the control register from user-level code, interrupts
  53 //       must be disabled while the register is being accessed.
  54 //
  55 // FIXME: Receiving in polled mode prevents duplex transfers from working for
  56 //        some reason.
  57 //####DESCRIPTIONEND####
  58 //==========================================================================
  59
  60 #include <pkgconf/io_serial.h>
  61 #include <pkgconf/io.h>
  62
  63 // FIXME: This is necessary since the SCIF driver may be overriding
  64 // CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two
  65 // different drivers.
  66 #include <pkgconf/io_serial_sh_sci.h>
  67
  68 #include <cyg/io/io.h>
  69 #include <cyg/hal/hal_intr.h>
  70 #include <cyg/io/devtab.h>
  71 #include <cyg/infra/diag.h>
  72 #include <cyg/io/serial.h>
  73
  74 #include <cyg/hal/sh_regs.h>
  75
  76 // Only compile driver if an inline file with driver details was selected.
  77 #ifdef CYGDAT_IO_SERIAL_SH_SCI_INL
  78
  79 // Find the SCI controller register layout from the SCI0 definitions
  80 #if defined(CYGARC_REG_SCI_SCSMR0)
  81 # define SCI_SCSMR                (CYGARC_REG_SCI_SCSMR0-CYGARC_REG_SCI_SCSMR0) // serial mode register
  82 # define SCI_SCBRR                (CYGARC_REG_SCI_SCBRR0-CYGARC_REG_SCI_SCSMR0) // bit rate register
  83 # define SCI_SCSCR                (CYGARC_REG_SCI_SCSCR0-CYGARC_REG_SCI_SCSMR0) // serial control register
  84 # define SCI_SCTDR                (CYGARC_REG_SCI_SCTDR0-CYGARC_REG_SCI_SCSMR0) // transmit data register
  85 # define SCI_SCSSR                (CYGARC_REG_SCI_SCSSR0-CYGARC_REG_SCI_SCSMR0) // serial status register
  86 # define SCI_SCRDR                (CYGARC_REG_SCI_SCRDR0-CYGARC_REG_SCI_SCSMR0) // receive data register
  87 # define SCI_SCSPTR               (CYGARC_REG_SCI_SCSPTR0-CYGARC_REG_SCI_SCSMR0)// serial port register
  88 #elif defined(CYGARC_REG_SCI_SCSMR)
  89 # define SCI_SCSMR                (CYGARC_REG_SCI_SCSMR-CYGARC_REG_SCI_SCSMR) // serial mode register
  90 # define SCI_SCBRR                (CYGARC_REG_SCI_SCBRR-CYGARC_REG_SCI_SCSMR) // bit rate register
  91 # define SCI_SCSCR                (CYGARC_REG_SCI_SCSCR-CYGARC_REG_SCI_SCSMR) // serial control register
  92 # define SCI_SCTDR                (CYGARC_REG_SCI_SCTDR-CYGARC_REG_SCI_SCSMR) // transmit data register
  93 # define SCI_SCSSR                (CYGARC_REG_SCI_SCSSR-CYGARC_REG_SCI_SCSMR) // serial status register
  94 # define SCI_SCRDR                (CYGARC_REG_SCI_SCRDR-CYGARC_REG_SCI_SCSMR) // receive data register
  95 # define SCI_SCSPTR               (CYGARC_REG_SCI_SCSPTR-CYGARC_REG_SCI_SCSMR) // serial port register
  96 #else
  97 # error "Missing register offsets"
  98 #endif
  99
 100 static short select_word_length[] = {
 101     -1,
 102     -1,
 103     CYGARC_REG_SCI_SCSMR_CHR,               // 7 bits
 104     0                                   // 8 bits
 105 };
 106
 107 static short select_stop_bits[] = {
 108     -1,
 109     0,                                  // 1 stop bit
 110     -1,
 111     CYGARC_REG_SCI_SCSMR_STOP               // 2 stop bits
 112 };
 113
 114 static short select_parity[] = {
 115     0,                                  // No parity
 116     CYGARC_REG_SCI_SCSMR_PE,                // Even parity
 117     CYGARC_REG_SCI_SCSMR_PE|CYGARC_REG_SCI_SCSMR_OE, // Odd parity
 118     -1,
 119     -1
 120 };
 121
 122 static unsigned short select_baud[] = {
 123     0,    // Unused
 124     CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50),
 125     CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75),
 126     CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110),
 127     CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134),
 128     CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150),
 129     CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200),
 130     CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300),
 131     CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600),
 132     CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200),
 133     CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800),
 134     CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400),
 135     CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600),
 136     CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800),
 137     CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200),
 138     CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600),
 139     CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400),
 140     CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200),
 141     CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400),
 142     CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600),
 143     CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200),
 144     CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400)
 145 };
 146
 147
 148 typedef struct sh_sci_info {
 149     CYG_ADDRWORD   data;                // Pointer to data register
 150
 151     CYG_WORD       er_int_num,          // Error interrupt number
 152                    rx_int_num,          // Receive interrupt number
 153                    tx_int_num;          // Transmit interrupt number
 154
 155     CYG_ADDRWORD   ctrl_base;           // Base address of SCI controller
 156
 157     cyg_interrupt  serial_er_interrupt,
 158                    serial_rx_interrupt,
 159                    serial_tx_interrupt;
 160     cyg_handle_t   serial_er_interrupt_handle,
 161                    serial_rx_interrupt_handle,
 162                    serial_tx_interrupt_handle;
 163
 164     bool           tx_enabled;
 165 } sh_sci_info;
 166
 167 static bool sh_serial_init(struct cyg_devtab_entry *tab);
 168 static bool sh_serial_putc(serial_channel *chan, unsigned char c);
 169 static Cyg_ErrNo sh_serial_lookup(struct cyg_devtab_entry **tab,
 170                                    struct cyg_devtab_entry *sub_tab,
 171                                    const char *name);
 172 static unsigned char sh_serial_getc(serial_channel *chan);
 173 static Cyg_ErrNo sh_serial_set_config(serial_channel *chan, cyg_uint32 key,
 174                                       const void *xbuf, cyg_uint32 *len);
 175 static void sh_serial_start_xmit(serial_channel *chan);
 176 static void sh_serial_stop_xmit(serial_channel *chan);
 177
 178 static cyg_uint32 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data);
 179 static void       sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count,
 180                                    cyg_addrword_t data);
 181 static cyg_uint32 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data);
 182 static void       sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count,
 183                                    cyg_addrword_t data);
 184 static cyg_uint32 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data);
 185 static void       sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count,
 186                                    cyg_addrword_t data);
 187
 188 static SERIAL_FUNS(sh_serial_funs,
 189                    sh_serial_putc,
 190                    sh_serial_getc,
 191                    sh_serial_set_config,
 192                    sh_serial_start_xmit,
 193                    sh_serial_stop_xmit
 194     );
 195
 196 #include CYGDAT_IO_SERIAL_SH_SCI_INL
 197
 198 // Internal function to actually configure the hardware to desired baud rate,
 199 // etc.
 200 static bool
 201 sh_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config,
 202                       bool init)
 203 {
 204     cyg_uint16 baud_divisor = select_baud[new_config->baud];
 205     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 206     cyg_uint8 _scr, _smr;
 207
 208     // Check configuration request
 209     if ((-1 == select_word_length[(new_config->word_length -
 210                                   CYGNUM_SERIAL_WORD_LENGTH_5)])
 211         || -1 == select_stop_bits[new_config->stop]
 212         || -1 == select_parity[new_config->parity]
 213         || baud_divisor == 0)
 214         return false;
 215
 216     // Disable SCI interrupts while changing hardware
 217     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 218     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, 0);
 219
 220     // Set databits, stopbits and parity.
 221     _smr = select_word_length[(new_config->word_length -
 222                                CYGNUM_SERIAL_WORD_LENGTH_5)] |
 223         select_stop_bits[new_config->stop] |
 224         select_parity[new_config->parity];
 225     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr);
 226
 227     // Set baud rate.
 228     _smr &= ~CYGARC_REG_SCI_SCSMR_CKSx_MASK;
 229     _smr |= baud_divisor >> 8;
 230     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr);
 231     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCBRR, baud_divisor & 0xff);
 232
 233     // Clear the status register.
 234     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, 0);
 235
 236     if (init) {
 237         // Always enable transmitter and receiver.
 238         _scr = CYGARC_REG_SCI_SCSCR_TE | CYGARC_REG_SCI_SCSCR_RE;
 239
 240         if (chan->out_cbuf.len != 0)
 241             _scr |= CYGARC_REG_SCI_SCSCR_TIE; // enable tx interrupts
 242
 243         if (chan->in_cbuf.len != 0)
 244             _scr |= CYGARC_REG_SCI_SCSCR_RIE; // enable rx interrupts
 245     }
 246
 247     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 248
 249     if (new_config != &chan->config) {
 250         chan->config = *new_config;
 251     }
 252     return true;
 253 }
 254
 255 // Function to initialize the device.  Called at bootstrap time.
 256 static bool
 257 sh_serial_init(struct cyg_devtab_entry *tab)
 258 {
 259     serial_channel *chan = (serial_channel *)tab->priv;
 260     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 261 #ifdef CYGDBG_IO_INIT
 262     diag_printf("SH SERIAL init - dev: %x.%d\n",
 263                 sh_chan->data, sh_chan->rx_int_num);
 264 #endif
 265     // Really only required for interrupt driven devices
 266     (chan->callbacks->serial_init)(chan);
 267
 268     if (chan->out_cbuf.len != 0) {
 269         cyg_drv_interrupt_create(sh_chan->tx_int_num,
 270                                  3,
 271                                  (cyg_addrword_t)chan, // Data item passed to interrupt handler
 272                                  sh_serial_tx_ISR,
 273                                  sh_serial_tx_DSR,
 274                                  &sh_chan->serial_tx_interrupt_handle,
 275                                  &sh_chan->serial_tx_interrupt);
 276         cyg_drv_interrupt_attach(sh_chan->serial_tx_interrupt_handle);
 277         cyg_drv_interrupt_unmask(sh_chan->tx_int_num);
 278         sh_chan->tx_enabled = false;
 279     }
 280     if (chan->in_cbuf.len != 0) {
 281         // Receive interrupt
 282         cyg_drv_interrupt_create(sh_chan->rx_int_num,
 283                                  3,
 284                                  (cyg_addrword_t)chan, // Data item passed to interrupt handler
 285                                  sh_serial_rx_ISR,
 286                                  sh_serial_rx_DSR,
 287                                  &sh_chan->serial_rx_interrupt_handle,
 288                                  &sh_chan->serial_rx_interrupt);
 289         cyg_drv_interrupt_attach(sh_chan->serial_rx_interrupt_handle);
 290         // Receive error interrupt
 291         cyg_drv_interrupt_create(sh_chan->er_int_num,
 292                                  3,
 293                                  (cyg_addrword_t)chan, // Data item passed to interrupt handler
 294                                  sh_serial_er_ISR,
 295                                  sh_serial_er_DSR,
 296                                  &sh_chan->serial_er_interrupt_handle,
 297                                  &sh_chan->serial_er_interrupt);
 298         cyg_drv_interrupt_attach(sh_chan->serial_er_interrupt_handle);
 299         // This unmasks both interrupt sources.
 300         cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
 301     }
 302     sh_serial_config_port(chan, &chan->config, true);
 303     return true;
 304 }
 305
 306 // This routine is called when the device is "looked" up (i.e. attached)
 307 static Cyg_ErrNo
 308 sh_serial_lookup(struct cyg_devtab_entry **tab,
 309                   struct cyg_devtab_entry *sub_tab,
 310                   const char *name)
 311 {
 312     serial_channel *chan = (serial_channel *)(*tab)->priv;
 313
 314     // Really only required for interrupt driven devices
 315     (chan->callbacks->serial_init)(chan);
 316     return ENOERR;
 317 }
 318
 319 // Send a character to the device output buffer.
 320 // Return 'true' if character is sent to device
 321 static bool
 322 sh_serial_putc(serial_channel *chan, unsigned char c)
 323 {
 324     cyg_uint8 _ssr;
 325     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 326
 327     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
 328     if (_ssr & CYGARC_REG_SCI_SCSSR_TDRE) {
 329 // Transmit buffer is empty
 330         HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCTDR, c);
 331         // Clear empty flag.
 332         HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
 333                         CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_TDRE);
 334         return true;
 335     } else {
 336 // No space
 337         return false;
 338     }
 339 }
 340
 341 // Fetch a character from the device input buffer, waiting if necessary
 342 static unsigned char
 343 sh_serial_getc(serial_channel *chan)
 344 {
 345     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 346     unsigned char c;
 347     cyg_uint8 _ssr;
 348
 349     do {
 350         HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
 351     } while ((_ssr & CYGARC_REG_SCI_SCSSR_RDRF) == 0);
 352
 353     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, c);
 354
 355     // Clear buffer full flag.
 356     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
 357                     CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF);
 358
 359     return c;
 360 }
 361
 362 // Set up the device characteristics; baud rate, etc.
 363 static Cyg_ErrNo
 364 sh_serial_set_config(serial_channel *chan, cyg_uint32 key,
 365                      const void *xbuf, cyg_uint32 *len)
 366 {
 367     switch (key) {
 368     case CYG_IO_SET_CONFIG_SERIAL_INFO:
 369       {
 370         cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
 371         if ( *len < sizeof(cyg_serial_info_t) ) {
 372             return -EINVAL;
 373         }
 374         *len = sizeof(cyg_serial_info_t);
 375         if ( true != sh_serial_config_port(chan, config, false) )
 376             return -EINVAL;
 377       }
 378       break;
 379     default:
 380         return -EINVAL;
 381     }
 382     return ENOERR;
 383 }
 384
 385 // Enable the transmitter on the device
 386 static void
 387 sh_serial_start_xmit(serial_channel *chan)
 388 {
 389     cyg_uint8 _scr;
 390     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 391
 392     sh_chan->tx_enabled = true;
 393
 394     // Mask the interrupts (all sources of the unit) while changing
 395     // the CR since a rx interrupt in the middle of this would result
 396     // in a bad CR state.
 397     cyg_drv_interrupt_mask(sh_chan->rx_int_num);
 398
 399     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 400     _scr |= CYGARC_REG_SCI_SCSCR_TIE;       // Enable xmit interrupt
 401     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 402
 403     cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
 404 }
 405
 406 // Disable the transmitter on the device
 407 static void
 408 sh_serial_stop_xmit(serial_channel *chan)
 409 {
 410     cyg_uint8 _scr;
 411     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 412
 413     sh_chan->tx_enabled = false;
 414
 415     // Mask the interrupts (all sources of the unit) while changing
 416     // the CR since a rx interrupt in the middle of this would result
 417     // in a bad CR state.
 418     cyg_drv_interrupt_mask(sh_chan->rx_int_num);
 419
 420     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 421     _scr &= ~CYGARC_REG_SCI_SCSCR_TIE;      // Disable xmit interrupt
 422     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 423
 424     cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
 425 }
 426
 427 // Serial I/O - low level tx interrupt handler (ISR)
 428 static cyg_uint32
 429 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data)
 430 {
 431     serial_channel *chan = (serial_channel *)data;
 432     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 433     cyg_uint8 _scr;
 434
 435     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 436     _scr &= ~CYGARC_REG_SCI_SCSCR_TIE;      // mask out tx interrupts
 437     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 438
 439     return CYG_ISR_CALL_DSR;  // Cause DSR to be run
 440 }
 441
 442 // Serial I/O - high level tx interrupt handler (DSR)
 443 static void
 444 sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
 445 {
 446     serial_channel *chan = (serial_channel *)data;
 447     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 448
 449     (chan->callbacks->xmt_char)(chan);
 450
 451     if (sh_chan->tx_enabled) {
 452         cyg_uint8 _scr;
 453
 454         HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 455         _scr |= CYGARC_REG_SCI_SCSCR_TIE;       // unmask tx interrupts
 456         HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 457     }
 458 }
 459
 460 // Serial I/O - low level RX interrupt handler (ISR)
 461 static cyg_uint32
 462 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data)
 463 {
 464     serial_channel *chan = (serial_channel *)data;
 465     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 466     cyg_uint8 _scr;
 467
 468     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 469     _scr &= ~CYGARC_REG_SCI_SCSCR_RIE;      // mask rx interrupts
 470     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 471     return CYG_ISR_CALL_DSR;  // Cause DSR to be run
 472 }
 473
 474 // Serial I/O - high level rx interrupt handler (DSR)
 475 static void
 476 sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
 477 {
 478     serial_channel *chan = (serial_channel *)data;
 479     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 480     cyg_uint8 _ssr, _scr;
 481
 482     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
 483     if (_ssr & CYGARC_REG_SCI_SCSSR_RDRF) {
 484         cyg_uint8 _c;
 485         HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, _c);
 486         // Clear buffer full flag.
 487         HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
 488                         CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF);
 489
 490         (chan->callbacks->rcv_char)(chan, _c);
 491     }
 492
 493     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 494     _scr |= CYGARC_REG_SCI_SCSCR_RIE;       // unmask rx interrupts
 495     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 496 }
 497
 498 static volatile int sh_serial_error_orer = 0;
 499 static volatile int sh_serial_error_fer = 0;
 500 static volatile int sh_serial_error_per = 0;
 501
 502 // Serial I/O - low level error interrupt handler (ISR)
 503 static cyg_uint32
 504 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data)
 505 {
 506     serial_channel *chan = (serial_channel *)data;
 507     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 508     cyg_uint8 _scr;
 509
 510     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 511     _scr &= ~CYGARC_REG_SCI_SCSCR_RIE;      // mask rx interrupts
 512     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 513     return CYG_ISR_CALL_DSR;            // Cause DSR to be run
 514 }
 515
 516 // Serial I/O - high level error interrupt handler (DSR)
 517 static void
 518 sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
 519 {
 520     serial_channel *chan = (serial_channel *)data;
 521     sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
 522     cyg_uint8 _ssr, _ssr2, _scr;
 523
 524     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
 525     _ssr2 = CYGARC_REG_SCI_SCSSR_CLEARMASK;
 526
 527     if (_ssr & CYGARC_REG_SCI_SCSSR_ORER) {
 528         _ssr2 &= ~CYGARC_REG_SCI_SCSSR_ORER;
 529         sh_serial_error_orer++;
 530     }
 531     if (_ssr & CYGARC_REG_SCI_SCSSR_FER) {
 532         _ssr2 &= ~CYGARC_REG_SCI_SCSSR_FER;
 533         sh_serial_error_fer++;
 534     }
 535     if (_ssr & CYGARC_REG_SCI_SCSSR_PER) {
 536         _ssr2 &= ~CYGARC_REG_SCI_SCSSR_PER;
 537         sh_serial_error_per++;
 538     }
 539     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr2);
 540
 541     HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 542     _scr |= CYGARC_REG_SCI_SCSCR_RIE;       // unmask rx interrupts
 543     HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
 544 }
 545
 546 #endif // ifdef CYGDAT_IO_SERIAL_SH_SCI_INL