1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
4 //=============================================================================
8 // HAL cache control API
10 //=============================================================================
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43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): nickg, gthomas
47 // Contributors: nickg, gthomas
49 // Purpose: Cache control API
50 // Description: The macros defined here provide the HAL APIs for handling
51 // cache control operations.
53 // #include <cyg/hal/hal_cache.h>
57 //####DESCRIPTIONEND####
59 //=============================================================================
61 #include <cyg/infra/cyg_type.h>
62 #include <cyg/hal/hal_io.h>
64 //-----------------------------------------------------------------------------
65 // Cache dimensions - one unified cache
67 #define HAL_CACHE_UNIFIED
69 #define HAL_UCACHE_SIZE 0x800 // Size of cache in bytes
70 #define HAL_UCACHE_LINE_SIZE 4 // Size of a cache line
71 #define HAL_UCACHE_WAYS 4 // Associativity of the cache
73 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
75 // Cache & SRAM control
76 #define CYG_DEVICE_CCR 0xFFFFA400
77 #define CYG_DEVICE_LSCR 0xFFFFA404
78 #define CYG_DEVICE_CACHE_MEM 0x60000800
80 #define CCR_E 0x01 // Cache enabled
81 #define CCR_S 0x02 // SRAM mode enabled
82 #define CCR_F 0x04 // Flush mode enabled
83 #define CCR_I 0x08 // Invalidate mode
85 #define LCSR_E 0x01 // Local SRAM enabled
86 #define LCSR_L 0x02 // Local SRAM mapped to high memory
88 //-----------------------------------------------------------------------------
89 // Global control of cache
92 #define HAL_UCACHE_ENABLE() \
94 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_E); \
98 #define HAL_UCACHE_DISABLE() \
100 HAL_WRITE_UINT8(CYG_DEVICE_CCR, 0); \
103 // Invalidate the entire cache
104 #define HAL_UCACHE_INVALIDATE_ALL() \
106 register cyg_uint8 old_ccr; \
107 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \
108 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \
109 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \
112 // Synchronize the contents of the cache with memory.
113 #define HAL_UCACHE_SYNC() \
115 register volatile cyg_uint32 *cache_SRAM = \
116 (volatile cyg_uint32*) CYG_DEVICE_CACHE_MEM; \
118 register cyg_uint8 old_ccr; \
119 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \
120 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_F); \
121 for (i = 0; i < HAL_DCACHE_SETS; i++) { \
122 cyg_uint32 tmp = *cache_SRAM++; \
124 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \
125 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \
128 // Query the state of the cache
129 #define HAL_UCACHE_IS_ENABLED(_state_) \
132 HAL_READ_UINT8(CYG_DEVICE_CCR, __ccr); \
133 (_state_) = (CCR_E == __ccr) ? 1 : 0; \
136 // Purge contents of cache
137 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
139 // Set the cache refill burst size
140 //#define HAL_UCACHE_BURST_SIZE(_size_)
142 // Set the cache write mode
143 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
145 //#define HAL_UCACHE_WRITETHRU_MODE 0
146 //#define HAL_UCACHE_WRITEBACK_MODE 1
148 // Load the contents of the given address range into the cache
149 // and then lock the cache so that it stays there.
150 //#define HAL_UCACHE_LOCK(_base_, _size_)
152 // Undo a previous lock operation
153 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
155 // Unlock entire cache
156 //#define HAL_UCACHE_UNLOCK_ALL()
158 //-----------------------------------------------------------------------------
159 // Cache line control
161 // Allocate cache lines for the given address range without reading its
162 // contents from memory.
163 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
165 // Write dirty cache lines to memory and invalidate the cache entries
166 // for the given address range.
167 //#define HAL_UCACHE_FLUSH( _base_ , _size_ )
169 // Invalidate cache lines in the given range without writing to memory.
170 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
172 // Write dirty cache lines to memory for the given address range.
173 //#define HAL_UCACHE_STORE( _base_ , _size_ )
175 // Preread the given range into the cache with the intention of reading
177 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
179 // Preread the given range into the cache with the intention of writing
181 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
183 // Allocate and zero the cache lines associated with the given range.
184 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
186 //-----------------------------------------------------------------------------
188 //-----------------------------------------------------------------------------
189 // Data and instruction cache macros map onto the both-cache macros
191 //-----------------------------------------------------------------------------
192 // Global control of data cache
194 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
195 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
196 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
197 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
199 // Enable the data cache
200 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
202 // Disable the data cache
203 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
205 // Invalidate the entire cache
206 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
208 // Synchronize the contents of the cache with memory.
209 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
211 // Query the state of the data cache
212 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
214 // Set the data cache refill burst size
215 //#define HAL_DCACHE_BURST_SIZE(_size_)
217 // Set the data cache write mode
218 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
220 //#define HAL_DCACHE_WRITETHRU_MODE 0
221 //#define HAL_DCACHE_WRITEBACK_MODE 1
223 // Load the contents of the given address range into the data cache
224 // and then lock the cache so that it stays there.
225 //#define HAL_DCACHE_LOCK(_base_, _size_)
227 // Undo a previous lock operation
228 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
230 // Unlock entire cache
231 //#define HAL_DCACHE_UNLOCK_ALL()
233 //-----------------------------------------------------------------------------
234 // Data cache line control
236 // Allocate cache lines for the given address range without reading its
237 // contents from memory.
238 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
240 // Write dirty cache lines to memory and invalidate the cache entries
241 // for the given address range.
242 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
244 // Invalidate cache lines in the given range without writing to memory.
245 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
247 // Write dirty cache lines to memory for the given address range.
248 //#define HAL_DCACHE_STORE( _base_ , _size_ )
250 // Preread the given range into the cache with the intention of reading
252 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
254 // Preread the given range into the cache with the intention of writing
256 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
258 // Allocate and zero the cache lines associated with the given range.
259 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
261 //-----------------------------------------------------------------------------
262 // Global control of Instruction cache
264 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
265 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
266 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
267 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
269 // Enable the instruction cache
270 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
272 // Disable the instruction cache
273 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
275 // Invalidate the entire cache
276 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
279 // Synchronize the contents of the cache with memory.
280 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
282 // Query the state of the instruction cache
283 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
285 // Set the instruction cache refill burst size
286 //#define HAL_ICACHE_BURST_SIZE(_size_)
288 // Load the contents of the given address range into the instruction cache
289 // and then lock the cache so that it stays there.
291 //#define HAL_ICACHE_LOCK(_base_, _size_)
293 // Undo a previous lock operation
294 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
296 // Unlock entire cache
297 //#define HAL_ICACHE_UNLOCK_ALL()
299 //-----------------------------------------------------------------------------
300 // Instruction cache line control
302 // Invalidate cache lines in the given range without writing to memory.
303 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
305 #endif // ifndef CYGONCE_HAL_CACHE_H
306 // End of hal_cache.h