1 #ifndef CYGONCE_AAED2000_H
2 #define CYGONCE_AAED2000_H
3 /*=============================================================================
7 // Platform specific support (register layout, etc)
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
46 // Contributors: gthomas, jskov
48 // Purpose: Agilent/AAED2000 platform specific support routines
50 // Usage: #include <cyg/hal/aaed2000.h>
52 //####DESCRIPTIONEND####
54 //===========================================================================*/
56 //---------------------------------------------------------------------------
57 // Memory layout details needed by conversion macro
58 #define AAED2000_SDRAM_PHYS_BASE 0xF0000000
59 #define AAED2000_SDRAM_VIRT_BASE 0x00000000
60 #define AAED2000_SDRAM_SIZE 0x02000000
61 #define AAED2000_SDRAM_MASK (AAED2000_SDRAM_SIZE-1)
63 #define AAED2000_FLASH_PHYS_BASE 0x00000000
64 #define AAED2000_FLASH_VIRT_BASE 0x60000000
65 #define AAED2000_FLASH_SIZE 0x02000000
66 #define AAED2000_FLASH_MASK (AAED2000_FLASH_SIZE-1)
68 //---------------------------------------------------------------------------
69 // Clock and state controller
70 #define AAEC_CSC_BLEOI 0x80000410 // battery low end of interrupt
71 #define AAEC_CSC_MCEOI 0x80000414 // media changed end of interrupt
72 #define AAEC_CSC_TEOI 0x80000418 // tick end of interrupt
73 #define AAEC_CSC_CLKSET 0x80000420
75 #define AAEC_CSC_CLKSET_PLL 0x80000000
76 #define AAEC_CSC_CLKSET_SMCROM 0x01000000
77 #define AAEC_CSC_CLKSET_PS(_n_) ((_n_)<<18) // values 0-3
78 #define AAEC_CSC_CLKSET_PCLKDIV(_n_) ((_n_)<<16) // values 0-3
79 #define AAEC_CSC_CLKSET_MAINDIV2(_n_) ((_n_)<<11) // values 0-31
80 #define AAEC_CSC_CLKSET_MAINDIV1(_n_) ((_n_)<<7) // values 0-15
81 #define AAEC_CSC_CLKSET_PREDIV(_n_) ((_n_)<<2) // values 0-31
82 #define AAEC_CSC_CLKSET_HCLKDIV(_n_) ((_n_)) // values 0-3
85 #define CYGNUM_HAL_ARM_AAED2000_BUS_CLOCK_MHZ ((CYGNUM_HAL_ARM_AAED2000_BUS_CLOCK+500000)/1000000)
87 #define AAEC_CSC_CLKSET_INIT \
88 ( AAEC_CSC_CLKSET_HCLKDIV(CYGNUM_HAL_ARM_AAED2000_CLOCK_HCLKDIV) \
89 | AAEC_CSC_CLKSET_PREDIV(CYGNUM_HAL_ARM_AAED2000_CLOCK_PREDIV) \
90 | AAEC_CSC_CLKSET_MAINDIV1(CYGNUM_HAL_ARM_AAED2000_CLOCK_MAINDIV1) \
91 | AAEC_CSC_CLKSET_MAINDIV2(CYGNUM_HAL_ARM_AAED2000_CLOCK_MAINDIV2) \
92 | AAEC_CSC_CLKSET_PCLKDIV(CYGNUM_HAL_ARM_AAED2000_CLOCK_PCLKDIV) \
93 | AAEC_CSC_CLKSET_PS(CYGNUM_HAL_ARM_AAED2000_CLOCK_PS) \
94 | AAEC_CSC_CLKSET_SMCROM)
96 //---------------------------------------------------------------------------
97 // Interrupt controller
98 #define AAEC_INT_SR 0x80000500
99 #define AAEC_INT_RSR 0x80000504 // Raw [unmasked] interrupt status
100 #define AAEC_INT_ENS 0x80000508
101 #define AAEC_INT_ENC 0x8000050c
102 #define AAEC_INT_TEST1 0x80000514
103 #define AAEC_INT_TEST2 0x80000518
105 #define AAEC_INTS_T3OI CYGNUM_HAL_INTERRUPT_TC3OI // Timer #3 overflow
107 //---------------------------------------------------------------------------
109 #define AAEC_UART1 0x80000600
110 #define AAEC_UART2 0x80000700
111 #define AAEC_UART3 0x80000800
113 #define AAEC_UART2_UMS2EOI 0x80000714 // modem end of interrupt
114 #define AAEC_UART2_UMS3EOI 0x80000814 // modem end of interrupt
116 #define AAEC_UART_DATA 0x0000 // Data/FIFO register
117 #define AAEC_UART_LCR 0x0004 // Control register
118 #define AAEC_UART_LCR_BRK 0x0001 // Send break
119 #define AAEC_UART_LCR_PEN 0x0002 // Enable parity
120 #define AAEC_UART_LCR_EP 0x0004 // Odd/Even parity
121 #define AAEC_UART_LCR_S2 0x0008 // One/Two stop bits
122 #define AAEC_UART_LCR_FIFO 0x0010 // Enable FIFO
123 #define AAEC_UART_LCR_WL5 0x0000 // Word length - 5 bits
124 #define AAEC_UART_LCR_WL6 0x0020 // Word length - 6 bits
125 #define AAEC_UART_LCR_WL7 0x0040 // Word length - 7 bits
126 #define AAEC_UART_LCR_WL8 0x0060 // Word length - 8 bits
127 #define AAEC_UART_BAUD 0x0008 // Baud rate
128 #define AAEC_UART_CTRL 0x000C // Control register
129 #define AAEC_UART_CTRL_ENAB 0x0001 // Enable uart
130 #define AAEC_UART_CTRL_SIR 0x0002 // Enable SIR IrDA
131 #define AAEC_UART_CTRL_SIRLP 0x0004 // Enable low power IrDA
132 #define AAEC_UART_CTRL_RXP 0x0008 // Receive pin polarity
133 #define AAEC_UART_CTRL_TXP 0x0010 // Transmit pin polarity
134 #define AAEC_UART_CTRL_MXP 0x0020 // Modem pin polarity
135 #define AAEC_UART_CTRL_LOOP 0x0040 // Loopback mode
136 #define AAEC_UART_CTRL_SIRBD 0x0080 // blanking disable
137 #define AAEC_UART_STATUS 0x0010 // Status
138 #define AAEC_UART_STATUS_CTS 0x0001 // Clear-to-send status
139 #define AAEC_UART_STATUS_DSR 0x0002 // Data-set-ready status
140 #define AAEC_UART_STATUS_DCD 0x0004 // Data-carrier-detect status
141 #define AAEC_UART_STATUS_TxBSY 0x0008 // Transmitter busy
142 #define AAEC_UART_STATUS_RxFE 0x0010 // Receive FIFO empty
143 #define AAEC_UART_STATUS_TxFF 0x0020 // Transmit FIFO full
144 #define AAEC_UART_STATUS_RxFF 0x0040 // Receive FIFO full
145 #define AAEC_UART_STATUS_TxFE 0x0080 // Transmit FIFO empty
146 #define AAEC_UART_INT 0x0014 // Interrupt status
147 #define AAEC_UART_INTM 0x0018 // Interrupt mask register
148 #define AAEC_UART_INTRES 0x001c // Interrupt result (masked interrupt status)
149 #define AAEC_UART_INT_RIS 0x0001 // Rx interrupt
150 #define AAEC_UART_INT_TIS 0x0002 // Tx interrupt
151 #define AAEC_UART_INT_MIS 0x0004 // Modem status interrupt
152 #define AAEC_UART_INT_RTIS 0x0008 // Rx timeout interrupt
153 //#define AAEC_UART_MCTRL 0x0100 // Modem control
155 //---------------------------------------------------------------------------
157 #define AAEC_PUMP_CONTROL 0x80000900 // Control
158 #define AAEC_PUMP_FREQUENCY 0x80000908 // Frequency
160 //---------------------------------------------------------------------------
162 #define AAEC_COD_CDEOI 0x80000a0c // codec end of interrupt
164 //---------------------------------------------------------------------------
165 // Synchronous Serial Peripheral (SSP)
166 #define AAEC_SSP_CR0 0x80000B00 // Control Register 0
167 #define AAEC_SSP_CR0_SCR 8 // Serial clock rate - Bits 15..8
168 #define AAEC_SSP_CR0_SCR_MASK (0x7F<<AAEC_SSP_CR0_SCR)
169 #define AAEC_SSP_CR0_SSE 7 // SSP enable/disable
170 #define AAEC_SSP_CR0_SSE_MASK (1<<AAEC_SSP_CR0_SSE)
171 #define AAEC_SSP_CR0_SSE_ON 1
172 #define AAEC_SSP_CR0_SSE_OFF 0
173 #define AAEC_SSP_CR0_FRF 4 // Frame format
174 #define AAEC_SSP_CR0_FRF_MASK (0x3<<AAEC_SSP_CR0_FRF)
175 #define AAEC_SSP_CR0_FRF_MOT 0 // Motorola SPI
176 #define AAEC_SSP_CR0_FRF_TI 1 // TI synchronous serial frame
177 #define AAEC_SSP_CR0_FRF_NAT 2 // National microwire
178 #define AAEC_SSP_CR0_SIZE 0 // Data size
179 #define AAEC_SSP_CR0_SIZE_MASK (0xF<<AAEC_SSP_CR0_SIZE)
180 #define AAEC_SSP_CR1 0x80000B04 // Control Register 1
181 #define AAEC_SSP_CR1_TXIDLE 7 // Tx idle interrupt
182 #define AAEC_SSP_CR1_FEN 6 // FIFO enable
183 #define AAEC_SSP_CR1_RORIE 5 // Rx FIFO overrun interrupt
184 #define AAEC_SSP_CR1_SPH 4 // SCLK phase
185 #define AAEC_SSP_CR1_SPO 3 // SCLK polarity
186 #define AAEC_SSP_CR1_LBM 2 // Lookpback
187 #define AAEC_SSP_CR1_TIE 1 // Tx interrupt
188 #define AAEC_SSP_CR1_RIE 0 // Rx Interrupt
189 #define AAEC_SSP_IIR 0x80000B08 // Interrupt ID register (read)
190 #define AAEC_SSP_IIR_TXIDLE 7 // Tx idle interrupt
191 #define AAEC_SSP_IIR_ROR 6 // Rx overrun
192 #define AAEC_SSP_IIR_TI 1 // Tx FIFO less than half full
193 #define AAEC_SSP_IIR_RI 0 // Rx FIFO more than half full
194 #define AAEC_SSP_ICR 0x80000B08 // Interrupt Clear register (write)
195 #define AAEC_SSP_DR 0x80000B0C // Data [FIFO] register
196 #define AAEC_SSP_CPSR 0x80000B10 // Clock prescale
197 #define AAEC_SSP_SR 0x80000B14 // Status register
198 #define AAEC_SSP_SR_RFF 8 // Rx FIFO full
199 #define AAEC_SSP_SR_TFE 7 // Tx FIFO empty
200 #define AAEC_SSP_SR_ROR 6 // Rx FIFO overrun
201 #define AAEC_SSP_SR_RHF 5 // Rx FIFO half full
202 #define AAEC_SSP_SR_THE 4 // Tx FIFO half empty
203 #define AAEC_SSP_SR_BSY 3 // SSP is busy
204 #define AAEC_SSP_SR_RNE 2 // Rx FIFO not empty
205 #define AAEC_SSP_SR_TNF 1 // Tx FIFO not full
207 //---------------------------------------------------------------------------
209 #define AAEC_TMR_T1_BASE 0x80000C00 // Timer #1 - preload
210 #define AAEC_TMR_T1LOAD 0x80000C00 // Timer #1 - preload
211 #define AAEC_TMR_T1VALUE 0x80000C04 // Timer #1 - current value
212 #define AAEC_TMR_T1CONTROL 0x80000C08 // Timer #1 - control
213 #define AAEC_TMR_T1EOI 0x80000C0C // Timer #1 - clear [end] interrupt
214 #define AAEC_TMR_T2LOAD 0x80000C20 // Timer #2 - preload
215 #define AAEC_TMR_T2VALUE 0x80000C24 // Timer #2 - current value
216 #define AAEC_TMR_T2CONTROL 0x80000C28 // Timer #2 - control
217 #define AAEC_TMR_T2EOI 0x80000C2C // Timer #2 - clear [end] interrupt
218 #define AAEC_TMR_BZCONT 0x80000C40
219 #define AAEC_TMR_T3LOAD 0x80000C80 // Timer #3 - preload
220 #define AAEC_TMR_T3VALUE 0x80000C84 // Timer #3 - current value
221 #define AAEC_TMR_T3CONTROL 0x80000C88 // Timer #3 - control
222 #define AAEC_TMR_T3EOI 0x80000C8C // Timer #3 - clear [end] interrupt
224 #define AAEC_TMR_TxLOAD_OFFSET 0
225 #define AAEC_TMR_TxVALUE_OFFSET 4
226 #define AAEC_TMR_TxCONTROL_OFFSET 8
227 #define AAEC_TMR_TxEOI_OFFSET 12
229 #define AAEC_TMR_TxCONTROL_ENABLE (1<<7) // Enable (start) timer
230 #define AAEC_TMR_TxCONTROL_MODE (1<<6) // Operating mode
231 #define AAEC_TMR_TxCONTROL_MODE_FREE (0x00&AAEC_TMR_TxCONTROL_MODE)
232 #define AAEC_TMR_TxCONTROL_MODE_PERIODIC (0xFF&AAEC_TMR_TxCONTROL_MODE)
233 #define AAEC_TMR_TxCONTROL_CLKSEL (1<<3) // Clock select (timer 1,2)
234 #define AAEC_TMR_TxCONTROL_508KHZ (1<<3)
235 #define AAEC_TMR_TxCONTROL_2KHZ (0<<3)
237 #define AAEC_TMR_TxCONTROL_508KHZ_uS(_n_) ((_n_)*508000/1000000)
239 //---------------------------------------------------------------------------
241 #define AAEC_RTC_RTCEOI 0x80000d10 // RTC end of interrupt
243 //---------------------------------------------------------------------------
245 #define AAEC_PCDR 0x80000e08
246 #define AAEC_PBDDR 0x80000e14
247 #define AAEC_PCCDR 0x80000e18
248 #define AAEC_KSCAN 0x80000e28
249 #define AAEC_PINMUX 0x80000e2c
250 #define AAEC_PFDR 0x80000e30
251 #define AAEC_PFDDR 0x80000e34
252 #define AAEC_GPIO_INT_TYPE1 0x80000e4c
253 #define AAEC_GPIO_INT_TYPE2 0x80000e50
254 #define AAEC_GPIO_FEOI 0x80000e54
255 #define AAEC_GPIO_INTEN 0x80000e58
256 #define AAEC_GPIO_INT_STATUS 0x80000e5c
257 #define AAEC_PINMUX_UART3CON 0x00000008
258 #define AAEC_PINMUX_CODECON 0x00000004
259 #define AAEC_PINMUX_PD0CON 0x00000002
260 #define AAEC_PINMUX_PE0CON 0x00000001
263 //---------------------------------------------------------------------------
264 // Static memory controller
265 #define AAEC_SMCBCR0 0x80002000
266 #define AAEC_SMCBCR1 0x80002004
267 #define AAEC_SMCBCR2 0x80002008
268 #define AAEC_SMCBCR3 0x8000200c
270 #define AAEC_SMCBCR_MW8 0x00000000
271 #define AAEC_SMCBCR_MW16 0x10000000
272 #define AAEC_SMCBCR_MW32 0x30000000
273 #define AAEC_SMCBCR_PME 0x08000000
274 #define AAEC_SMCBCR_WP 0x04000000
275 #define AAEC_SMCBCR_WPERR 0x02000000
276 #define AAEC_SMCBCR_WST(_n_) (((((_n_)-1)&0x1f)<<11) | ((((_n_)-1)&0x1f)<<5)) // for n 1-32
277 #define AAEC_SMCBCR_IDCY(_n_) ((((_n_)-1)&0x0f)<<0) // for n 1-16
279 // These settings come from the Agilent startup.s file
280 // [note, the WST values match their values, not the comments]
281 // CS0: Flash, access=90ns, hold=30ns
282 // CS1: ethernet, access=162ns, hold=47ns
283 // CS2: GPIO, access=14ns, hold=14ns
284 #if (75 == CYGNUM_HAL_ARM_AAED2000_BUS_CLOCK_MHZ)
291 #elif (83 == CYGNUM_HAL_ARM_AAED2000_BUS_CLOCK_MHZ)
299 # error "Unsupported clocking"
303 //---------------------------------------------------------------------------
304 // Synchronous memory controller
305 #define AAEC_SMC_GLOBAL 0x80002404
306 #define AAEC_SMC_REFRESH_TIME 0x80002408
307 #define AAEC_SMC_BOOT_STATUS 0x8000240c
308 #define AAEC_SMC_DEV0 0x80002410
309 #define AAEC_SMC_DEV1 0x80002414
310 #define AAEC_SMC_DEV2 0x80002418
311 #define AAEC_SMC_DEV3 0x8000241c
313 #define AAEC_SMC_GLOBAL_CKE 0x80000000
314 #define AAEC_SMC_GLOBAL_CS 0x40000000
315 #define AAEC_SMC_GLOBAL_LCR 0x00000040
316 #define AAEC_SMC_GLOBAL_BUSY 0x00000020
317 #define AAEC_SMC_GLOBAL_MRS 0x00000002
318 #define AAEC_SMC_GLOBAL_INIT 0x00000001
320 #define AAEC_SMC_GLOBAL_CMD_NOP (AAEC_SMC_GLOBAL_INIT|AAEC_SMC_GLOBAL_MRS)
321 #define AAEC_SMC_GLOBAL_CMD_PREALL (AAEC_SMC_GLOBAL_INIT)
322 #define AAEC_SMC_GLOBAL_CMD_MODE (AAEC_SMC_GLOBAL_MRS)
323 #define AAEC_SMC_GLOBAL_CMD_ENABLE (AAEC_SMC_GLOBAL_CKE)
326 #define AAEC_SMC_DEV_AUTOP 0x01000000
327 #define AAEC_SMC_DEV_RAS_2 0x00200000
328 #define AAEC_SMC_DEV_RAS_3 0x00300000
329 #define AAEC_SMC_DEV_WBL_4 0x00080000
330 #define AAEC_SMC_DEV_WBL_1 0x00000000
331 #define AAEC_SMC_DEV_CASLAT(_n_) (((_n_)-1)<<16) // 2-7
332 #define AAEC_SMC_DEV_2KPAGE 0x00000040
333 #define AAEC_SMC_DEV_SROMLL 0x00000020
334 #define AAEC_SMC_DEV_SROM512 0x00000010
335 #define AAEC_SMC_DEV_BANKS_2 0x00000008
336 #define AAEC_SMC_DEV_BANKS_4 0x00000000
337 #define AAEC_SMC_DEV_WIDTH16 0x00000004
338 #define AAEC_SMC_DEV_WIDTH32 0x00000000
340 #define AAEC_SMC_DEV_INIT ( AAEC_SMC_DEV_RAS_2 \
341 |AAEC_SMC_DEV_CASLAT(3) \
342 |AAEC_SMC_DEV_BANKS_2)
344 //---------------------------------------------------------------------------
346 #define AAEC_LCD_TIMING0 0x80003000 // Timing registers
347 #define AAEC_LCD_TIMING1 0x80003004
348 #define AAEC_LCD_TIMING2 0x80003008
349 #define AAEC_LCD_TIMING3 0x8000300C
350 #define AAEC_LCD_UPBASE 0x80003010 // Upper panel DMA address
351 #define AAEC_LCD_LPBASE 0x80003014 // Lower panel DMA address
352 #define AAEC_LCD_MASK 0x80003018 // Status mask
353 #define AAEC_LCD_CONTROL 0x8000301C // Control
354 #define AAEC_LCD_CONTROL_ENAB 0x00000001 // Enable controller
355 #define AAEC_LCD_CONTROL_PWR_ENAB 0x00000800 // Enables signals
356 #define AAEC_LCD_STATUS 0x80003020 // Status
357 #define AAEC_LCD_INTERRUPT 0x80003024 // Interrupts
358 #define AAEC_LCD_UPCURR 0x80003028 // Upper panel current address
359 #define AAEC_LCD_LPCURR 0x8000302C // Lower panel current address
360 #define AAEC_LCD_LPOVERFLOW 0x80003030 // Panel overflow
361 #define AAEC_LCD_PALETTE 0x80003200 // Palette
363 //---------------------------------------------------------------------------
364 // Extended GPIO bits [platform specific]
365 #define AAED_EXT_GPIO 0x30000000
366 #define AAED_EXT_GPIO_KBD_SCAN 0x00003FFF // Keyboard scan data
367 #define AAED_EXT_GPIO_PWR_INT 0x00008FFF // Smart battery charger interrupt
368 #define AAED_EXT_GPIO_SWITCHES 0x000F0000 // DIP switches
369 #define AAED_EXT_GPIO_SWITCHES_SHIFT 16
370 #define AAED_EXT_GPIO_USB_VBUS 0x00400000 // USB Vbus sense
371 #define AAED_EXT_GPIO_LCD_PWR_EN 0x02000000 // LCD (& backlight) power enable
372 #define AAED_EXT_GPIO_LED0 0x20000000 // LED 0 (0=>ON, 1=>OFF)
373 #define AAED_EXT_GPIO_LED1 0x40000000 // LED 1 (0=>ON, 1=>OFF)
374 #define AAED_EXT_GPIO_LED2 0x80000000 // LED 2 (0=>ON, 1=>OFF)
376 /*---------------------------------------------------------------------------*/
377 /* end of aaed2000.h */
378 #endif /* CYGONCE_AAED2000_H */