1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
2 #define CYGONCE_HAL_PLATFORM_INTS_H
3 //==========================================================================
7 // HAL Interrupt and clock support
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
46 // Contributors: jskov
48 // Purpose: Define Interrupt support
49 // Description: The interrupt details for the Agilent AAED2000 are defined here.
51 // #include <cyg/hal/hal_platform_ints.h>
55 //####DESCRIPTIONEND####
57 //==========================================================================
59 // These are interrupts on the AAEC-2000 core
61 #define CYGNUM_HAL_INTERRUPT_GPIO0FIQ 0
62 #define CYGNUM_HAL_INTERRUPT_TS CYGNUM_HAL_INTERRUPT_GPIO0FIQ
63 #define CYGNUM_HAL_INTERRUPT_BLINT 1
64 #define CYGNUM_HAL_INTERRUPT_WEINT 2
65 #define CYGNUM_HAL_INTERRUPT_MCINT 3
66 #define CYGNUM_HAL_INTERRUPT_CSINT 4
67 #define CYGNUM_HAL_INTERRUPT_GPIO1INTR 5
68 #define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO1INTR
69 #define CYGNUM_HAL_INTERRUPT_GPIO2INTR 6
70 #define CYGNUM_HAL_INTERRUPT_PCMCIA_CD2 CYGNUM_HAL_INTERRUPT_GPIO2INTR
71 #define CYGNUM_HAL_INTERRUPT_GPIO3INTR 7
72 #define CYGNUM_HAL_INTERRUPT_PCMCIA_CD1 CYGNUM_HAL_INTERRUPT_GPIO3INTR
73 #define CYGNUM_HAL_INTERRUPT_TC1OI 8
74 #define CYGNUM_HAL_INTERRUPT_TC2OI 9
75 #define CYGNUM_HAL_INTERRUPT_RTCMI 10
76 #define CYGNUM_HAL_INTERRUPT_TINTR 11
77 #define CYGNUM_HAL_INTERRUPT_UART1INTR 12
78 #define CYGNUM_HAL_INTERRUPT_UART2INTR 13
79 #define CYGNUM_HAL_INTERRUPT_LCDINTR 14
80 #define CYGNUM_HAL_INTERRUPT_SSEOTI 15
81 #define CYGNUM_HAL_INTERRUPT_UART3INTR 16
82 #define CYGNUM_HAL_INTERRUPT_SCIINTR 17
83 #define CYGNUM_HAL_INTERRUPT_AACINTR 18
84 #define CYGNUM_HAL_INTERRUPT_MMCINTR 19
85 #define CYGNUM_HAL_INTERRUPT_USBINTR 20
86 #define CYGNUM_HAL_INTERRUPT_DMAINTR 21
87 #define CYGNUM_HAL_INTERRUPT_TC3OI 22
88 #define CYGNUM_HAL_INTERRUPT_GPIO4INTR 23
89 #define CYGNUM_HAL_INTERRUPT_SCI_VCCEN CYGNUM_HAL_INTERRUPT_GPIO4INTR
90 #define CYGNUM_HAL_INTERRUPT_GPIO5INTR 24
91 #define CYGNUM_HAL_INTERRUPT_SCI_DETECT CYGNUM_HAL_INTERRUPT_GPIO5INTR
92 #define CYGNUM_HAL_INTERRUPT_GPIO6INTR 25
93 #define CYGNUM_HAL_INTERRUPT_PCMCIA_RDY1 CYGNUM_HAL_INTERRUPT_GPIO6INTR
94 #define CYGNUM_HAL_INTERRUPT_GPIO7INTR 26
95 #define CYGNUM_HAL_INTERRUPT_PCMCIA_RDY2 CYGNUM_HAL_INTERRUPT_GPIO7INTR
96 #define CYGNUM_HAL_INTERRUPT_BMIINTR 27
98 #define CYGNUM_HAL_INTERRUPT_NONE -1
100 #define CYGNUM_HAL_ISR_MIN 0
101 #define CYGNUM_HAL_ISR_MAX (CYGNUM_HAL_INTERRUPT_BMIINTR)
103 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1)
105 // The vector used by the Real time clock
106 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TC1OI
108 //----------------------------------------------------------------------------
111 externC void cyg_hal_arm9_soft_reset(CYG_ADDRESS);
112 #define HAL_PLATFORM_RESET() cyg_hal_arm9_soft_reset(0)
114 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
116 #endif // CYGONCE_HAL_PLATFORM_INTS_H