1 /*=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
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34 // this file might be covered by the GNU General Public License.
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): nickg, gthomas
44 // Contributors:nickg, gthomas
46 // Purpose: HAL diagnostic output
47 // Description: Implementations of HAL diagnostic output support.
49 //####DESCRIPTIONEND####
51 //===========================================================================*/
53 #include <pkgconf/hal.h>
54 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
55 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
57 #include <cyg/infra/cyg_type.h> // base types
58 #include <cyg/infra/cyg_trac.h> // tracing macros
59 #include <cyg/infra/cyg_ass.h> // assertion macros
61 #include <cyg/hal/hal_arch.h> // basic machine info
62 #include <cyg/hal/hal_intr.h> // interrupt macros
63 #include <cyg/hal/hal_io.h> // IO macros
64 #include <cyg/hal/hal_diag.h>
65 #include <cyg/hal/drv_api.h>
66 #include <cyg/hal/hal_if.h> // interface API
67 #include <cyg/hal/hal_misc.h> // Helper functions
68 #include <cyg/hal/aaed2000.h> // platform definitions
70 // The controller is clocked at 7.3728MHz
71 #define BAUD_RATE(_n_) ((7372800/((_n_)*16))-1)
73 //-----------------------------------------------------------------------------
76 cyg_int32 msec_timeout;
80 static channel_data_t aaed2000_ser_channels[1] = {
81 { (cyg_uint8 *)AAEC_UART3, 1000, CYGNUM_HAL_INTERRUPT_UART3INTR },
84 //-----------------------------------------------------------------------------
87 cyg_hal_plf_serial_init_channel(void* __ch_data)
89 channel_data_t* chan = (channel_data_t*)__ch_data;
90 cyg_uint8* base = chan->base;
93 // Register writes don't take effect till the UART is enabled.
94 HAL_WRITE_UINT32(base+AAEC_UART_CTRL, AAEC_UART_CTRL_ENAB);
96 HAL_WRITE_UINT32(base+AAEC_UART_STATUS, 0);
97 HAL_WRITE_UINT32(base+AAEC_UART_INTM, 0);
98 HAL_WRITE_UINT32(base+AAEC_UART_BAUD,
99 BAUD_RATE(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD));
101 HAL_WRITE_UINT32(base+AAEC_UART_LCR, AAEC_UART_LCR_FIFO | AAEC_UART_LCR_WL8);
105 cyg_hal_plf_serial_putc(void *__ch_data, char c)
107 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
111 HAL_READ_UINT32(base+AAEC_UART_STATUS, status);
112 } while ((status & AAEC_UART_STATUS_TxFF) != 0);
114 HAL_WRITE_UINT32(base+AAEC_UART_DATA, c);
117 HAL_READ_UINT32(base+AAEC_UART_STATUS, status);
118 } while (status & AAEC_UART_STATUS_TxBSY);
122 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
124 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
128 HAL_READ_UINT32(base+AAEC_UART_STATUS, status);
129 if ((status & AAEC_UART_STATUS_RxFE) != 0)
132 HAL_READ_UINT32(base+AAEC_UART_DATA, c);
139 cyg_hal_plf_serial_getc(void* __ch_data)
143 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
148 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
152 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
156 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
159 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
163 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
166 channel_data_t* chan = (channel_data_t*)__ch_data;
169 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
172 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
173 if (res || 0 == delay_count--)
176 CYGACC_CALL_IF_DELAY_US(100);
182 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
184 static int irq_state = 0;
186 channel_data_t* chan = (channel_data_t*)__ch_data;
187 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
190 CYGARC_HAL_SAVE_GP();
193 case __COMMCTL_IRQ_ENABLE:
195 HAL_READ_UINT32(base+AAEC_UART_INTM, intm);
196 intm |= AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS;
197 HAL_WRITE_UINT32(base+AAEC_UART_INTM, intm);
198 HAL_INTERRUPT_UNMASK(chan->isr_vector);
200 case __COMMCTL_IRQ_DISABLE:
203 HAL_READ_UINT32(base+AAEC_UART_INTM, intm);
204 intm &= ~(AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS);
205 HAL_WRITE_UINT32(base+AAEC_UART_INTM, intm);
206 HAL_INTERRUPT_MASK(chan->isr_vector);
208 case __COMMCTL_DBG_ISR_VECTOR:
209 ret = chan->isr_vector;
211 case __COMMCTL_SET_TIMEOUT:
215 va_start(ap, __func);
217 ret = chan->msec_timeout;
218 chan->msec_timeout = va_arg(ap, cyg_uint32);
225 CYGARC_HAL_RESTORE_GP();
230 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
231 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
234 channel_data_t* chan = (channel_data_t*)__ch_data;
235 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
238 CYGARC_HAL_SAVE_GP();
240 cyg_drv_interrupt_acknowledge(chan->isr_vector);
243 HAL_READ_UINT32(base+AAEC_UART_STATUS, lsr);
244 if ( (lsr & AAEC_UART_STATUS_RxFE) != 0 ) {
245 HAL_READ_UINT32(base+AAEC_UART_DATA, _c);
247 if( cyg_hal_is_break( &c , 1 ) )
250 res = CYG_ISR_HANDLED;
253 CYGARC_HAL_RESTORE_GP();
258 cyg_hal_plf_serial_init(void)
260 hal_virtual_comm_table_t* comm;
261 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
264 cyg_hal_plf_serial_init_channel(&aaed2000_ser_channels[0]);
266 // Setup procs in the vector table
269 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
270 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
271 CYGACC_COMM_IF_CH_DATA_SET(*comm, &aaed2000_ser_channels[0]);
272 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
273 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
274 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
275 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
276 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
277 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
278 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
280 // Restore original console
281 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
285 cyg_hal_plf_comms_init(void)
287 static int initialized = 0;
294 cyg_hal_plf_serial_init();
297 /*---------------------------------------------------------------------------*/
298 /* End of hal_diag.c */