1 #ifndef CYGONCE_EXCALIBUR_H
2 #define CYGONCE_EXCALIBUR_H
4 //=============================================================================
8 // Platform specific support (register layout, etc)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: jskov
49 // Purpose: Altera/EXCALIBUR platform specific support routines
51 // Usage: #include <cyg/hal/excalibur.h>
53 //####DESCRIPTIONEND####
55 //=============================================================================
57 #include <pkgconf/hal_arm_arm9_excalibur.h>
59 #define EXCALIBUR_BASE EXCALIBUR_REGS_PHYS_BASE
61 //-----------------------------------------------------------------------------
63 // Note: this register is actually write-bit-to-clear-it
64 #define EXCALIBUR_BOOT_CR (EXCALIBUR_BASE + 0x0000)
66 #define EXCALIBUR_BOOT_CR_BM 0x00000001
67 #define EXCALIBUR_BOOT_CR_HM 0x00000002
68 #define EXCALIBUR_BOOT_CR_RE 0x00000004
70 //-----------------------------------------------------------------------------
72 #define EXCALIBUR_DPSRAM_BASE (EXCALIBUR_BASE + 0x0030)
73 #define _DPSRAM0_SR 0x0000
74 #define _DPSRAM0_LCR 0x0004
75 #define _DPSRAM1_SR 0x0008
76 #define _DPSRAM1_LCR 0x000c
78 #define _DPSRAM0_LCR_INIT 0x00000000
79 #define _DPSRAM1_LCR_INIT 0x00000000
81 //-----------------------------------------------------------------------------
83 #define EXCALIBUR_IOCR_BASE (EXCALIBUR_BASE + 0x0040)
84 #define _IOCR_SDRAM 0x0000
85 #define _IOCR_EBI 0x0004
86 #define _IOCR_UART 0x0008
87 #define _IOCR_TRACE 0x000c
89 #define _IOCR_OC_PCI 0x00000008
90 #define _IOCR_OC_FAST 0x00000004
91 #define _IOCR_OC_SLOW 0x00000000
92 #define _IOCR_IO_STRIPE 0x00000002
93 #define _IOCR_LOCK 0x00000001
95 #define EXCALIBUR_IOCR_SDRAM_INIT (_IOCR_OC_FAST | _IOCR_IO_STRIPE | _IOCR_LOCK)
96 #define EXCALIBUR_IOCR_EBI_INIT (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK)
97 #define EXCALIBUR_IOCR_UART_INIT (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK)
100 //-----------------------------------------------------------------------------
102 #define EXCALIBUR_MMAP_BASE (EXCALIBUR_BASE + 0x0080)
103 #define _MMAP_REGISTERS 0x0000
104 #define _MMAP_SRAM0 0x0010
105 #define _MMAP_SRAM1 0x0014
106 #define _MMAP_DPSRAM0 0x0020
107 #define _MMAP_DPSRAM1 0x0024
108 #define _MMAP_SDRAM0 0x0030
109 #define _MMAP_SDRAM1 0x0034
110 #define _MMAP_EBI0 0x0040
111 #define _MMAP_EBI1 0x0044
112 #define _MMAP_EBI2 0x0048
113 #define _MMAP_EBI3 0x004c
114 #define _MMAP_PLD0 0x0050
115 #define _MMAP_PLD1 0x0054
116 #define _MMAP_PLD2 0x0058
117 #define _MMAP_PLD3 0x005c
119 #define _MMAP_SIZE_16K (13<<7)
120 #define _MMAP_SIZE_64K (15<<7)
121 #define _MMAP_SIZE_128K (16<<7)
122 #define _MMAP_SIZE_1M (19<<7)
123 #define _MMAP_SIZE_4M (21<<7)
124 #define _MMAP_SIZE_16M (23<<7)
125 #define _MMAP_SIZE_32M (24<<7)
126 #define _MMAP_SIZE_64M (25<<7)
128 #define _MMAP_PREFETCH 0x00000000
129 #define _MMAP_NOPREFETCH 0x00000002
131 #define _MMAP_ENABLE 0x00000001
132 #define _MMAP_DISABLE 0x00000000
134 #define _MMAP_REGISTERS_INIT (EXCALIBUR_REGS_PHYS_BASE + 0x00000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
135 #define _MMAP_SRAM0_INIT (EXCALIBUR_SRAM_PHYS_BASE + 0x00000000 | _MMAP_SIZE_128K | _MMAP_PREFETCH | _MMAP_ENABLE)
136 #define _MMAP_SRAM1_INIT (EXCALIBUR_SRAM_PHYS_BASE + 0x00020000 | _MMAP_SIZE_128K | _MMAP_PREFETCH | _MMAP_ENABLE)
137 #define _MMAP_DPSRAM0_INIT (EXCALIBUR_SRAM_PHYS_BASE + 0x00040000 | _MMAP_SIZE_64K | _MMAP_PREFETCH | _MMAP_ENABLE)
138 #define _MMAP_DPSRAM1_INIT (EXCALIBUR_SRAM_PHYS_BASE + 0x00050000 | _MMAP_SIZE_64K | _MMAP_PREFETCH | _MMAP_ENABLE)
139 #define _MMAP_SDRAM0_INIT (EXCALIBUR_SDRAM_PHYS_BASE + 0x00000000 | _MMAP_SIZE_64M | _MMAP_PREFETCH | _MMAP_ENABLE)
140 #define _MMAP_SDRAM1_INIT (EXCALIBUR_SDRAM_PHYS_BASE + 0x04000000 | _MMAP_SIZE_64M | _MMAP_PREFETCH | _MMAP_ENABLE)
141 #define _MMAP_EBI0_INIT (EXCALIBUR_FLASH_PHYS_BASE + 0x00000000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE)
142 #define _MMAP_EBI1_INIT (EXCALIBUR_FLASH_PHYS_BASE + 0x00400000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE)
143 #define _MMAP_EBI2_INIT (EXCALIBUR_FLASH_PHYS_BASE + 0x00800000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE)
144 #define _MMAP_EBI3_INIT (EXCALIBUR_FLASH_PHYS_BASE + 0x00c00000 | _MMAP_SIZE_4M | _MMAP_PREFETCH | _MMAP_ENABLE)
145 #define _MMAP_PLD0_INIT (EXCALIBUR_PLD_PHYS_BASE + 0x00000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
146 //#define _MMAP_PLD1_INIT (EXCALIBUR_PLD_PHYS_BASE + 0x00004000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
147 #define _MMAP_PLD1_INIT (0x0f000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
148 #define _MMAP_PLD2_INIT (EXCALIBUR_PLD_PHYS_BASE + 0x00008000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
149 #define _MMAP_PLD3_INIT (EXCALIBUR_PLD_PHYS_BASE + 0x0000c000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
151 #define EXCALIBUR_SDRAM_PHYS_BASE 0x00000000
152 #define EXCALIBUR_FLASH_PHYS_BASE 0x40000000
153 #define EXCALIBUR_SRAM_PHYS_BASE 0x08000000
154 #define EXCALIBUR_PLD_PHYS_BASE 0x80000000
155 #define EXCALIBUR_REGS_PHYS_BASE 0x7fffc000
160 //-----------------------------------------------------------------------------
162 #define EXCALIBUR_TIMER0_CR (EXCALIBUR_BASE+0x0200)
163 #define EXCALIBUR_TIMER0_PRE (EXCALIBUR_BASE+0x0210)
164 #define EXCALIBUR_TIMER0_LIMIT (EXCALIBUR_BASE+0x0220)
165 #define EXCALIBUR_TIMER0_READ (EXCALIBUR_BASE+0x0230)
167 #define EXCALIBUR_TIMER1_CR (EXCALIBUR_BASE+0x0240)
168 #define EXCALIBUR_TIMER1_PRE (EXCALIBUR_BASE+0x0250)
169 #define EXCALIBUR_TIMER1_LIMIT (EXCALIBUR_BASE+0x0260)
170 #define EXCALIBUR_TIMER1_READ (EXCALIBUR_BASE+0x0270)
172 #define EXCALIBUR_TIMER_CR_MODE_HEARBEAT 0x00000000
173 #define EXCALIBUR_TIMER_CR_MODE_ONE_SHOT 0x00000001
174 #define EXCALIBUR_TIMER_CR_IE 0x00000004
175 #define EXCALIBUR_TIMER_CR_CI 0x00000008
176 #define EXCALIBUR_TIMER_CR_S 0x00000010
178 //-----------------------------------------------------------------------------
180 #define EXCALIBUR_UART0_BASE (EXCALIBUR_BASE+0x0280)
181 #define _UART_RSR 0x0000
182 #define _UART_RDS 0x0004
183 #define _UART_RD 0x0008
184 #define _UART_TSR 0x000c
185 #define _UART_TD 0x0010
186 #define _UART_FCR 0x0014
187 #define _UART_IES 0x0018
188 #define _UART_IEC 0x001c
189 #define _UART_ISR 0x0020
190 #define _UART_IID 0x0024
191 #define _UART_MC 0x0028
192 #define _UART_MCR 0x002c
193 #define _UART_MSR 0x0030
194 #define _UART_DIV_LO 0x0034
195 #define _UART_DIV_HI 0x0038
197 #define _UART_RSR_RX_LEVEL 0x0000001f
199 #define _UART_TSR_TXI 0x00000080
201 #define _UART_FCR_TC 0x00000001
202 #define _UART_FCR_RC 0x00000002
203 #define _UART_FCR_TX_THR_15 0x0000001c
204 #define _UART_FCR_RX_THR_1 0x00000000
206 #define _UART_INTS_RE 0x00000001
207 #define _UART_INTS_RI _UART_INTS_RE
208 #define _UART_INTS_TE 0x00000002
209 #define _UART_INTS_TI _UART_INTS_TE
210 #define _UART_INTS_TIE 0x00000004
211 #define _UART_INTS_TII _UART_INTS_TIE
212 #define _UART_INTS_ME 0x00000008
213 #define _UART_INTS_MI _UART_INTS_ME
216 #define _UART_MC_8BIT 0x00000003
217 #define _UART_MC_1STOP 0x00000000
218 #define _UART_MC_PARITY_NONE 0x00000000
220 //-----------------------------------------------------------------------------
222 #define EXCALIBUR_CLK_BASE (EXCALIBUR_BASE + 0x0300)
223 #define _CLK_PLL1_NCNT 0x0000
224 #define _CLK_PLL1_MCNT 0x0004
225 #define _CLK_PLL1_KCNT 0x0008
226 #define _CLK_PLL1_CTRL 0x000c
227 #define _CLK_PLL2_NCNT 0x0010
228 #define _CLK_PLL2_MCNT 0x0014
229 #define _CLK_PLL2_KCNT 0x0018
230 #define _CLK_PLL2_CTRL 0x001c
231 #define _CLK_DERIVE 0x0020
232 #define _CLK_STATUS 0x0024
233 #define _CLK_AHB1_COUNT 0x0028
235 #define _CLK_PLL1_CTRL_P 0x00000001
236 #define _CLK_PLL2_CTRL_P 0x00000001
238 #define _CLK_DERIVE_BP1 (1<<12)
239 #define _CLK_DERIVE_BP2 (1<<13)
241 #define _CLK_STATUS_L1 0x00000001
242 #define _CLK_STATUS_L2 0x00000002
243 #define _CLK_STATUS_C1 0x00000004
244 #define _CLK_STATUS_C2 0x00000008
246 // Settings from Altera example code. Note that this differs from the
247 // magic values described in the manual. I think the values are
248 // supposed to disable the PLLs, making the core run at 25MHz and
249 // peripherals at 12.5MHz
250 #define _CLK_PLL1_CTRL_INIT 0x00001064
251 #define _CLK_PLL2_CTRL_INIT 0x00001064
252 #define _CLK_DERIVE_INIT 0x00003010
254 //-----------------------------------------------------------------------------
255 // Expansion Bus Interface
256 #define EXCALIBUR_EBI_CR (EXCALIBUR_BASE + 0x0380)
258 #define EXCALIBUR_EBI_CR_EO 0x00000008
260 #define EXCALIBUR_EBI_CR_INIT (EXCALIBUR_EBI_CR_EO)
262 //-----------------------------------------------------------------------------
264 #define EXCALIBUR_SDRAM_BASE (EXCALIBUR_BASE + 0x0400)
265 #define _SDRAM_TIMING1 0x0000
266 #define _SDRAM_TIMING2 0x0004
267 #define _SDRAM_CONFIG 0x0008
268 #define _SDRAM_REFRESH 0x000c
269 #define _SDRAM_ADDR 0x0010
270 #define _SDRAM_INIT 0x001c
271 #define _SDRAM_MODE0 0x0020
272 #define _SDRAM_MODE1 0x0024
273 #define EXCALIBUR_SDRAM_WIDTH (EXCALIBUR_BASE + 0x007c)
276 #define _SDRAM_WIDTH_W 0x00000002
277 #define _SDRAM_WIDTH_LK 0x00000001
281 #define _SDRAM_TIMING1_INIT 0x00009124
282 // CAS-2, 8 words burst, 3 clock refresh
283 #define _SDRAM_TIMING2_INIT 0x00000788
285 #define _SDRAM_CONFIG_INIT 0x00000000
286 // Refresh period of 15us - at a clock of 75MHz that's 1125 cycles
287 #define _SDRAM_REFRESH_INIT 1125
288 // Rows (12) & columns (10)
289 #define _SDRAM_ADDR_INIT 0x0000ca80
290 // SDRAM mode (from Micron MT48LC16M8A2 manual)
291 // M0-2: burst length = 3 (8 words)
292 // M3 : burst type = 0 (sequential vs interleaved)
293 // M4-6: CAS latency = 2
294 // M7-8: operating mode = 0
295 // M9 : write burst mode = 0 (writes are also in burst)
296 #define _SDRAM_MODE0_INIT ((2<<4)|3)
298 #define _SDRAM_MODE1_INIT 0x00000000
301 #define _SDRAM_INIT_EN 0x00008000
302 #define _SDRAM_INIT_PR 0x00004000
303 #define _SDRAM_INIT_LM 0x00002000
304 #define _SDRAM_INIT_LEM 0x00001000
305 #define _SDRAM_INIT_RF 0x00000800
306 #define _SDRAM_INIT_BS 0x00000400
307 #define _SDRAM_INIT_SR 0x00000200
309 #if (CYGNUM_HAL_ARM_EXCALIBUR_SDRAM_CLOCK != 75000000)
310 # error "Hardwired for a 75MHz SDRAM clock"
313 //-----------------------------------------------------------------------------
314 // Watchdog controller
315 #define EXCALIBUR_WDOG_CR (EXCALIBUR_BASE+0x0a00)
316 #define EXCALIBUR_WDOG_COUNT (EXCALIBUR_BASE+0x0a04)
317 #define EXCALIBUR_WDOG_RELOAD (EXCALIBUR_BASE+0x0a08)
319 //-----------------------------------------------------------------------------
320 // Interrupt controller
321 #define EXCALIBUR_INT_MASK_SET (EXCALIBUR_BASE+0x0c00)
322 #define EXCALIBUR_INT_MASK_CLEAR (EXCALIBUR_BASE+0x0c04)
323 #define EXCALIBUR_INT_SOURCE_STATUS (EXCALIBUR_BASE+0x0c08)
324 #define EXCALIBUR_INT_REQUEST_STATUS (EXCALIBUR_BASE+0x0c0c)
325 #define EXCALIBUR_INT_ID (EXCALIBUR_BASE+0x0c10)
326 #define EXCALIBUR_INT_PLD_PRIORITY (EXCALIBUR_BASE+0x0c14)
327 #define EXCALIBUR_INT_INT_MODE (EXCALIBUR_BASE+0x0c18)
328 #define EXCALIBUR_INT_PRIORITY_0 (EXCALIBUR_BASE+0x0c80)
329 #define EXCALIBUR_INT_PRIORITY_1 (EXCALIBUR_BASE+0x0c84)
330 #define EXCALIBUR_INT_PRIORITY_2 (EXCALIBUR_BASE+0x0c88)
331 #define EXCALIBUR_INT_PRIORITY_3 (EXCALIBUR_BASE+0x0c8c)
332 #define EXCALIBUR_INT_PRIORITY_4 (EXCALIBUR_BASE+0x0c90)
333 #define EXCALIBUR_INT_PRIORITY_5 (EXCALIBUR_BASE+0x0c94)
334 #define EXCALIBUR_INT_PRIORITY_6 (EXCALIBUR_BASE+0x0c98)
335 #define EXCALIBUR_INT_PRIORITY_7 (EXCALIBUR_BASE+0x0c9c)
336 #define EXCALIBUR_INT_PRIORITY_8 (EXCALIBUR_BASE+0x0ca0)
337 #define EXCALIBUR_INT_PRIORITY_9 (EXCALIBUR_BASE+0x0ca4)
338 #define EXCALIBUR_INT_PRIORITY_10 (EXCALIBUR_BASE+0x0ca8)
339 #define EXCALIBUR_INT_PRIORITY_11 (EXCALIBUR_BASE+0x0cac)
340 #define EXCALIBUR_INT_PRIORITY_12 (EXCALIBUR_BASE+0x0cb0)
341 #define EXCALIBUR_INT_PRIORITY_13 (EXCALIBUR_BASE+0x0cb4)
342 #define EXCALIBUR_INT_PRIORITY_14 (EXCALIBUR_BASE+0x0cb8)
343 #define EXCALIBUR_INT_PRIORITY_15 (EXCALIBUR_BASE+0x0cbc)
344 #define EXCALIBUR_INT_PRIORITY_16 (EXCALIBUR_BASE+0x0cc0)
346 #define EXCALIBUR_INT_SOURCE_P0 0x00000001
347 #define EXCALIBUR_INT_SOURCE_P1 0x00000002
348 #define EXCALIBUR_INT_SOURCE_P2 0x00000004
349 #define EXCALIBUR_INT_SOURCE_P3 0x00000008
350 #define EXCALIBUR_INT_SOURCE_P4 0x00000010
351 #define EXCALIBUR_INT_SOURCE_P5 0x00000020
352 #define EXCALIBUR_INT_SOURCE_IP 0x00000040
353 #define EXCALIBUR_INT_SOURCE_UA 0x00000080
354 #define EXCALIBUR_INT_SOURCE_T0 0x00000100
355 #define EXCALIBUR_INT_SOURCE_T1 0x00000200
356 #define EXCALIBUR_INT_SOURCE_PS 0x00000400
357 #define EXCALIBUR_INT_SOURCE_EE 0x00000800
358 #define EXCALIBUR_INT_SOURCE_PE 0x00001000
359 #define EXCALIBUR_INT_SOURCE_AE 0x00002000
360 #define EXCALIBUR_INT_SOURCE_CT 0x00004000
361 #define EXCALIBUR_INT_SOURCE_CR 0x00008000
362 #define EXCALIBUR_INT_SOURCE_FC 0x00010000
364 #define EXCALIBUR_INT_PRIORITY_FIQ 0x00000040
365 #define EXCALIBUR_INT_PRIORITY_LVL_mask 0x0000003f
367 //-----------------------------------------------------------------------------
369 #define EXCALIBUR_PLD_BASE EXCALIBUR_PLD_PHYS_BASE
371 #define EXCALIBUR_PLD_LEDS (EXCALIBUR_PLD_BASE + 0x0100)
375 #endif // CYGONCE_EXCALIBUR_H
376 //-----------------------------------------------------------------------------
377 // end of excalibur.h