1 //=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Purpose: HAL diagnostic output
47 // Description: Implementations of HAL diagnostic output support.
49 //####DESCRIPTIONEND####
51 //=============================================================================
53 #include <pkgconf/hal.h>
54 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
55 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
57 #include <cyg/infra/cyg_type.h> // base types
58 #include <cyg/infra/cyg_trac.h> // tracing macros
59 #include <cyg/infra/cyg_ass.h> // assertion macros
61 #include <cyg/hal/hal_arch.h> // basic machine info
62 #include <cyg/hal/hal_intr.h> // interrupt macros
63 #include <cyg/hal/hal_io.h> // IO macros
64 #include <cyg/hal/hal_diag.h>
65 #include <cyg/hal/drv_api.h>
66 #include <cyg/hal/hal_if.h> // interface API
67 #include <cyg/hal/hal_misc.h> // Helper functions
68 #include <cyg/hal/excalibur.h> // platform definitions
70 //-----------------------------------------------------------------------------
72 #define CYG_DEVICE_SERIAL_BAUD_DIV (CYGNUM_HAL_ARM_EXCALIBUR_PERIPHERAL_CLOCK/CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD/16)
73 #define CYG_DEVICE_SERIAL_BAUD_LSB (CYG_DEVICE_SERIAL_BAUD_DIV&0xff)
74 #define CYG_DEVICE_SERIAL_BAUD_MSB ((CYG_DEVICE_SERIAL_BAUD_DIV>>8)&0xff)
76 //-----------------------------------------------------------------------------
79 cyg_int32 msec_timeout;
83 //-----------------------------------------------------------------------------
86 cyg_hal_plf_serial_init_channel(void* __ch_data)
88 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
91 HAL_WRITE_UINT32(base+_UART_MC, _UART_MC_8BIT | _UART_MC_1STOP | _UART_MC_PARITY_NONE);
93 HAL_WRITE_UINT32(base+_UART_DIV_LO, CYG_DEVICE_SERIAL_BAUD_LSB);
94 HAL_WRITE_UINT32(base+_UART_DIV_HI, CYG_DEVICE_SERIAL_BAUD_MSB);
95 HAL_WRITE_UINT32(base+_UART_FCR, (_UART_FCR_TC | _UART_FCR_RC |
96 _UART_FCR_TX_THR_15 | _UART_FCR_RX_THR_1)); // clear & enableFIFO
98 // enable RX interrupts - otherwise ISR cannot be polled. Actual
99 // interrupt control of serial happens via INT_MASK
100 HAL_WRITE_UINT32(base+_UART_IES, _UART_INTS_RE);
104 cyg_hal_plf_serial_putc(void *__ch_data, char c)
106 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
108 CYGARC_HAL_SAVE_GP();
111 HAL_READ_UINT32(base+_UART_TSR, tsr);
112 // Wait for TXI flag to be set - or for the register to be
113 // zero (works around a HW bug it seems).
114 } while (tsr && (tsr & _UART_TSR_TXI) == 0);
116 HAL_WRITE_UINT32(base+_UART_TD, (cyg_uint32)(unsigned char)c);
118 CYGARC_HAL_RESTORE_GP();
122 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
124 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
125 cyg_uint32 rsr, isr, data;
127 HAL_READ_UINT32(base+_UART_ISR, isr);
128 if (0 == (isr & _UART_INTS_RI)) {
129 HAL_READ_UINT32(base+_UART_RSR, rsr);
134 HAL_READ_UINT32(base+_UART_RD, data);
135 *ch = (cyg_uint8)(data & 0xff);
137 // Read RSR to clear interrupt, and RDS to clear errors
138 HAL_READ_UINT32(base+_UART_RSR, data);
139 HAL_READ_UINT32(base+_UART_RDS, data);
145 cyg_hal_plf_serial_getc(void* __ch_data)
148 CYGARC_HAL_SAVE_GP();
150 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
152 CYGARC_HAL_RESTORE_GP();
156 static channel_data_t excalibur_ser_channels[1] = {
157 { (cyg_uint32)EXCALIBUR_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART }
161 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
164 CYGARC_HAL_SAVE_GP();
167 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
169 CYGARC_HAL_RESTORE_GP();
173 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
175 CYGARC_HAL_SAVE_GP();
178 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
180 CYGARC_HAL_RESTORE_GP();
184 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
187 channel_data_t* chan = (channel_data_t*)__ch_data;
189 CYGARC_HAL_SAVE_GP();
191 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
194 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
195 if (res || 0 == delay_count--)
198 CYGACC_CALL_IF_DELAY_US(100);
201 CYGARC_HAL_RESTORE_GP();
206 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
208 static int irq_state = 0;
209 channel_data_t* chan = (channel_data_t*)__ch_data;
211 CYGARC_HAL_SAVE_GP();
214 case __COMMCTL_IRQ_ENABLE:
217 // Need to keep it enabled to allow polling using ISR
218 //HAL_WRITE_UINT32(chan->base+_UART_IES, _UART_INTS_RE);
220 HAL_INTERRUPT_UNMASK(chan->isr_vector);
222 case __COMMCTL_IRQ_DISABLE:
226 // Need to keep it enabled to allow polling using ISR
227 // HAL_WRITE_UINT32(chan->base+_UART_IEC, _UART_INTS_RE);
229 HAL_INTERRUPT_MASK(chan->isr_vector);
231 case __COMMCTL_DBG_ISR_VECTOR:
232 ret = chan->isr_vector;
234 case __COMMCTL_SET_TIMEOUT:
238 va_start(ap, __func);
240 ret = chan->msec_timeout;
241 chan->msec_timeout = va_arg(ap, cyg_uint32);
248 CYGARC_HAL_RESTORE_GP();
253 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
254 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
257 channel_data_t* chan = (channel_data_t*)__ch_data;
258 cyg_uint32 isr, ch, rsr;
260 CYGARC_HAL_SAVE_GP();
262 cyg_drv_interrupt_acknowledge(chan->isr_vector);
265 HAL_READ_UINT32(chan->base+_UART_ISR, isr);
266 HAL_READ_UINT32(chan->base+_UART_RSR, rsr);
268 // Again, check both RI and the RX FIFO count.
269 if ( ((isr & _UART_INTS_RI) != 0 ) || (rsr) ) {
271 HAL_READ_UINT32(chan->base+_UART_RD, ch);
274 if( cyg_hal_is_break( &c , 1 ) )
277 res = CYG_ISR_HANDLED;
280 CYGARC_HAL_RESTORE_GP();
285 cyg_hal_plf_serial_init(void)
287 hal_virtual_comm_table_t* comm;
288 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
290 // Disable interrupts.
291 HAL_INTERRUPT_MASK(excalibur_ser_channels[0].isr_vector);
294 cyg_hal_plf_serial_init_channel(&excalibur_ser_channels[0]);
296 // Setup procs in the vector table
299 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
300 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
301 CYGACC_COMM_IF_CH_DATA_SET(*comm, &excalibur_ser_channels[0]);
302 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
303 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
304 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
305 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
306 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
307 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
308 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
310 // Restore original console
311 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
315 cyg_hal_plf_comms_init(void)
317 static int initialized = 0;
324 cyg_hal_plf_serial_init();
327 //-----------------------------------------------------------------------------
334 //-----------------------------------------------------------------------------