1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
2 #define CYGONCE_HAL_PLATFORM_INTS_H
3 //==========================================================================
7 // HAL Interrupt and clock support
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): michael anburaj <michaelanburaj@hotmail.com>
46 // Contributors: michael anburaj <michaelanburaj@hotmail.com>
48 // Purpose: Define Interrupt support
49 // Description: The interrupt details for the Samsung SMDK2410 are defined here.
51 // #include <cyg/hal/hal_platform_ints.h>
55 //####DESCRIPTIONEND####
57 //==========================================================================
59 #include <cyg/hal/s3c2410x.h>
61 // These are interrupts on the SMDK2410
63 #define CYGNUM_HAL_INTERRUPT_EINT0 0
64 #define CYGNUM_HAL_INTERRUPT_EINT1 1
65 #define CYGNUM_HAL_INTERRUPT_EINT2 2
66 #define CYGNUM_HAL_INTERRUPT_EINT3 3
67 #define CYGNUM_HAL_INTERRUPT_EINT4_7 4
68 #define CYGNUM_HAL_INTERRUPT_EINT8_23 5
69 #define CYGNUM_HAL_INTERRUPT_NOTUSED6 6
70 #define CYGNUM_HAL_INTERRUPT_BAT_FLT 7
71 #define CYGNUM_HAL_INTERRUPT_TICK 8
72 #define CYGNUM_HAL_INTERRUPT_WDT 9
73 #define CYGNUM_HAL_INTERRUPT_TIMER0 10
74 #define CYGNUM_HAL_INTERRUPT_TIMER1 11
75 #define CYGNUM_HAL_INTERRUPT_TIMER2 12
76 #define CYGNUM_HAL_INTERRUPT_TIMER3 13
77 #define CYGNUM_HAL_INTERRUPT_TIMER4 14
78 #define CYGNUM_HAL_INTERRUPT_UART2 15
79 #define CYGNUM_HAL_INTERRUPT_LCD 16
80 #define CYGNUM_HAL_INTERRUPT_DMA0 17
81 #define CYGNUM_HAL_INTERRUPT_DMA1 18
82 #define CYGNUM_HAL_INTERRUPT_DMA2 19
83 #define CYGNUM_HAL_INTERRUPT_DMA3 20
84 #define CYGNUM_HAL_INTERRUPT_SDI 21
85 #define CYGNUM_HAL_INTERRUPT_SPI0 22
86 #define CYGNUM_HAL_INTERRUPT_UART1 23
87 #define CYGNUM_HAL_INTERRUPT_NOTUSED24 24
88 #define CYGNUM_HAL_INTERRUPT_USBD 25
89 #define CYGNUM_HAL_INTERRUPT_USBH 26
90 #define CYGNUM_HAL_INTERRUPT_IIC 27
91 #define CYGNUM_HAL_INTERRUPT_UART0 28
92 #define CYGNUM_HAL_INTERRUPT_SPI1 29
93 #define CYGNUM_HAL_INTERRUPT_RTCC 30
94 #define CYGNUM_HAL_INTERRUPT_ADC 31
96 #define CYGNUM_HAL_INTERRUPT_NONE -1
98 #define CYGNUM_HAL_ISR_MIN 0
99 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_ADC
100 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1)
102 // The vector used by the Real time clock
103 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER4
107 //----------------------------------------------------------------------------
110 // Watchdog is started with a very small delay to Reset immediatly.
111 #define HAL_PLATFORM_RESET() \
113 HAL_WRITE_UINT32(WTCON, 0); \
114 HAL_WRITE_UINT32(WTDAT, 1); \
115 HAL_WRITE_UINT32(WTCON, (1<<0)|(0<<2)|(0<<3)|(1<<5)|(0<<8)); \
119 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
121 #endif // CYGONCE_HAL_PLATFORM_INTS_H