1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
3 //=============================================================================
5 // hal_platform_setup.h
7 // Platform specific support for HAL (assembly code)
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): michael anburaj <michaelanburaj@hotmail.com>
46 // Contributors: michael anburaj <michaelanburaj@hotmail.com>
48 // Purpose: ARM9/SMDK2410 platform specific support routines
50 // Usage: #include <cyg/hal/hal_platform_setup.h>
51 // Only used by "vectors.S"
53 //####DESCRIPTIONEND####
55 //=============================================================================
57 #include <pkgconf/system.h> // System-wide configuration info
58 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
59 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
60 #include CYGHWR_MEMORY_LAYOUT_H
61 #include <cyg/hal/hal_mmu.h> // MMU definitions
62 #include <cyg/hal/s3c2410x.h> // Platform specific hardware definitions
63 #include <cyg/hal/memcfg.h> // Platform specific memory configuration
66 #if (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 176000000)
67 #define M_MDIV 80 // Fin=12.0MHz Fout=176.0MHz
70 #elif (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 180000000)
71 #define M_MDIV 82 // Fin=12.0MHz Fout=180.0MHz
74 #elif (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 184000000)
75 #define M_MDIV 84 // Fin=12.0MHz Fout=184.0MHz
78 #elif (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 192000000)
79 #define M_MDIV 88 // Fin=12.0MHz Fout=192.0MHz
82 #elif (CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK == 200000000)
83 #define M_MDIV 92 // Fin=12.0MHz Fout=200.0MHz
87 #error CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK not set to the right value
91 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
92 #define PLATFORM_SETUP1 _platform_setup1
93 #define CYGHWR_HAL_ARM_HAS_MMU
94 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
96 // We need this here - can't rely on a translation table until MMU has
98 .macro RAW_LED_MACRO x
102 orr r1,r1,#((0xf & ~(\x))<<4)
107 // Configure GPF[4:7] as Output & pull-up turned off
108 .macro RAW_LED_PORT_INIT_MACRO
111 orr r1,r1,#((1<<7)|(1<<6)|(1<<5)|(1<<4))
118 orr r1,r1,#((1<<14)|(1<<12)|(1<<10)|(1<<8))
122 // This macro represents the initial startup code for the platform
123 .macro _platform_setup1
124 #ifndef CYG_HAL_STARTUP_RAM
125 ldr r0,=WTCON // watch dog disable
129 RAW_LED_PORT_INIT_MACRO
131 #ifndef CYG_HAL_STARTUP_RAM
133 ldr r1,=0xffffffff // all interrupt disable
137 ldr r1,=0x7ff // all sub interrupt disable
142 // Disable and clear caches
144 bic r0,r0,#0x1000 // disable ICache
145 bic r0,r0,#0x000f // disable DCache, write buffer,
146 // MMU and alignment faults
151 mcr p15,0,r0,c7,c6,0 // clear data cache
153 mrc p15,0,r0,c15,c1,0 // disable streaming
155 mcr p15,0,r0,c15,c1,0
158 // To reduce PLL lock time, adjust the LOCKTIME register.
163 // We must set ratios, set memctl, then change FCLK.
164 ldr r0,=CLKDIVN // Set ratios 1:2:4 for FCLK:HCLK:PCLK
168 // MMU_SetAsyncBusMode //Must select, since we're setting HDIVN=1
169 #define R1_iA (1<<31)
170 #define R1_nF (1<<30)
172 orr r0,r0,#(R1_nF|R1_iA)
176 // Set memory control registers
178 ldr r1,=BWSCON // BWSCON Address
179 add r2, r0, #52 // End address of SMRDATA
188 // Memory configuration should be optimized for best performance
189 // The following parameter is not optimized.
190 // Memory access cycle parameter strategy
191 // 1) The memory settings is safe parameters even at HCLK=75Mhz.
192 // 2) SDRAM refresh period is for HCLK=75Mhz.
194 .long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
195 .long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) //GCS0
196 .long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) //GCS1
197 .long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) //GCS2
198 .long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) //GCS3
199 .long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) //GCS4
200 .long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) //GCS5
201 .long ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) //GCS6
202 .long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) //GCS7
203 .long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
205 .long 0x32 // SCLK power saving mode, BANKSIZE 128M/128M
207 .long 0x30 // MRSR6 CL=3clk
209 // .long 0x20 // MRSR6 CL=2clk
210 // .long 0x20 // MRSR7
217 ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) // Fin=12MHz,Fout=50MHz
220 #endif /* !CYG_HAL_STARTUP_RAM */
222 // Set up a stack [for calling C code]
223 ldr r1,=__startup_stack
224 ldr r2,=SMDK2410_SDRAM_PHYS_BASE
234 #ifdef CYG_HAL_STARTUP_ROMRAM
235 ldr r1,=__exception_handlers
238 add r2,r9,r1 // r9 has ROM offset
240 ldr r1,=MMU_Control_Init|MMU_Control_M
241 mcr MMU_CP,0,r1,MMU_Control,c0
242 mov pc,r2 /* Change address spaces */
249 #ifdef CYG_HAL_STARTUP_ROMRAM
250 mov r0,r9 // Relocate FLASH/ROM to RAM
251 ldr r1,=__exception_handlers // ram base & length
252 ldr r2,=__rom_data_end
268 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
269 #define PLATFORM_SETUP1
272 //-----------------------------------------------------------------------------
273 // end of hal_platform_setup.h
274 #endif // CYGONCE_HAL_PLATFORM_SETUP_H