3 //=============================================================================
7 // Samsung SMDK2410 specific memory configuration
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): michael anburaj <michaelanburaj@hotmail.com>
46 // Contributors: michael anburaj <michaelanburaj@hotmail.com>
48 // Purpose: ARM9/SMDK2410 platform specific memory configuration
50 // Usage: #include <cyg/hal/memcfg.h>
51 // Only used by "hal_platform_setup.h"
53 //####DESCRIPTIONEND####
55 //=============================================================================
61 //GCS6 16bit(16MB) SDRAM(0x0c000000-0x0cffffff)
62 //GCS7 16bit(16MB) SDRAM(0x0d000000-0x0dffffff)
64 //GCS6 32bit(32MB) SDRAM(0x0c000000-0x0dffffff)
75 #error BUSWIDTH not defined
78 #define B1_BWSCON (DW16)
79 #define B2_BWSCON (DW16)
80 #define B3_BWSCON (DW16)
81 #define B4_BWSCON (DW16)
82 #define B5_BWSCON (DW16)
83 #define B6_BWSCON (DW16)
84 #define B7_BWSCON (DW16)
86 #define B1_BWSCON (DW32)
87 #define B2_BWSCON (DW16)
88 #define B3_BWSCON (DW16)
89 #define B4_BWSCON (DW16)
90 #define B5_BWSCON (DW16)
91 #define B6_BWSCON (DW32)
92 #define B7_BWSCON (DW32)
97 #define B0_Tacs 0x0 //0clk
98 #define B0_Tcos 0x0 //0clk
99 #define B0_Tacc 0x7 //14clk
100 #define B0_Tcoh 0x0 //0clk
101 #define B0_Tah 0x0 //0clk
103 #define B0_PMC 0x0 //normal
106 #define B1_Tacs 0x0 //0clk
107 #define B1_Tcos 0x0 //0clk
108 #define B1_Tacc 0x7 //14clk
109 #define B1_Tcoh 0x0 //0clk
110 #define B1_Tah 0x0 //0clk
112 #define B1_PMC 0x0 //normal
115 #define B2_Tacs 0x0 //0clk
116 #define B2_Tcos 0x0 //0clk
117 #define B2_Tacc 0x7 //14clk
118 #define B2_Tcoh 0x0 //0clk
119 #define B2_Tah 0x0 //0clk
121 #define B2_PMC 0x0 //normal
124 #define B3_Tacs 0x0 //0clk
125 #define B3_Tcos 0x0 //0clk
126 #define B3_Tacc 0x7 //14clk
127 #define B3_Tcoh 0x0 //0clk
128 #define B3_Tah 0x0 //0clk
130 #define B3_PMC 0x0 //normal
133 #define B4_Tacs 0x0 //0clk
134 #define B4_Tcos 0x0 //0clk
135 #define B4_Tacc 0x7 //14clk
136 #define B4_Tcoh 0x0 //0clk
137 #define B4_Tah 0x0 //0clk
139 #define B4_PMC 0x0 //normal
142 #define B5_Tacs 0x0 //0clk
143 #define B5_Tcos 0x0 //0clk
144 #define B5_Tacc 0x7 //14clk
145 #define B5_Tcoh 0x0 //0clk
146 #define B5_Tah 0x0 //0clk
148 #define B5_PMC 0x0 //normal
151 #define B6_MT 0x3 //SDRAM
152 //#define B6_Trcd 0x0 //2clk
153 #define B6_Trcd 0x1 //3clk
154 #define B6_SCAN 0x1 //9bit
157 #define B7_MT 0x3 //SDRAM
158 //#define B7_Trcd 0x0 //2clk
159 #define B7_Trcd 0x1 //3clk
160 #define B7_SCAN 0x1 //9bit
163 #define REFEN 0x1 //Refresh enable
164 #define TREFMD 0x0 //CBR(CAS before RAS)/Auto refresh
165 #define Trp 0x0 //2clk
166 #define Trc 0x3 //7clk
168 #define Tchr 0x2 //3clk
169 #define REFCNT 1113 //period=15.6us, HCLK=60Mhz, (2048+1-15.6*60)
171 //-----------------------------------------------------------------------------