1 #ifndef CYGONCE_SMDK2410_H
2 #define CYGONCE_SMDK2410_H
4 //=============================================================================
8 // Platform specific support (register layout, etc)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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30 // or inline functions from this file, or you compile this file and link it
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): michael anburaj <michaelanburaj@hotmail.com>
47 // Contributors: michael anburaj <michaelanburaj@hotmail.com>
49 // Purpose: SMDK2410 platform specific support definitions
51 // Usage: #include <cyg/hal/s3c2410x.h>
53 //####DESCRIPTIONEND####
55 //=============================================================================
57 #include <pkgconf/hal_arm_arm9_smdk2410.h>
59 // Memory layout details needed by conversion macro
60 #define SMDK2410_SDRAM_PHYS_BASE 0x30000000
61 #define SMDK2410_SDRAM_VIRT_BASE 0x00000000
63 #define SMDK2410_FLASH_PHYS_BASE 0x00000000
64 #define SMDK2410_FLASH_VIRT_BASE 0x80000000
68 #define FCLK CYGNUM_HAL_ARM_SMDK2410_CPU_CLOCK
69 #define HCLK CYGNUM_HAL_ARM_SMDK2410_BUS_CLOCK
70 #define PCLK CYGNUM_HAL_ARM_SMDK2410_PERIPHERAL_CLOCK
75 #define BWSCON 0x48000000 //Bus width & wait status
76 #define BANKCON0 0x48000004 //Boot ROM control
77 #define BANKCON1 0x48000008 //BANK1 control
78 #define BANKCON2 0x4800000c //BANK2 cControl
79 #define BANKCON3 0x48000010 //BANK3 control
80 #define BANKCON4 0x48000014 //BANK4 control
81 #define BANKCON5 0x48000018 //BANK5 control
82 #define BANKCON6 0x4800001c //BANK6 control
83 #define BANKCON7 0x48000020 //BANK7 control
84 #define REFRESH 0x48000024 //DRAM/SDRAM refresh
85 #define BANKSIZE 0x48000028 //Flexible Bank Size
86 #define MRSRB6 0x4800002c //Mode register set for SDRAM
87 #define MRSRB7 0x48000030 //Mode register set for SDRAM
94 #define SRCPND 0x4a000000 //Interrupt request status
95 #define INTMOD 0x4a000004 //Interrupt mode control
96 #define INTMSK 0x4a000008 //Interrupt mask control
97 #define PRIORITY 0x4a00000a //IRQ priority control
98 #define INTPND 0x4a000010 //Interrupt request status
101 #define BIT_EINT0 (0x1)
102 #define BIT_EINT1 (0x1<<1)
103 #define BIT_EINT2 (0x1<<2)
104 #define BIT_EINT3 (0x1<<3)
105 #define BIT_EINT4_7 (0x1<<4)
106 #define BIT_EINT8_23 (0x1<<5)
107 #define BIT_NOTUSED6 (0x1<<6)
108 #define BIT_BAT_FLT (0x1<<7)
109 #define BIT_TICK (0x1<<8)
110 #define BIT_WDT (0x1<<9)
111 #define BIT_TIMER0 (0x1<<10)
112 #define BIT_TIMER1 (0x1<<11)
113 #define BIT_TIMER2 (0x1<<12)
114 #define BIT_TIMER3 (0x1<<13)
115 #define BIT_TIMER4 (0x1<<14)
116 #define BIT_UART2 (0x1<<15)
117 #define BIT_LCD (0x1<<16)
118 #define BIT_DMA0 (0x1<<17)
119 #define BIT_DMA1 (0x1<<18)
120 #define BIT_DMA2 (0x1<<19)
121 #define BIT_DMA3 (0x1<<20)
122 #define BIT_SDI (0x1<<21)
123 #define BIT_SPI0 (0x1<<22)
124 #define BIT_UART1 (0x1<<23)
125 #define BIT_NOTUSED24 (0x1<<24)
126 #define BIT_USBD (0x1<<25)
127 #define BIT_USBH (0x1<<26)
128 #define BIT_IIC (0x1<<27)
129 #define BIT_UART0 (0x1<<28)
130 #define BIT_SPI1 (0x1<<29)
131 #define BIT_RTCC (0x1<<30)
132 #define BIT_ADC (0x1<<31)
133 #define BIT_ALLMSK (0xffffffff)
135 #define INTOFFSET 0x4a000014 //Interruot request source offset
136 #define SUBSRCPND 0x4a000018 //Sub source pending
137 #define INTSUBMSK 0x4a00001c //Interrupt sub mask
139 #define BIT_SUB_ALLMSK (0x7ff)
140 #define BIT_SUB_ADC (0x1<<10)
141 #define BIT_SUB_TC (0x1<<9)
142 #define BIT_SUB_ERR2 (0x1<<8)
143 #define BIT_SUB_TXD2 (0x1<<7)
144 #define BIT_SUB_RXD2 (0x1<<6)
145 #define BIT_SUB_ERR1 (0x1<<5)
146 #define BIT_SUB_TXD1 (0x1<<4)
147 #define BIT_SUB_RXD1 (0x1<<3)
148 #define BIT_SUB_ERR0 (0x1<<2)
149 #define BIT_SUB_TXD0 (0x1<<1)
150 #define BIT_SUB_RXD0 (0x1<<0)
154 #define DISRC0 0x4b000000 //DMA 0 Initial source
155 #define DISRCC0 0x4b000004 //DMA 0 Initial source control
156 #define DIDST0 0x4b000008 //DMA 0 Initial Destination
157 #define DIDSTC0 0x4b00000c //DMA 0 Initial Destination control
158 #define DCON0 0x4b000010 //DMA 0 Control
159 #define DSTAT0 0x4b000014 //DMA 0 Status
160 #define DCSRC0 0x4b000018 //DMA 0 Current source
161 #define DCDST0 0x4b00001c //DMA 0 Current destination
162 #define DMASKTRIG0 0x4b000020 //DMA 0 Mask trigger
164 #define DISRC1 0x4b000040 //DMA 1 Initial source
165 #define DISRCC1 0x4b000044 //DMA 1 Initial source control
166 #define DIDST1 0x4b000048 //DMA 1 Initial Destination
167 #define DIDSTC1 0x4b00004c //DMA 1 Initial Destination control
168 #define DCON1 0x4b000050 //DMA 1 Control
169 #define DSTAT1 0x4b000054 //DMA 1 Status
170 #define DCSRC1 0x4b000058 //DMA 1 Current source
171 #define DCDST1 0x4b00005c //DMA 1 Current destination
172 #define DMASKTRIG1 0x4b000060 //DMA 1 Mask trigger
174 #define DISRC2 0x4b000080 //DMA 2 Initial source
175 #define DISRCC2 0x4b000084 //DMA 2 Initial source control
176 #define DIDST2 0x4b000088 //DMA 2 Initial Destination
177 #define DIDSTC2 0x4b00008c //DMA 2 Initial Destination control
178 #define DCON2 0x4b000090 //DMA 2 Control
179 #define DSTAT2 0x4b000094 //DMA 2 Status
180 #define DCSRC2 0x4b000098 //DMA 2 Current source
181 #define DCDST2 0x4b00009c //DMA 2 Current destination
182 #define DMASKTRIG2 0x4b0000a0 //DMA 2 Mask trigger
184 #define DISRC3 0x4b0000c0 //DMA 3 Initial source
185 #define DISRCC3 0x4b0000c4 //DMA 3 Initial source control
186 #define DIDST3 0x4b0000c8 //DMA 3 Initial Destination
187 #define DIDSTC3 0x4b0000cc //DMA 3 Initial Destination control
188 #define DCON3 0x4b0000d0 //DMA 3 Control
189 #define DSTAT3 0x4b0000d4 //DMA 3 Status
190 #define DCSRC3 0x4b0000d8 //DMA 3 Current source
191 #define DCDST3 0x4b0000dc //DMA 3 Current destination
192 #define DMASKTRIG3 0x4b0000e0 //DMA 3 Mask trigger
195 // CLOCK & POWER MANAGEMENT
196 #define LOCKTIME 0x4c000000 //PLL lock time counter
197 #define MPLLCON 0x4c000004 //MPLL Control
198 #define UPLLCON 0x4c000008 //UPLL Control
199 #define CLKCON 0x4c00000c //Clock generator control
200 #define CLKSLOW 0x4c000010 //Slow clock control
201 #define CLKDIVN 0x4c000014 //Clock divider control
205 #define LCDCON1 0x4d000000 //LCD control 1
206 #define LCDCON2 0x4d000004 //LCD control 2
207 #define LCDCON3 0x4d000008 //LCD control 3
208 #define LCDCON4 0x4d00000c //LCD control 4
209 #define LCDCON5 0x4d000010 //LCD control 5
210 #define LCDSADDR1 0x4d000014 //STN/TFT Frame buffer start address 1
211 #define LCDSADDR2 0x4d000018 //STN/TFT Frame buffer start address 2
212 #define LCDSADDR3 0x4d00001c //STN/TFT Virtual screen address set
213 #define REDLUT 0x4d000020 //STN Red lookup table
214 #define GREENLUT 0x4d000024 //STN Green lookup table
215 #define BLUELUT 0x4d000028 //STN Blue lookup table
216 #define DITHMODE 0x4d00004c //STN Dithering mode
217 #define TPAL 0x4d000050 //TFT Temporary palette
218 #define LCDINTPND 0x4d000054 //LCD Interrupt pending
219 #define LCDSRCPND 0x4d000058 //LCD Interrupt source
220 #define LCDINTMSK 0x4d00005c //LCD Interrupt mask
221 #define LPCSEL 0x4d000060 //LPC3600 Control
222 #define PALETTE 0x4d000400 //Palette start address
226 #define NFCONF 0x4e000000 //NAND Flash configuration
227 #define NFCMD 0x4e000004 //NADD Flash command
228 #define NFADDR 0x4e000008 //NAND Flash address
229 #define NFDATA 0x4e00000c //NAND Flash data
230 #define NFSTAT 0x4e000010 //NAND Flash operation status
231 #define NFECC 0x4e000014 //NAND Flash ECC
232 #define NFECC0 0x4e000014
233 #define NFECC1 0x4e000015
234 #define NFECC2 0x4e000016
238 #define ULCON0 0x50000000 //UART 0 Line control
239 #define UCON0 0x50000004 //UART 0 Control
240 #define UFCON0 0x50000008 //UART 0 FIFO control
241 #define UMCON0 0x5000000c //UART 0 Modem control
242 #define UTRSTAT0 0x50000010 //UART 0 Tx/Rx status
243 #define UERSTAT0 0x50000014 //UART 0 Rx error status
244 #define UFSTAT0 0x50000018 //UART 0 FIFO status
245 #define UMSTAT0 0x5000001c //UART 0 Modem status
246 #define UBRDIV0 0x50000028 //UART 0 Baud rate divisor
248 #define ULCON1 0x50004000 //UART 1 Line control
249 #define UCON1 0x50004004 //UART 1 Control
250 #define UFCON1 0x50004008 //UART 1 FIFO control
251 #define UMCON1 0x5000400c //UART 1 Modem control
252 #define UTRSTAT1 0x50004010 //UART 1 Tx/Rx status
253 #define UERSTAT1 0x50004014 //UART 1 Rx error status
254 #define UFSTAT1 0x50004018 //UART 1 FIFO status
255 #define UMSTAT1 0x5000401c //UART 1 Modem status
256 #define UBRDIV1 0x50004028 //UART 1 Baud rate divisor
258 #define ULCON2 0x50008000 //UART 2 Line control
259 #define UCON2 0x50008004 //UART 2 Control
260 #define UFCON2 0x50008008 //UART 2 FIFO control
261 #define UMCON2 0x5000800c //UART 2 Modem control
262 #define UTRSTAT2 0x50008010 //UART 2 Tx/Rx status
263 #define UERSTAT2 0x50008014 //UART 2 Rx error status
264 #define UFSTAT2 0x50008018 //UART 2 FIFO status
265 #define UMSTAT2 0x5000801c //UART 2 Modem status
266 #define UBRDIV2 0x50008028 //UART 2 Baud rate divisor
268 #define UTXH0 0x50000020 //UART 0 Transmission Hold
269 #define URXH0 0x50000024 //UART 0 Receive buffer
270 #define UTXH1 0x50004020 //UART 1 Transmission Hold
271 #define URXH1 0x50004024 //UART 1 Receive buffer
272 #define UTXH2 0x50008020 //UART 2 Transmission Hold
273 #define URXH2 0x50008024 //UART 2 Receive buffer
275 #define OFS_ULCON (ULCON0-ULCON0) //UART Line control
276 #define OFS_UCON (UCON0-ULCON0) //UART Control
277 #define OFS_UFCON (UFCON0-ULCON0) //UART FIFO control
278 #define OFS_UMCON (UMCON0-ULCON0) //UART Modem control
279 #define OFS_UTRSTAT (UTRSTAT0-ULCON0)//UART Tx/Rx status
280 #define OFS_UERSTAT (UERSTAT0-ULCON0)//UART Rx error status
281 #define OFS_UFSTAT (UFSTAT0-ULCON0) //UART FIFO status
282 #define OFS_UMSTAT (UMSTAT0-ULCON0) //UART Modem status
283 #define OFS_UBRDIV (UBRDIV0-ULCON0) //UART Baud rate divisor
284 #define OFS_UTXH (UTXH0-ULCON0) //UART Transmission Hold
285 #define OFS_URXH (URXH0-ULCON0) //UART Receive buffer
288 #define SHF_ULCON_WL 0
289 #define MSK_ULCON_WL (0x3<<SHF_ULCON_WL)
290 #define VAL_ULCON_WL_5 (0x0<<SHF_ULCON_WL)
291 #define VAL_ULCON_WL_6 (0x1<<SHF_ULCON_WL)
292 #define VAL_ULCON_WL_7 (0x2<<SHF_ULCON_WL)
293 #define VAL_ULCON_WL_8 (0x3<<SHF_ULCON_WL)
295 #define SHF_ULCON_SB 2
296 #define MSK_ULCON_SB (0x1<<SHF_ULCON_SB)
297 #define VAL_ULCON_SB_1 (0x0<<SHF_ULCON_SB)
298 #define VAL_ULCON_SB_2 (0x1<<SHF_ULCON_SB)
300 #define SHF_ULCON_PM 3
301 #define MSK_ULCON_PM (0x7<<SHF_ULCON_PM)
302 #define VAL_ULCON_PM_N (0x0<<SHF_ULCON_PM)
303 #define VAL_ULCON_PM_O (0x4<<SHF_ULCON_PM)
304 #define VAL_ULCON_PM_E (0x5<<SHF_ULCON_PM)
305 #define VAL_ULCON_PM_FC1 (0x6<<SHF_ULCON_PM)
306 #define VAL_ULCON_PM_FC0 (0x7<<SHF_ULCON_PM)
308 #define SHF_ULCON_IRM 6
309 #define MSK_ULCON_IRM (0x1<<SHF_ULCON_IRM)
310 #define VAL_ULCON_IRM_N (0x0<<SHF_ULCON_IRM)
311 #define VAL_ULCON_IRM_IR (0x1<<SHF_ULCON_IRM)
315 #define TCFG0 0x51000000 //Timer 0 configuration
316 #define TCFG1 0x51000004 //Timer 1 configuration
317 #define TCON 0x51000008 //Timer control
318 #define TCNTB0 0x5100000c //Timer count buffer 0
319 #define TCMPB0 0x51000010 //Timer compare buffer 0
320 #define TCNTO0 0x51000014 //Timer count observation 0
321 #define TCNTB1 0x51000018 //Timer count buffer 1
322 #define TCMPB1 0x5100001c //Timer compare buffer 1
323 #define TCNTO1 0x51000020 //Timer count observation 1
324 #define TCNTB2 0x51000024 //Timer count buffer 2
325 #define TCMPB2 0x51000028 //Timer compare buffer 2
326 #define TCNTO2 0x5100002c //Timer count observation 2
327 #define TCNTB3 0x51000030 //Timer count buffer 3
328 #define TCMPB3 0x51000034 //Timer compare buffer 3
329 #define TCNTO3 0x51000038 //Timer count observation 3
330 #define TCNTB4 0x5100003c //Timer count buffer 4
331 #define TCNTO4 0x51000040 //Timer count observation 4
335 #define FUNC_ADDR_REG 0x52000140 //Function address
336 #define PWR_REG 0x52000144 //Power management
337 #define EP_INT_REG 0x52000148 //EP Interrupt pending and clear
338 #define USB_INT_REG 0x52000158 //USB Interrupt pending and clear
339 #define EP_INT_EN_REG 0x5200015c //Interrupt enable
340 #define USB_INT_EN_REG 0x5200016c
341 #define FRAME_NUM1_REG 0x52000170 //Frame number lower byte
342 #define FRAME_NUM2_REG 0x52000174 //Frame number higher byte
343 #define INDEX_REG 0x52000178 //Register index
344 #define MAXP_REG 0x52000180 //Endpoint max packet
345 #define EP0_CSR 0x52000184 //Endpoint 0 status
346 #define IN_CSR1_REG 0x52000184 //In endpoint control status
347 #define IN_CSR2_REG 0x52000188
348 #define OUT_CSR1_REG 0x52000190 //Out endpoint control status
349 #define OUT_CSR2_REG 0x52000194
350 #define OUT_FIFO_CNT1_REG 0x52000198 //Endpoint out write count
351 #define OUT_FIFO_CNT2_REG 0x5200019c
352 #define EP0_FIFO 0x520001c0 //Endpoint 0 FIFO
353 #define EP1_FIFO 0x520001c4 //Endpoint 1 FIFO
354 #define EP2_FIFO 0x520001c8 //Endpoint 2 FIFO
355 #define EP3_FIFO 0x520001cc //Endpoint 3 FIFO
356 #define EP4_FIFO 0x520001d0 //Endpoint 4 FIFO
357 #define EP1_DMA_CON 0x52000200 //EP1 DMA interface control
358 #define EP1_DMA_UNIT 0x52000204 //EP1 DMA Tx unit counter
359 #define EP1_DMA_FIFO 0x52000208 //EP1 DMA Tx FIFO counter
360 #define EP1_DMA_TTC_L 0x5200020c //EP1 DMA total Tx counter
361 #define EP1_DMA_TTC_M 0x52000210
362 #define EP1_DMA_TTC_H 0x52000214
363 #define EP2_DMA_CON 0x52000218 //EP2 DMA interface control
364 #define EP2_DMA_UNIT 0x5200021c //EP2 DMA Tx unit counter
365 #define EP2_DMA_FIFO 0x52000220 //EP2 DMA Tx FIFO counter
366 #define EP2_DMA_TTC_L 0x52000224 //EP2 DMA total Tx counter
367 #define EP2_DMA_TTC_M 0x52000228
368 #define EP2_DMA_TTC_H 0x5200022c
369 #define EP3_DMA_CON 0x52000240 //EP3 DMA interface control
370 #define EP3_DMA_UNIT 0x52000244 //EP3 DMA Tx unit counter
371 #define EP3_DMA_FIFO 0x52000248 //EP3 DMA Tx FIFO counter
372 #define EP3_DMA_TTC_L 0x5200024c //EP3 DMA total Tx counter
373 #define EP3_DMA_TTC_M 0x52000250
374 #define EP3_DMA_TTC_H 0x52000254
375 #define EP4_DMA_CON 0x52000258 //EP4 DMA interface control
376 #define EP4_DMA_UNIT 0x5200025c //EP4 DMA Tx unit counter
377 #define EP4_DMA_FIFO 0x52000260 //EP4 DMA Tx FIFO counter
378 #define EP4_DMA_TTC_L 0x52000264 //EP4 DMA total Tx counter
379 #define EP4_DMA_TTC_M 0x52000268
380 #define EP4_DMA_TTC_H 0x5200026c
384 #define WTCON 0x53000000 //Watch-dog timer mode
385 #define WTDAT 0x53000004 //Watch-dog timer data
386 #define WTCNT 0x53000008 //Eatch-dog timer count
390 #define IICCON 0x54000000 //IIC control
391 #define IICSTAT 0x54000004 //IIC status
392 #define IICADD 0x54000008 //IIC address
393 #define IICDS 0x5400000c //IIC data shift
397 #define IISCON 0x55000000 //IIS Control
398 #define IISMOD 0x55000004 //IIS Mode
399 #define IISPSR 0x55000008 //IIS Prescaler
400 #define IISFCON 0x5500000c //IIS FIFO control
402 #define IISFIFO 0x55000010 //IIS FIFO entry
406 #define GPACON 0x56000000 //Port A control
407 #define GPADAT 0x56000004 //Port A data
409 #define GPBCON 0x56000010 //Port B control
410 #define GPBDAT 0x56000014 //Port B data
411 #define GPBUP 0x56000018 //Pull-up control B
413 #define GPCCON 0x56000020 //Port C control
414 #define GPCDAT 0x56000024 //Port C data
415 #define GPCUP 0x56000028 //Pull-up control C
417 #define GPDCON 0x56000030 //Port D control
418 #define GPDDAT 0x56000034 //Port D data
419 #define GPDUP 0x56000038 //Pull-up control D
421 #define GPECON 0x56000040 //Port E control
422 #define GPEDAT 0x56000044 //Port E data
423 #define GPEUP 0x56000048 //Pull-up control E
425 #define GPFCON 0x56000050 //Port F control
426 #define GPFDAT 0x56000054 //Port F data
427 #define GPFUP 0x56000058 //Pull-up control F
429 #define GPGCON 0x56000060 //Port G control
430 #define GPGDAT 0x56000064 //Port G data
431 #define GPGUP 0x56000068 //Pull-up control G
433 #define GPHCON 0x56000070 //Port H control
434 #define GPHDAT 0x56000074 //Port H data
435 #define GPHUP 0x56000078 //Pull-up control H
437 #define MISCCR 0x56000080 //Miscellaneous control
438 #define DCLKCON 0x56000084 //DCLK0/1 control
439 #define EXTINT0 0x56000088 //External interrupt control register 0
440 #define EXTINT1 0x5600008c //External interrupt control register 1
441 #define EXTINT2 0x56000090 //External interrupt control register 2
442 #define EINTFLT0 0x56000094 //Reserved
443 #define EINTFLT1 0x56000098 //Reserved
444 #define EINTFLT2 0x5600009c //External interrupt filter control register 2
445 #define EINTFLT3 0x560000a0 //External interrupt filter control register 3
446 #define EINTMASK 0x560000a4 //External interrupt mask
447 #define EINTPEND 0x560000a8 //External interrupt pending
448 #define GSTATUS0 0x560000ac //External pin status
449 #define GSTATUS1 0x560000b0 //Chip ID(0x32410000)
450 #define GSTATUS2 0x560000b4 //Reset type
451 #define GSTATUS3 0x560000b8 //Saved data0(32-bit) before entering POWER_OFF mode
452 #define GSTATUS4 0x560000bc //Saved data0(32-bit) before entering POWER_OFF mode
456 #define RTCCON 0x57000040 //RTC control
457 #define TICNT 0x57000044 //Tick time count
458 #define RTCALM 0x57000050 //RTC alarm control
459 #define ALMSEC 0x57000054 //Alarm second
460 #define ALMMIN 0x57000058 //Alarm minute
461 #define ALMHOUR 0x5700005c //Alarm Hour
462 #define ALMDAY 0x57000060 //Alarm day
463 #define ALMMON 0x57000064 //Alarm month
464 #define ALMYEAR 0x57000068 //Alarm year
465 #define RTCRST 0x5700006c //RTC round reset
466 #define BCDSEC 0x57000070 //BCD second
467 #define BCDMIN 0x57000074 //BCD minute
468 #define BCDHOUR 0x57000078 //BCD hour
469 #define BCDDAY 0x5700007c //BCD day
470 #define BCDDATE 0x57000080 //BCD date
471 #define BCDMON 0x57000084 //BCD month
472 #define BCDYEAR 0x57000088 //BCD year
476 #define ADCCON 0x58000000 //ADC control
477 #define ADCTSC 0x58000004 //ADC touch screen control
478 #define ADCDLY 0x58000008 //ADC start or Interval Delay
479 #define ADCDAT0 0x5800000c //ADC conversion data 0
480 #define ADCDAT1 0x58000010 //ADC conversion data 1
484 #define SPCON0 0x59000000 //SPI0 control
485 #define SPSTA0 0x59000004 //SPI0 status
486 #define SPPIN0 0x59000008 //SPI0 pin control
487 #define SPPRE0 0x5900000c //SPI0 baud rate prescaler
488 #define SPTDAT0 0x59000010 //SPI0 Tx data
489 #define SPRDAT0 0x59000014 //SPI0 Rx data
491 #define SPCON1 0x59000020 //SPI1 control
492 #define SPSTA1 0x59000024 //SPI1 status
493 #define SPPIN1 0x59000028 //SPI1 pin control
494 #define SPPRE1 0x5900002c //SPI1 baud rate prescaler
495 #define SPTDAT1 0x59000030 //SPI1 Tx data
496 #define SPRDAT1 0x59000034 //SPI1 Rx data
500 #define SDICON 0x5a000000 //SDI control
501 #define SDIPRE 0x5a000004 //SDI baud rate prescaler
502 #define SDICARG 0x5a000008 //SDI command argument
503 #define SDICCON 0x5a00000c //SDI command control
504 #define SDICSTA 0x5a000010 //SDI command status
505 #define SDIRSP0 0x5a000014 //SDI response 0
506 #define SDIRSP1 0x5a000018 //SDI response 1
507 #define SDIRSP2 0x5a00001c //SDI response 2
508 #define SDIRSP3 0x5a000020 //SDI response 3
509 #define SDIDTIMER 0x5a000024 //SDI data/busy timer
510 #define SDIBSIZE 0x5a000028 //SDI block size
511 #define SDIDCON 0x5a00002c //SDI data control
512 #define SDIDCNT 0x5a000030 //SDI data remain counter
513 #define SDIDSTA 0x5a000034 //SDI data status
514 #define SDIFSTA 0x5a000038 //SDI FIFO status
515 #define SDIIMSK 0x5a000040 //SDI interrupt mask
517 #define SDIDAT 0x5a00003c //SDI data
520 #endif // CYGONCE_SMDK2410_H
521 //-----------------------------------------------------------------------------
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