1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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15 // Copyright (C) 2006 eCosCentric Ltd
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
46 // Contributors:gthomas, asl
48 // Purpose: AT91SAM7S platform specific support routines
50 // Usage: #include <cyg/hal/hal_platform_setup.h>
52 //####DESCRIPTIONEND####
54 //===========================================================================*/
56 #include <cyg/hal/var_io.h>
57 #include <cyg/hal/plf_io.h>
59 // Macro to initialise the Memory Controller
63 #if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 60000000
64 // When the clock is running faster than 60MHz we need two wait states
65 ldr r1,=(AT91_MC_FMR_2FWS)
67 # if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 30000000
68 // When the clock is running faster than 30MHz we need a wait state
69 ldr r1,=(AT91_MC_FMR_1FWS)
71 // We have a slow clock, no extra wait states are needed
72 ldr r1,=AT91_MC_FMR_0FWS
75 str r1,[r0,#AT91_MC_FMR]
78 // Macro to start the main clock.
79 .macro _main_clock_init
82 // Swap to the slow clock, just to be sure.
83 ldr r1,=(AT91_PMC_MCKR_PRES_CLK|AT91_PMC_MCKR_SLOW_CLK)
84 str r1,[r0,#AT91_PMC_MCKR]
86 #if defined(CYGNUM_HAL_ARM_AT91_CLOCK_TYPE_EXTCLOCK)
87 ldr r1,=(AT91_PMC_MOR_OSCBYPASS)
89 ldr r1,=(AT91_PMC_MOR_OSCCOUNT(6)|AT91_PMC_MOR_MOSCEN)
91 str r1,[r0,#AT91_PMC_MOR]
93 // Wait for oscilator start timeout
95 ldr r1,[r0,#AT91_PMC_SR]
96 ands r1,r1,#AT91_PMC_SR_MOSCS
99 // Set the PLL multiplier and divider. 16 slow clocks go by
100 // before the LOCK bit is set. */
101 ldr r1,=((AT91_PMC_PLLR_DIV(CYGNUM_HAL_ARM_AT91_PLL_DIVIDER))|(AT91_PMC_PLLR_PLLCOUNT(16))|(AT91_PMC_PLLR_MUL(CYGNUM_HAL_ARM_AT91_PLL_MULTIPLIER-1)))
102 str r1,[r0,#AT91_PMC_PLLR]
104 // Wait for PLL locked indication
106 ldr r1,[r0,#AT91_PMC_SR]
107 ands r1,r1,#AT91_PMC_SR_LOCK
110 // Enable the PLL clock and set the prescale to 2 */
111 ldr r1,=(AT91_PMC_MCKR_PRES_CLK_2|AT91_PMC_MCKR_PLL_CLK)
112 str r1,[r0,#AT91_PMC_MCKR]
114 // Wait for the MCLK ready indication
116 ldr r1,[r0,#AT91_PMC_SR]
117 ands r1,r1,#AT91_PMC_SR_MCKRDY
121 // Remap the flash from address 0x0 and place RAM there instead.
124 ldr r0,=0x000004 // Use the underfined instruction exception
126 ldr r2,[r0] // Save away copies so we can restore them
129 eor r4,r3,r4 // XOR the contents of 0x20004
130 str r4,[r1] // and write it
131 ldr r5,[r0] // Read from low memory
134 ldr r0,=AT91_MC // Need to do a remap
136 str r5,[r0,#AT91_MC_RCR]
138 str r3,[r1] // restore the value we changed
141 #if defined(CYG_HAL_STARTUP_ROM)
148 #define PLATFORM_SETUP1 _setup
150 #define PLATFORM_SETUP1
153 //-----------------------------------------------------------------------------
154 // end of hal_platform_setup.h
155 #endif // CYGONCE_HAL_PLATFORM_SETUP_H