1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
2 #define CYGONCE_HAL_PLATFORM_INTS_H
3 //==========================================================================
7 // HAL Interrupt and clock assignments for JTST
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): amichelotti
46 // Contributors: gthomas
48 // Purpose: Define Interrupt support
49 // Description: The interrupt specifics for the JTST board/platform are
52 // Usage: #include <cyg/hal/hal_platform_ints.h>
56 //####DESCRIPTIONEND####
58 //==========================================================================
60 // JTST MAGICHLT is the AIC FIQ that's connected to the halt signal of
62 #define CYGNUM_HAL_INTERRUPT_MAGICHLT 0
64 #define CYGNUM_HAL_INTERRUPT_TIMER0 1
65 #define CYGNUM_HAL_INTERRUPT_TIMER1 2
66 #define CYGNUM_HAL_INTERRUPT_TIMER2 3
67 #define CYGNUM_HAL_INTERRUPT_USART0 4
68 #define CYGNUM_HAL_INTERRUPT_USART1 5
69 #define CYGNUM_HAL_INTERRUPT_SPI0 6
70 #define CYGNUM_HAL_INTERRUPT_SPI1 7
71 #define CYGNUM_HAL_INTERRUPT_SIRQ0 8
72 #define CYGNUM_HAL_INTERRUPT_SIRQ1 9
73 #define CYGNUM_HAL_INTERRUPT_SIRQ2 10
74 #define CYGNUM_HAL_INTERRUPT_SIRQ3 11
75 #define CYGNUM_HAL_INTERRUPT_SIRQ4 12
76 #define CYGNUM_HAL_INTERRUPT_SIRQ5 13
77 //exception signal from DSP
78 #define CYGNUM_HAL_INTERRUPT_MAGICEX 15
79 #define CYGNUM_HAL_INTERRUPT_WATCHDOG 16
80 #define CYGNUM_HAL_INTERRUPT_PIO 17
81 #define CYGNUM_HAL_INTERRUPT_EXT4 24
82 //change mode signal system/run and run/system from DSP
83 //I/O operation are allowed only in system mode
84 #define CYGNUM_HAL_INTERRUPT_MAGICMOD 25
85 #define CYGNUM_HAL_INTERRUPT_EXT5 26
87 #define CYGNUM_HAL_INTERRUPT_ENDTXRX 27
88 #define CYGNUM_HAL_INTERRUPT_EXT0 28
89 #define CYGNUM_HAL_INTERRUPT_EXT1 29
90 #define CYGNUM_HAL_INTERRUPT_EXT2 30
91 #define CYGNUM_HAL_INTERRUPT_EXT3 31
93 #define CYGNUM_HAL_ISR_MIN 0
94 #define CYGNUM_HAL_ISR_MAX 31
95 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
97 // The vector used by the Real time clock
98 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
101 //----------------------------------------------------------------------------
103 __externC void hal_at91_reset_cpu(void);
104 #define HAL_PLATFORM_RESET() hal_at91_reset_cpu()
106 #define HAL_PLATFORM_RESET_ENTRY 0x01010000
108 #endif // CYGONCE_HAL_PLATFORM_INTS_H