1 #ifndef CYGONCE_HAL_PLF_IO_H
2 #define CYGONCE_HAL_PLF_IO_H
3 //=============================================================================
7 // Platform specific registers
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
46 // Contributors:jskov, gthomas
48 // Purpose: AT91/EB40 platform specific registers
50 // Usage: #include <cyg/hal/plf_io.h>
52 //####DESCRIPTIONEND####
54 //=============================================================================
58 #define AT91_USART0 0xFFFD0000
59 #define AT91_USART1 0xFFFCC000
61 #define AT91_US_CR 0x00 // Control register
62 #define AT91_US_CR_RxRESET (1<<2)
63 #define AT91_US_CR_TxRESET (1<<3)
64 #define AT91_US_CR_RxENAB (1<<4)
65 #define AT91_US_CR_RxDISAB (1<<5)
66 #define AT91_US_CR_TxENAB (1<<6)
67 #define AT91_US_CR_TxDISAB (1<<7)
68 #define AT91_US_CR_RSTATUS (1<<8)
69 #define AT91_US_MR 0x04 // Mode register
70 #define AT91_US_MR_CLOCK 4
71 #define AT91_US_MR_CLOCK_MCK (0<<AT91_US_MR_CLOCK)
72 #define AT91_US_MR_CLOCK_MCK8 (1<<AT91_US_MR_CLOCK)
73 #define AT91_US_MR_CLOCK_SCK (2<<AT91_US_MR_CLOCK)
74 #define AT91_US_MR_LENGTH 6
75 #define AT91_US_MR_LENGTH_5 (0<<AT91_US_MR_LENGTH)
76 #define AT91_US_MR_LENGTH_6 (1<<AT91_US_MR_LENGTH)
77 #define AT91_US_MR_LENGTH_7 (2<<AT91_US_MR_LENGTH)
78 #define AT91_US_MR_LENGTH_8 (3<<AT91_US_MR_LENGTH)
79 #define AT91_US_MR_SYNC 8
80 #define AT91_US_MR_SYNC_ASYNC (0<<AT91_US_MR_SYNC)
81 #define AT91_US_MR_SYNC_SYNC (1<<AT91_US_MR_SYNC)
82 #define AT91_US_MR_PARITY 9
83 #define AT91_US_MR_PARITY_EVEN (0<<AT91_US_MR_PARITY)
84 #define AT91_US_MR_PARITY_ODD (1<<AT91_US_MR_PARITY)
85 #define AT91_US_MR_PARITY_SPACE (2<<AT91_US_MR_PARITY)
86 #define AT91_US_MR_PARITY_MARK (3<<AT91_US_MR_PARITY)
87 #define AT91_US_MR_PARITY_NONE (4<<AT91_US_MR_PARITY)
88 #define AT91_US_MR_PARITY_MULTI (6<<AT91_US_MR_PARITY)
89 #define AT91_US_MR_STOP 12
90 #define AT91_US_MR_STOP_1 (0<<AT91_US_MR_STOP)
91 #define AT91_US_MR_STOP_1_5 (1<<AT91_US_MR_STOP)
92 #define AT91_US_MR_STOP_2 (2<<AT91_US_MR_STOP)
93 #define AT91_US_MR_MODE 14
94 #define AT91_US_MR_MODE_NORMAL (0<<AT91_US_MR_MODE)
95 #define AT91_US_MR_MODE_ECHO (1<<AT91_US_MR_MODE)
96 #define AT91_US_MR_MODE_LOCAL (2<<AT91_US_MR_MODE)
97 #define AT91_US_MR_MODE_REMOTE (3<<AT91_US_MR_MODE)
98 #define AT91_US_MR_MODE9 17
99 #define AT91_US_MR_CLKO 18
100 #define AT91_US_IER 0x08 // Interrupt enable register
101 #define AT91_US_IER_RxRDY (1<<0) // Receive data ready
102 #define AT91_US_IER_TxRDY (1<<1) // Transmitter ready
103 #define AT91_US_IER_RxBRK (1<<2) // Break received
104 #define AT91_US_IER_ENDRX (1<<3) // Rx end
105 #define AT91_US_IER_ENDTX (1<<4) // Tx end
106 #define AT91_US_IER_OVRE (1<<5) // Rx overflow
107 #define AT91_US_IER_FRAME (1<<6) // Rx framing error
108 #define AT91_US_IER_PARITY (1<<7) // Rx parity
109 #define AT91_US_IER_TIMEOUT (1<<8) // Rx timeout
110 #define AT91_US_IER_TxEMPTY (1<<9) // Tx empty
111 #define AT91_US_IDR 0x0C // Interrupt disable register
112 #define AT91_US_IMR 0x10 // Interrupt mask register
113 #define AT91_US_CSR 0x14 // Channel status register
114 #define AT91_US_CSR_RxRDY 0x01 // Receive data ready
115 #define AT91_US_CSR_TxRDY 0x02 // Transmit ready
116 #define AT91_US_RHR 0x18 // Receive holding register
117 #define AT91_US_THR 0x1C // Transmit holding register
118 #define AT91_US_BRG 0x20 // Baud rate generator
119 #define AT91_US_RTO 0x24 // Receive time out
120 #define AT91_US_TTG 0x28 // Transmit timer guard
122 #define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud)))
126 #define AT91_PIO 0xFFFF0000
128 #define AT91_PIO_PER 0x00 // PIO enable
129 #define AT91_PIO_PDR 0x04 // PIO disable
130 #define AT91_PIO_PSR 0x08 // PIO status
131 #define AT91_PIO_OER 0x10 // Output enable
132 #define AT91_PIO_ODR 0x14 // Output disable
133 #define AT91_PIO_OSR 0x1C // Output status register
134 #define AT91_PIO_IFER 0x20 // Input Filter enable
135 #define AT91_PIO_IFDR 0x24 // Input Filter disable
136 #define AT91_PIO_IFSR 0x28 // Input Filter status register
137 #define AT91_PIO_SODR 0x30 // Set out bits
138 #define AT91_PIO_CODR 0x34 // Clear out bits
139 #define AT91_PIO_ODSR 0x38 // Output data status register
140 #define AT91_PIO_IER 0x40 // Interrupt enable
141 #define AT91_PIO_IDR 0x44 // Interrupt disable
142 #define AT91_PIO_IMR 0x48 // Interrupt mask
143 #define AT91_PIO_ISR 0x4C // Interrupt status register
146 // Advanced Interrupt Controller (AIC)
148 #define AT91_AIC 0xFFFFF000
150 #define AT91_AIC_SMR0 ((0*4)+0x000)
151 #define AT91_AIC_SMR1 ((1*4)+0x000)
152 #define AT91_AIC_SMR2 ((2*4)+0x000)
153 #define AT91_AIC_SMR3 ((3*4)+0x000)
154 #define AT91_AIC_SMR4 ((4*4)+0x000)
155 #define AT91_AIC_SMR5 ((5*4)+0x000)
156 #define AT91_AIC_SMR6 ((6*4)+0x000)
157 #define AT91_AIC_SMR7 ((7*4)+0x000)
158 #define AT91_AIC_SMR8 ((8*4)+0x000)
159 #define AT91_AIC_SMR9 ((9*4)+0x000)
160 #define AT91_AIC_SMR10 ((10*4)+0x000)
161 #define AT91_AIC_SMR11 ((11*4)+0x000)
162 #define AT91_AIC_SMR12 ((12*4)+0x000)
163 #define AT91_AIC_SMR13 ((13*4)+0x000)
164 #define AT91_AIC_SMR14 ((14*4)+0x000)
165 #define AT91_AIC_SMR15 ((15*4)+0x000)
166 #define AT91_AIC_SMR16 ((16*4)+0x000)
167 #define AT91_AIC_SMR17 ((17*4)+0x000)
168 #define AT91_AIC_SMR18 ((18*4)+0x000)
169 #define AT91_AIC_SMR19 ((19*4)+0x000)
170 #define AT91_AIC_SMR20 ((20*4)+0x000)
171 #define AT91_AIC_SMR21 ((21*4)+0x000)
172 #define AT91_AIC_SMR22 ((22*4)+0x000)
173 #define AT91_AIC_SMR23 ((23*4)+0x000)
174 #define AT91_AIC_SMR24 ((24*4)+0x000)
175 #define AT91_AIC_SMR25 ((25*4)+0x000)
176 #define AT91_AIC_SMR26 ((26*4)+0x000)
177 #define AT91_AIC_SMR27 ((27*4)+0x000)
178 #define AT91_AIC_SMR28 ((28*4)+0x000)
179 #define AT91_AIC_SMR29 ((29*4)+0x000)
180 #define AT91_AIC_SMR30 ((30*4)+0x000)
181 #define AT91_AIC_SMR31 ((31*4)+0x000)
182 #define AT91_AIC_SMR_LEVEL_LOW (0<<5)
183 #define AT91_AIC_SMR_LEVEL_HI (2<<5)
184 #define AT91_AIC_SMR_EDGE_NEG (1<<5)
185 #define AT91_AIC_SMR_EDGE_POS (3<<5)
186 #define AT91_AIC_SMR_PRIORITY 0x07
187 #define AT91_AIC_SVR0 ((0*4)+0x080)
188 #define AT91_AIC_SVR1 ((1*4)+0x080)
189 #define AT91_AIC_SVR2 ((2*4)+0x080)
190 #define AT91_AIC_SVR3 ((3*4)+0x080)
191 #define AT91_AIC_SVR4 ((4*4)+0x080)
192 #define AT91_AIC_SVR5 ((5*4)+0x080)
193 #define AT91_AIC_SVR6 ((6*4)+0x080)
194 #define AT91_AIC_SVR7 ((7*4)+0x080)
195 #define AT91_AIC_SVR8 ((8*4)+0x080)
196 #define AT91_AIC_SVR9 ((9*4)+0x080)
197 #define AT91_AIC_SVR10 ((10*4)+0x080)
198 #define AT91_AIC_SVR11 ((11*4)+0x080)
199 #define AT91_AIC_SVR12 ((12*4)+0x080)
200 #define AT91_AIC_SVR13 ((13*4)+0x080)
201 #define AT91_AIC_SVR14 ((14*4)+0x080)
202 #define AT91_AIC_SVR15 ((15*4)+0x080)
203 #define AT91_AIC_SVR16 ((16*4)+0x080)
204 #define AT91_AIC_SVR17 ((17*4)+0x080)
205 #define AT91_AIC_SVR18 ((18*4)+0x080)
206 #define AT91_AIC_SVR19 ((19*4)+0x080)
207 #define AT91_AIC_SVR20 ((20*4)+0x080)
208 #define AT91_AIC_SVR21 ((21*4)+0x080)
209 #define AT91_AIC_SVR22 ((22*4)+0x080)
210 #define AT91_AIC_SVR23 ((23*4)+0x080)
211 #define AT91_AIC_SVR24 ((24*4)+0x080)
212 #define AT91_AIC_SVR25 ((25*4)+0x080)
213 #define AT91_AIC_SVR26 ((26*4)+0x080)
214 #define AT91_AIC_SVR27 ((27*4)+0x080)
215 #define AT91_AIC_SVR28 ((28*4)+0x080)
216 #define AT91_AIC_SVR29 ((29*4)+0x080)
217 #define AT91_AIC_SVR30 ((30*4)+0x080)
218 #define AT91_AIC_SVR31 ((31*4)+0x080)
219 #define AT91_AIC_IVR 0x100
220 #define AT91_AIC_FVR 0x104
221 #define AT91_AIC_ISR 0x108
222 #define AT91_AIC_IPR 0x10C
223 #define AT91_AIC_IMR 0x110
224 #define AT91_AIC_CISR 0x114
225 #define AT91_AIC_IECR 0x120
226 #define AT91_AIC_IDCR 0x124
227 #define AT91_AIC_ICCR 0x128
228 #define AT91_AIC_ISCR 0x12C
229 #define AT91_AIC_EOI 0x130
230 #define AT91_AIC_SVR 0x134
234 #define AT91_TC 0xFFFE0000
235 #define AT91_TC_TC0 0x00
236 #define AT91_TC_CCR 0x00
237 #define AT91_TC_CCR_CLKEN 0x01
238 #define AT91_TC_CCR_CLKDIS 0x02
239 #define AT91_TC_CCR_TRIG 0x04
240 #define AT91_TC_CMR 0x04
241 // Capture mode definitions
242 #define AT91_TC_CMR_CLKS 0
243 #define AT91_TC_CMR_CLKS_MCK2 (0<<0)
244 #define AT91_TC_CMR_CLKS_MCK8 (1<<0)
245 #define AT91_TC_CMR_CLKS_MCK32 (2<<0)
246 #define AT91_TC_CMR_CLKS_MCK128 (3<<0)
247 #define AT91_TC_CMR_CLKS_MCK1024 (4<<0)
248 #define AT91_TC_CMR_CLKS_XC0 (5<<0)
249 #define AT91_TC_CMR_CLKS_XC1 (6<<0)
250 #define AT91_TC_CMR_CLKS_XC2 (7<<0)
251 #define AT91_TC_CMR_CLKI (1<<3)
252 #define AT91_TC_CMR_BURST_NONE (0<<4)
253 #define AT91_TC_CMR_BURST_XC0 (1<<4)
254 #define AT91_TC_CMR_BURST_XC1 (2<<4)
255 #define AT91_TC_CMR_BURST_XC2 (3<<4)
256 #define AT91_TC_CMR_LDBSTOP (1<<6)
257 #define AT91_TC_CMR_LDBDIS (1<<7)
258 #define AT91_TC_CMR_TRIG_NONE (0<<8)
259 #define AT91_TC_CMR_TRIG_NEG (1<<8)
260 #define AT91_TC_CMR_TRIG_POS (2<<8)
261 #define AT91_TC_CMR_TRIG_BOTH (3<<8)
262 #define AT91_TC_CMR_EXT_TRIG_TIOB (0<<10)
263 #define AT91_TC_CMR_EXT_TRIG_TIOA (1<<10)
264 #define AT91_TC_CMR_CPCTRG (1<<14)
265 #define AT91_TC_CMR_LDRA_NONE (0<<16)
266 #define AT91_TC_CMR_LDRA_TIOA_NEG (1<<16)
267 #define AT91_TC_CMR_LDRA_TIOA_POS (2<<16)
268 #define AT91_TC_CMR_LDRA_TIOA_BOTH (3<<16)
269 #define AT91_TC_CMR_LDRB_NONE (0<<16)
270 #define AT91_TC_CMR_LDRB_TIOA_NEG (1<<16)
271 #define AT91_TC_CMR_LDRB_TIOA_POS (2<<16)
272 #define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<16)
273 // Waveform mode definitions [missing]
274 #define AT91_TC_CV 0x10
275 #define AT91_TC_RA 0x14
276 #define AT91_TC_RB 0x18
277 #define AT91_TC_RC 0x1C
278 #define AT91_TC_SR 0x20
279 #define AT91_TC_SR_COVF (1<<0) // Counter overrun
280 #define AT91_TC_SR_LOVR (1<<1) // Load overrun
281 #define AT91_TC_SR_CPA (1<<2) // RA compare
282 #define AT91_TC_SR_CPB (1<<3) // RB compare
283 #define AT91_TC_SR_CPC (1<<4) // RC compare
284 #define AT91_TC_SR_LDRA (1<<5) // Load A status
285 #define AT91_TC_SR_LDRB (1<<6) // Load B status
286 #define AT91_TC_SR_EXT (1<<7) // External trigger
287 #define AT91_TC_SR_CLKSTA (1<<16) // Clock enable/disable status
288 #define AT91_TC_SR_MTIOA (1<<17) // TIOA mirror
289 #define AT91_TC_SR_MTIOB (1<<18) // TIOB mirror
290 #define AT91_TC_IER 0x24
291 #define AT91_TC_IER_COVF (1<<0) // Counter overrun
292 #define AT91_TC_IER_LOVR (1<<1) // Load overrun
293 #define AT91_TC_IER_CPA (1<<2) // RA compare
294 #define AT91_TC_IER_CPB (1<<3) // RB compare
295 #define AT91_TC_IER_CPC (1<<4) // RC compare
296 #define AT91_TC_IER_LDRA (1<<5) // Load A status
297 #define AT91_TC_IER_LDRB (1<<6) // Load B status
298 #define AT91_TC_IER_EXT (1<<7) // External trigger
299 #define AT91_TC_IDR 0x28
300 #define AT91_TC_IMR 0x2C
301 #define AT91_TC_TC1 0x40
302 #define AT91_TC_TC2 0x80
303 #define AT91_TC_BCR 0xC0
304 #define AT91_TC_BCR_SYNC 0x01
305 #define AT91_TC_BMR 0xC4
307 // External Bus Interface
309 #define AT91_EBI 0xFFE00000 // Base
311 #define AT91_EBI_CSR0 0x00 // Chip selects 0 - 7
312 #define AT91_EBI_CSR1 0x04
313 #define AT91_EBI_CSR2 0x08
314 #define AT91_EBI_CSR3 0x0C
315 #define AT91_EBI_CSR4 0x10
316 #define AT91_EBI_CSR5 0x14
317 #define AT91_EBI_CSR6 0x18
318 #define AT91_EBI_CSR7 0x1C
320 #define AT91_EBI_RCR 0x20 // Reset control
321 #define AT91_EBI_MCR 0x24 // Memory control
323 #define AT91_EBI_CSEN (1<<13) // Chip Select enable
324 #define AT91_EBI_BAT_BYTE_WRITE (0<<12) // Byte write access
325 #define AT91_EBI_BAT_BYTE_SELECT (1<<12) // Byte select access type
326 #define AT91_EBI_TDF0 (0<<9) // 0 cycles of data float time
327 #define AT91_EBI_TDF1 (1<<9) // 1
328 #define AT91_EBI_TDF2 (2<<9) // 2, etc
329 #define AT91_EBI_TDF3 (3<<9) //
330 #define AT91_EBI_TDF4 (4<<9) //
331 #define AT91_EBI_TDF5 (5<<9) //
332 #define AT91_EBI_TDF6 (6<<9) //
333 #define AT91_EBI_TDF7 (7<<9) //
335 #define AT91_EBI_PAGES_1M (0<<7) // 1MByte page size
336 #define AT91_EBI_PAGES_4M (1<<7) // 4MByte page size
337 #define AT91_EBI_PAGES_16M (2<<7) // 16MByte page size
338 #define AT91_EBI_PAGES_64M (3<<7) // 64MByte page size
340 #define AT91_EBI_WSE (1<<5) // Wait State enable
342 #define AT91_EBI_NWS_1 (0<<2) // 1 wait state
343 #define AT91_EBI_NWS_2 (1<<2) // 1 wait state
344 #define AT91_EBI_NWS_3 (2<<2) // 1 wait state
345 #define AT91_EBI_NWS_4 (3<<2) // 1 wait state
346 #define AT91_EBI_NWS_5 (4<<2) // 1 wait state
347 #define AT91_EBI_NWS_6 (5<<2) // 1 wait state
348 #define AT91_EBI_NWS_7 (6<<2) // 1 wait state
349 #define AT91_EBI_NWS_8 (7<<2) // 1 wait state
351 #define AT91_EBI_DBW_8 (2<<0) // 8-bit data bus width
352 #define AT91_EBI_DBW_16 (1<<0) // 16-bit data bus width
354 #define AT91_EBI_RCB (1<<0) // Remap command bit
356 #define AT91_EBI_ALE_16M (0<<0) // Address line enable: A20,A21,A22,A23
357 #define AT91_EBI_ALE_8M (4<<0) // " " A20,A21,A22 CS4
358 #define AT91_EBI_ALE_4M (5<<0) // " " A20,A21 CS4,CS5
359 #define AT91_EBI_ALE_2M (6<<0) // " " A20 CS4,CS5,CS6
360 #define AT91_EBI_ALE_1M (7<<0) // " " CS4,CS5,CS6,CS7
362 #define AT91_EBI_DRP_STANDARD (0<<4) // Standard data read protocol
363 #define AT91_EBI_DRP_EARLY (1<<4) // Early data read protocol
367 // Power Savings control
369 #define AT91_PS 0xFFFF4000
370 #define AT91_PS_CR 0x000 // Control
371 #define AT91_PS_PCER 0x004 // Peripheral clock enable
372 #define AT91_PS_PCDR 0x004 // Peripheral clock disable
373 #define AT91_PS_PCSR 0x004 // Peripheral clock status
377 #define AT91_WD 0xFFFF8000
378 #define AT91_WD_OMR 0x00
379 #define AT91_WD_OMR_WDEN 0x00000001
380 #define AT91_WD_OMR_RSTEN 0x00000002
381 #define AT91_WD_OMR_IRQEN 0x00000004
382 #define AT91_WD_OMR_EXTEN 0x00000008
383 #define AT91_WD_OMR_OKEY (0x00000234 << 4)
384 #define AT91_WD_CMR 0x04
385 #define AT91_WD_CMR_WDCLKS 0x00000003
386 #define AT91_WD_CMR_HPCV 0x0000003C
387 #define AT91_WD_CMR_CKEY (0x0000006E << 7)
388 #define AT91_WD_CR 0x08
389 #define AT91_WD_CR_RSTKEY 0x0000C071
390 #define AT91_WD_SR 0x0C
391 #define AT91_WD_SR_WDOVF 0x00000001
394 //-----------------------------------------------------------------------------
396 #endif // CYGONCE_HAL_PLF_IO_H
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