1 #ifndef CYGONCE_HAL_PLF_IO_H
2 #define CYGONCE_HAL_PLF_IO_H
3 //=============================================================================
7 // Platform specific registers
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
48 // Purpose: ARM/E7T platform specific registers
50 // Usage: #include <cyg/hal/plf_io.h>
52 //####DESCRIPTIONEND####
54 //=============================================================================
56 // Platform doesn't need address munging even if configures as big-endian
58 #define HAL_IO_MACROS_NO_ADDRESS_MUNGING
60 // non-caching by accessing addr|0x04000000
62 #define E7T_REG_BASE 0x07ff0000
64 // -----------------------------------------------------------------------------
65 // System config (register bases and caching)
66 #define E7T_SYSCFG (E7T_REG_BASE + 0x0000)
68 #define E7T_SYSCFG_SDM 0x80000000
69 #define E7T_SYSCFG_PD_ID_MASK 0x3c000000
70 #define E7T_SYSCFG_SRBBP_MASK 0x03ff0000 // address/64k
71 #define E7T_SYSCFG_ISBBP_MASK 0x0000ffc0 // a25-a16
72 #define E7T_SYSCFG_CM_MASK 0x00000030
73 #define E7T_SYSCFG_CM_4R_4C 0x00000000
74 #define E7T_SYSCFG_CM_0R_8C 0x00000010
75 #define E7T_SYSCFG_CM_8R_0C 0x00000020
76 #define E7T_SYSCFG_WE 0x00000004 // only KS32C50100?
77 #define E7T_SYSCFG_CE 0x00000002
78 #define E7T_SYSCFG_SE 0x00000001
80 #define E7T_CLKCON (E7T_REG_BASE + 0x3000)
82 #define E7T_EXTACON0 (E7T_REG_BASE + 0x3008)
83 #define E7T_EXTACON1 (E7T_REG_BASE + 0x300c)
85 //-----------------------------------------------------------------------------
86 // Memory banks data width
87 #define E7T_EXTDBWTH (E7T_REG_BASE + 0x3010)
89 #define E7T_EXTDBWTH_MASK 3
90 #define E7T_EXTDBWTH_8BIT 1
91 #define E7T_EXTDBWTH_16BIT 2
92 #define E7T_EXTDBWTH_32BIT 3
94 #define E7T_EXTDBWTH_DSR0_shift 0
95 #define E7T_EXTDBWTH_DSR1_shift 2
96 #define E7T_EXTDBWTH_DSR2_shift 4
97 #define E7T_EXTDBWTH_DSR3_shift 6
98 #define E7T_EXTDBWTH_DSR4_shift 8
99 #define E7T_EXTDBWTH_DSR5_shift 10
100 #define E7T_EXTDBWTH_DSD0_shift 12
101 #define E7T_EXTDBWTH_DSD1_shift 14
102 #define E7T_EXTDBWTH_DSD2_shift 16
103 #define E7T_EXTDBWTH_DSD3_shift 18
104 #define E7T_EXTDBWTH_DSX0_shift 20
105 #define E7T_EXTDBWTH_DSX1_shift 22
106 #define E7T_EXTDBWTH_DSX2_shift 24
107 #define E7T_EXTDBWTH_DSX3_shift 26
109 // -----------------------------------------------------------------------------
110 // Bank locations and timing
111 #define E7T_ROMCON0 (E7T_REG_BASE + 0x3014)
112 #define E7T_ROMCON1 (E7T_REG_BASE + 0x3018)
113 #define E7T_ROMCON2 (E7T_REG_BASE + 0x301c)
114 #define E7T_ROMCON3 (E7T_REG_BASE + 0x3020)
115 #define E7T_ROMCON4 (E7T_REG_BASE + 0x3024)
116 #define E7T_ROMCON5 (E7T_REG_BASE + 0x3028)
118 #define E7T_ROMCON_PMC_MASK 0x00000003
119 #define E7T_ROMCON_PMC_ROM 0x00000000
120 #define E7T_ROMCON_PMC_4W_PAGE 0x00000001
121 #define E7T_ROMCON_PMC_8W_PAGE 0x00000002
122 #define E7T_ROMCON_PMC_16W_PAGE 0x00000003
124 #define E7T_ROMCON_TPA_MASK 0x0000000c
125 #define E7T_ROMCON_TPA_5C 0x00000000
126 #define E7T_ROMCON_TPA_2C 0x00000004
127 #define E7T_ROMCON_TPA_3C 0x00000008
128 #define E7T_ROMCON_TPA_4C 0x0000000c
130 #define E7T_ROMCON_TACC_MASK 0x00000070
131 #define E7T_ROMCON_TACC_DISABLE 0x00000000
132 #define E7T_ROMCON_TACC_2C 0x00000010
133 #define E7T_ROMCON_TACC_3C 0x00000020
134 #define E7T_ROMCON_TACC_4C 0x00000030
135 #define E7T_ROMCON_TACC_5C 0x00000040
136 #define E7T_ROMCON_TACC_6C 0x00000050
137 #define E7T_ROMCON_TACC_7C 0x00000060
139 #define E7T_ROMCON_BASE_MASK 0x000ffc00
140 #define E7T_ROMCON_BASE_shift 10
142 #define E7T_ROMCON_NEXT_MASK 0x3ff00000
143 #define E7T_ROMCON_NEXT_shift 20
147 #define E7T_DRAMCON0 (E7T_REG_BASE + 0x302c)
148 #define E7T_DRAMCON1 (E7T_REG_BASE + 0x3030)
149 #define E7T_DRAMCON2 (E7T_REG_BASE + 0x3034)
150 #define E7T_DRAMCON3 (E7T_REG_BASE + 0x3038)
151 #define E7T_REFEXTCON (E7T_REG_BASE + 0x303c)
153 //-----------------------------------------------------------------------------
156 #define E7T_INTMOD (E7T_REG_BASE + 0x4000)
157 #define E7T_INTPND (E7T_REG_BASE + 0x4004)
158 #define E7T_INTMSK (E7T_REG_BASE + 0x4008)
159 #define E7T_INTPRI0 (E7T_REG_BASE + 0x400c)
160 #define E7T_INTPRI1 (E7T_REG_BASE + 0x4010)
161 #define E7T_INTPRI2 (E7T_REG_BASE + 0x4014)
162 #define E7T_INTPRI3 (E7T_REG_BASE + 0x4018)
163 #define E7T_INTPRI4 (E7T_REG_BASE + 0x401c)
164 #define E7T_INTPRI5 (E7T_REG_BASE + 0x4020)
165 #define E7T_INTOFFSET (E7T_REG_BASE + 0x4024)
166 #define E7T_PNDPRI (E7T_REG_BASE + 0x4028)
167 #define E7T_PNDTEST (E7T_REG_BASE + 0x402c)
168 #define E7T_INTOFFSET_FIQ (E7T_REG_BASE + 0x4030)
169 #define E7T_INTOFFSET_IRQ (E7T_REG_BASE + 0x4034)
171 #define E7T_INTMSK_GLOBAL (1<<21)
173 //-----------------------------------------------------------------------------
176 #define E7T_IOPMOD (E7T_REG_BASE + 0x5000)
177 #define E7T_IOPCON (E7T_REG_BASE + 0x5004)
178 #define E7T_IOPDATA (E7T_REG_BASE + 0x5008)
180 //-----------------------------------------------------------------------------
183 #define E7T_TMOD (E7T_REG_BASE + 0x6000)
184 #define E7T_TDATA0 (E7T_REG_BASE + 0x6004)
185 #define E7T_TDATA1 (E7T_REG_BASE + 0x6008)
186 #define E7T_TCNT0 (E7T_REG_BASE + 0x600c)
187 #define E7T_TCNT1 (E7T_REG_BASE + 0x6010)
189 #define E7T_TMOD_TE0 0x00000001
190 #define E7T_TMOD_TMD0 0x00000002
191 #define E7T_TMOD_TCLR0 0x00000004
192 #define E7T_TMOD_TE1 0x00000008
193 #define E7T_TMOD_TMD1 0x00000010
194 #define E7T_TMOD_TCLR1 0x00000020
197 //-----------------------------------------------------------------------------
200 #define E7T_UART0_BASE (E7T_REG_BASE + 0xd000)
201 #define E7T_UART1_BASE (E7T_REG_BASE + 0xe000)
203 #define E7T_UART_LCON 0x0000
204 #define E7T_UART_CON 0x0004
205 #define E7T_UART_STAT 0x0008
206 #define E7T_UART_TXBUF 0x000c
207 #define E7T_UART_RXBUF 0x0010
208 #define E7T_UART_BRDIV 0x0014
209 #define E7T_UART_BRDCNT 0x0018
210 #define E7T_UART_BRDCLK 0x001c
212 #define E7T_UART_LCON_5_DBITS 0x00
213 #define E7T_UART_LCON_6_DBITS 0x01
214 #define E7T_UART_LCON_7_DBITS 0x02
215 #define E7T_UART_LCON_8_DBITS 0x03
216 #define E7T_UART_LCON_1_SBITS 0x00
217 #define E7T_UART_LCON_2_SBITS 0x04
218 #define E7T_UART_LCON_NO_PARITY 0x00
219 #define E7T_UART_LCON_EVEN_PARITY 0x00
220 #define E7T_UART_LCON_ODD_PARITY 0x28
221 #define E7T_UART_LCON_1_PARITY 0x30
222 #define E7T_UART_LCON_0_PARITY 0x38
223 #define E7T_UART_LCON_SCS 0x40
224 #define E7T_UART_LCON_IR 0x80
226 #define E7T_UART_CON_RXM_MASK 0x03
227 #define E7T_UART_CON_RXM_INT 0x01
228 #define E7T_UART_CON_TXM_MASK 0x0c
229 #define E7T_UART_CON_TXM_INT 0x08
230 #define E7T_UART_CON_RX_ERR_INT 0x04
233 #define E7T_UART_STAT_DTR 0x10
234 #define E7T_UART_STAT_RDR 0x20
235 #define E7T_UART_STAT_TXE 0x40 // tx empty
236 #define E7T_UART_STAT_TC 0x80 // tx complete
238 //-----------------------------------------------------------------------------
240 #define E7T_CACHE_SET0_ADDR 0x14000000
241 #define E7T_CACHE_SET1_ADDR 0x14800000
242 #define E7T_CACHE_TAG_ADDR 0x15000000
244 //-----------------------------------------------------------------------------
247 #define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_)
249 //-----------------------------------------------------------------------------
251 #endif // CYGONCE_HAL_PLF_IO_H