packages/hal/arm/e7t/v2_0/src/hal_diag.c

   1 /*=============================================================================
   2 //
   3 //      hal_diag.c
   4 //
   5 //      HAL diagnostic output code
   6 //
   7 //=============================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
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  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //=============================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):   jskov
  44 // Contributors:jskov
  45 // Date:        2001-03-16
  46 // Purpose:     HAL diagnostic output
  47 // Description: Implementations of HAL diagnostic output support.
  48 //
  49 //####DESCRIPTIONEND####
  50 //
  51 //===========================================================================*/
  52
  53 #include <pkgconf/hal.h>
  54 #include CYGBLD_HAL_PLATFORM_H
  55
  56 #include <cyg/infra/cyg_type.h>         // base types
  57
  58 #include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
  59 #include <cyg/hal/hal_io.h>             // IO macros
  60 #include <cyg/hal/hal_if.h>             // interface API
  61 #include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
  62 #include <cyg/hal/hal_misc.h>           // Helper functions
  63 #include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
  64
  65 #include <cyg/hal/plf_io.h>             // SIO registers
  66
  67 #define SIO_BRDDIV (((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD)<<4))
  68
  69 //-----------------------------------------------------------------------------
  70 typedef struct {
  71     cyg_uint8* base;
  72     cyg_int32 msec_timeout;
  73     int isr_vector_rx;
  74     int isr_vector_tx;
  75 } channel_data_t;
  76
  77 //-----------------------------------------------------------------------------
  78
  79 char hextab[] = "0123456789ABCDEF";
  80
  81 void putc_ser(int c)
  82 {
  83     cyg_uint8* base = (cyg_uint8*)E7T_UART1_BASE;
  84     cyg_uint32 status;
  85     do {
  86         HAL_READ_UINT32(base+E7T_UART_STAT, status);
  87     } while ((status & E7T_UART_STAT_TXE) == 0);
  88
  89     HAL_WRITE_UINT32(base+E7T_UART_TXBUF, c);
  90 }
  91
  92 void putint(int a)
  93 {
  94     int i;
  95     putc_ser('0');
  96     putc_ser('x');
  97     for (i = 0; i < 8; i++) {
  98         putc_ser(hextab[(a>>(28-(4*i))) & 0x0f]);
  99     }
 100     putc_ser('\r');
 101     putc_ser('\n');
 102 }
 103
 104 void
 105 init_ser(void)
 106 {
 107     cyg_uint8* base = (cyg_uint8*)E7T_UART1_BASE;
 108
 109     // 8-1-no parity.
 110     HAL_WRITE_UINT32(base+E7T_UART_LCON,
 111                      E7T_UART_LCON_8_DBITS|E7T_UART_LCON_1_SBITS|E7T_UART_LCON_NO_PARITY);
 112
 113     // Mask interrupts.
 114     HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_RX);
 115     HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_TX);
 116
 117     HAL_WRITE_UINT32(base+E7T_UART_BRDIV, SIO_BRDDIV);
 118 }
 119
 120 //-----------------------------------------------------------------------------
 121
 122 static void
 123 cyg_hal_plf_serial_init_channel(void* __ch_data)
 124 {
 125     cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 126
 127     // 8-1-no parity.
 128     HAL_WRITE_UINT32(base+E7T_UART_LCON,
 129                      E7T_UART_LCON_8_DBITS|E7T_UART_LCON_1_SBITS|E7T_UART_LCON_NO_PARITY);
 130
 131     HAL_WRITE_UINT32(base+E7T_UART_BRDIV, SIO_BRDDIV);
 132
 133     // Mask interrupts
 134     HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_rx);
 135     HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_tx);
 136
 137     // Enable RX and TX
 138     HAL_WRITE_UINT32(base+E7T_UART_CON, E7T_UART_CON_RXM_INT|E7T_UART_CON_TXM_INT);
 139 }
 140
 141 void
 142 cyg_hal_plf_serial_putc(void *__ch_data, char c)
 143 {
 144     cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 145     cyg_uint32 status, ch;
 146     CYGARC_HAL_SAVE_GP();
 147
 148     do {
 149         HAL_READ_UINT32(base+E7T_UART_STAT, status);
 150     } while ((status & E7T_UART_STAT_TXE) == 0);
 151
 152     ch = (cyg_uint32)c;
 153     HAL_WRITE_UINT32(base+E7T_UART_TXBUF, ch);
 154
 155     CYGARC_HAL_RESTORE_GP();
 156 }
 157
 158 static cyg_bool
 159 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
 160 {
 161     channel_data_t* chan = (channel_data_t*)__ch_data;
 162     cyg_uint8* base = chan->base;
 163     cyg_uint32 stat;
 164     cyg_uint32 c;
 165
 166     HAL_READ_UINT32(base+E7T_UART_STAT, stat);
 167     if ((stat & E7T_UART_STAT_RDR) == 0)
 168         return false;
 169
 170     HAL_READ_UINT32(base+E7T_UART_RXBUF, c);
 171     *ch = (cyg_uint8)(c & 0xff);
 172
 173     HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
 174
 175     return true;
 176 }
 177
 178 cyg_uint8
 179 cyg_hal_plf_serial_getc(void* __ch_data)
 180 {
 181     cyg_uint8 ch;
 182     CYGARC_HAL_SAVE_GP();
 183
 184     while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 185
 186     CYGARC_HAL_RESTORE_GP();
 187     return ch;
 188 }
 189
 190 static void
 191 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
 192                          cyg_uint32 __len)
 193 {
 194     CYGARC_HAL_SAVE_GP();
 195
 196     while(__len-- > 0)
 197         cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 198
 199     CYGARC_HAL_RESTORE_GP();
 200 }
 201
 202 static void
 203 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
 204 {
 205     CYGARC_HAL_SAVE_GP();
 206
 207     while(__len-- > 0)
 208         *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 209
 210     CYGARC_HAL_RESTORE_GP();
 211 }
 212
 213 cyg_bool
 214 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
 215 {
 216     int delay_count;
 217     channel_data_t* chan = (channel_data_t*)__ch_data;
 218     cyg_bool res;
 219     CYGARC_HAL_SAVE_GP();
 220
 221     delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 222
 223     for(;;) {
 224         res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
 225         if (res || 0 == delay_count--)
 226             break;
 227
 228         CYGACC_CALL_IF_DELAY_US(100);
 229     }
 230
 231     CYGARC_HAL_RESTORE_GP();
 232     return res;
 233 }
 234
 235 static int
 236 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
 237 {
 238     static int irq_state = 0;
 239     channel_data_t* chan = (channel_data_t*)__ch_data;
 240     int ret = 0;
 241     CYGARC_HAL_SAVE_GP();
 242
 243     switch (__func) {
 244     case __COMMCTL_IRQ_ENABLE:
 245         irq_state = 1;
 246         HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
 247         HAL_INTERRUPT_UNMASK(chan->isr_vector_rx);
 248         break;
 249     case __COMMCTL_IRQ_DISABLE:
 250         ret = irq_state;
 251         irq_state = 0;
 252         HAL_INTERRUPT_MASK(chan->isr_vector_rx);
 253         break;
 254     case __COMMCTL_DBG_ISR_VECTOR:
 255         ret = chan->isr_vector_rx;
 256         break;
 257     case __COMMCTL_SET_TIMEOUT:
 258     {
 259         va_list ap;
 260
 261         va_start(ap, __func);
 262
 263         ret = chan->msec_timeout;
 264         chan->msec_timeout = va_arg(ap, cyg_uint32);
 265
 266         va_end(ap);
 267     }
 268     default:
 269         break;
 270     }
 271     CYGARC_HAL_RESTORE_GP();
 272     return ret;
 273 }
 274
 275 static int
 276 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
 277                        CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
 278 {
 279     int res = 0;
 280     channel_data_t* chan = (channel_data_t*)__ch_data;
 281     cyg_uint32 c;
 282     cyg_uint8 ch;
 283     cyg_uint32 stat;
 284     CYGARC_HAL_SAVE_GP();
 285
 286     *__ctrlc = 0;
 287     HAL_READ_UINT32(chan->base+E7T_UART_STAT, stat);
 288     if ( (stat & E7T_UART_STAT_RDR) != 0 ) {
 289
 290         HAL_READ_UINT32(chan->base+E7T_UART_RXBUF, c);
 291         ch = (cyg_uint8)(c & 0xff);
 292         if( cyg_hal_is_break( &ch , 1 ) )
 293             *__ctrlc = 1;
 294
 295         res = CYG_ISR_HANDLED;
 296     }
 297
 298     HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
 299
 300     CYGARC_HAL_RESTORE_GP();
 301     return res;
 302 }
 303
 304 static channel_data_t e7t_ser_channels[2] = {
 305     { (cyg_uint8*)E7T_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART0_RX, CYGNUM_HAL_INTERRUPT_UART0_TX },
 306     { (cyg_uint8*)E7T_UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1_RX, CYGNUM_HAL_INTERRUPT_UART1_TX }
 307 };
 308
 309 static void
 310 cyg_hal_plf_serial_init(void)
 311 {
 312     hal_virtual_comm_table_t* comm;
 313     int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 314
 315     // Init channels
 316     cyg_hal_plf_serial_init_channel(&e7t_ser_channels[0]);
 317     cyg_hal_plf_serial_init_channel(&e7t_ser_channels[1]);
 318
 319     // Setup procs in the vector table
 320
 321     // Set channel 0
 322     CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
 323     comm = CYGACC_CALL_IF_CONSOLE_PROCS();
 324     CYGACC_COMM_IF_CH_DATA_SET(*comm, &e7t_ser_channels[0]);
 325     CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
 326     CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
 327     CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
 328     CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
 329     CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
 330     CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
 331     CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 332
 333     // Set channel 1
 334     CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
 335     comm = CYGACC_CALL_IF_CONSOLE_PROCS();
 336     CYGACC_COMM_IF_CH_DATA_SET(*comm, &e7t_ser_channels[1]);
 337     CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
 338     CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
 339     CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
 340     CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
 341     CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
 342     CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
 343     CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 344
 345     // Restore original console
 346     CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
 347 }
 348
 349 void
 350 cyg_hal_plf_comms_init(void)
 351 {
 352     static int initialized = 0;
 353
 354     if (initialized)
 355         return;
 356
 357     initialized = 1;
 358
 359     cyg_hal_plf_serial_init();
 360 }
 361
 362 //-----------------------------------------------------------------------------
 363 // LED
 364 void
 365 hal_diag_led(int mask)
 366 {
 367     cyg_uint32 l;
 368
 369     HAL_READ_UINT32(E7T_IOPDATA, l);
 370     l &= ~0x000000f0;
 371     l |= (mask & 0xf) << 4;
 372     HAL_WRITE_UINT32(E7T_IOPDATA, l);
 373 }
 374
 375 //-----------------------------------------------------------------------------
 376 // End of hal_diag.c