packages/hal/arm/ebsa285/v2_0/include/hal_platform_ints.h

   1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
   2 #define CYGONCE_HAL_PLATFORM_INTS_H
   3 //==========================================================================
   4 //
   5 //      hal_platform_ints.h
   6 //
   7 //      HAL Interrupt and clock support
   8 //
   9 //==========================================================================
  10 //####ECOSGPLCOPYRIGHTBEGIN####
  11 // -------------------------------------------
  12 // This file is part of eCos, the Embedded Configurable Operating System.
  13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  14 //
  15 // eCos is free software; you can redistribute it and/or modify it under
  16 // the terms of the GNU General Public License as published by the Free
  17 // Software Foundation; either version 2 or (at your option) any later version.
  18 //
  19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  22 // for more details.
  23 //
  24 // You should have received a copy of the GNU General Public License along
  25 // with eCos; if not, write to the Free Software Foundation, Inc.,
  26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  27 //
  28 // As a special exception, if other files instantiate templates or use macros
  29 // or inline functions from this file, or you compile this file and link it
  30 // with other works to produce a work based on this file, this file does not
  31 // by itself cause the resulting work to be covered by the GNU General Public
  32 // License. However the source code for this file must still be made available
  33 // in accordance with section (3) of the GNU General Public License.
  34 //
  35 // This exception does not invalidate any other reasons why a work based on
  36 // this file might be covered by the GNU General Public License.
  37 //
  38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  39 // at http://sources.redhat.com/ecos/ecos-license/
  40 // -------------------------------------------
  41 //####ECOSGPLCOPYRIGHTEND####
  42 //==========================================================================
  43 //#####DESCRIPTIONBEGIN####
  44 //
  45 // Author(s):    hmt
  46 // Contributors: hmt
  47 // Date:         1999-04-21
  48 // Purpose:      Define Interrupt support
  49 // Description:  The interrupt details for the EBSA285 are defined here.
  50 // Usage:
  51 //               #include <cyg/hal/hal_platform_ints.h>
  52 //               ...
  53 //
  54 //
  55 //####DESCRIPTIONEND####
  56 //
  57 //==========================================================================
  58
  59 #define CYGNUM_HAL_INTERRUPT_reserved0                   0
  60 #define CYGNUM_HAL_INTERRUPT_SOFT_IRQ                    1
  61 #define CYGNUM_HAL_INTERRUPT_SERIAL_RX                   2
  62 #define CYGNUM_HAL_INTERRUPT_SERIAL_TX                   3
  63 #define CYGNUM_HAL_INTERRUPT_TIMER_1                     4
  64 #define CYGNUM_HAL_INTERRUPT_TIMER_2                     5
  65 #define CYGNUM_HAL_INTERRUPT_TIMER_3                     6
  66 #define CYGNUM_HAL_INTERRUPT_TIMER_4                     7
  67 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_0                    8
  68 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_1                    9
  69 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_2                    10
  70 #define CYGNUM_HAL_INTERRUPT_IRQ_IN_3                    11
  71 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_0                   12
  72 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_1                   13
  73 #define CYGNUM_HAL_INTERRUPT_XBUS_CS_2                   14
  74 #define CYGNUM_HAL_INTERRUPT_DOORBELL                    15
  75 #define CYGNUM_HAL_INTERRUPT_DMA_1                       16
  76 #define CYGNUM_HAL_INTERRUPT_DMA_2                       17
  77 #define CYGNUM_HAL_INTERRUPT_PCI_IRQ                     18
  78 #define CYGNUM_HAL_INTERRUPT_PMCSR                       19
  79 #define CYGNUM_HAL_INTERRUPT_reserved20                  20
  80 #define CYGNUM_HAL_INTERRUPT_reserved21                  21
  81 #define CYGNUM_HAL_INTERRUPT_BIST                        22
  82 #define CYGNUM_HAL_INTERRUPT_SERR                        23
  83 #define CYGNUM_HAL_INTERRUPT_SDRAM_PARITY                24
  84 #define CYGNUM_HAL_INTERRUPT_I2O_POST                    25
  85 #define CYGNUM_HAL_INTERRUPT_reserved26                  26
  86 #define CYGNUM_HAL_INTERRUPT_DISCARD_TIMER               27
  87 #define CYGNUM_HAL_INTERRUPT_PCI_DATA_PARITY             28
  88 #define CYGNUM_HAL_INTERRUPT_PCI_MASTER_ABORT            29
  89 #define CYGNUM_HAL_INTERRUPT_PCI_TARGET_ABORT            30
  90 #define CYGNUM_HAL_INTERRUPT_PCI_PARITY_ERROR            31
  91
  92 #define CYGNUM_HAL_ISR_MIN               0
  93 #define CYGNUM_HAL_ISR_MAX              31
  94
  95 #define CYGNUM_HAL_ISR_COUNT            (CYGNUM_HAL_ISR_MAX+1)
  96
  97 // The vector used by the Real time clock
  98 #define CYGNUM_HAL_INTERRUPT_RTC        CYGNUM_HAL_INTERRUPT_TIMER_3
  99
 100
 101 //----------------------------------------------------------------------------
 102 // Reset.
 103 #include <cyg/hal/hal_ebsa285.h>        // registers
 104 #include <cyg/hal/hal_io.h>             // IO macros
 105
 106 #define HAL_PLATFORM_RESET()                                               \
 107     CYG_MACRO_START                                                        \
 108     cyg_uint32 ctrl;                                                       \
 109                                                                            \
 110     /* If watchdog is already enabled, writing to timer4 has no effect. */ \
 111     /* But by disabling interupts and just hanging in the loop below    */ \
 112     /* the timer might run out eventually (not guaranteed).             */ \
 113     HAL_DISABLE_INTERRUPTS(ctrl);                                          \
 114                                                                            \
 115     /* Set timer4 (must be done before enabling watchdog) */               \
 116     HAL_WRITE_UINT32(SA110_TIMER4_LOAD, 2);                                \
 117     HAL_WRITE_UINT32(SA110_TIMER4_CONTROL, SA110_TIMER_CONTROL_ENABLE);    \
 118                                                                            \
 119     /* Enable watchdog */                                                  \
 120     HAL_READ_UINT32(SA110_CONTROL, ctrl);                                  \
 121     ctrl |= SA110_CONTROL_WATCHDOG;                                        \
 122     HAL_WRITE_UINT32(SA110_CONTROL, ctrl);                                 \
 123                                                                            \
 124     for(;;); /* wait for it */                                             \
 125     CYG_MACRO_END
 126
 127 #define HAL_PLATFORM_RESET_ENTRY 0x41000000
 128
 129 #endif // CYGONCE_HAL_PLATFORM_INTS_H