1 #ifndef CYGONCE_HAL_VAR_IO_H
2 #define CYGONCE_HAL_VAR_IO_H
3 //=============================================================================
7 // Variant specific registers
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 2004 eCosCentric Limited
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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37 // -------------------------------------------
38 //####ECOSGPLCOPYRIGHTEND####
39 //=============================================================================
40 //#####DESCRIPTIONBEGIN####
42 // Author(s): Uwe Kindler
45 // Purpose: NXP LPC24xx variant specific registers
47 // Usage: #include <cyg/hal/var_io.h>
49 //####DESCRIPTIONEND####
51 //=============================================================================
53 #include <pkgconf/hal_arm_lpc24xx.h> // variant chip model selection.
54 #include <cyg/hal/plf_io.h>
56 //=============================================================================
58 #define CYGARC_HAL_LPC24XX_REG_WD_BASE 0xE0000000
60 // Registers are offsets from base of this subsystem
61 #define CYGARC_HAL_LPC24XX_REG_WDMOD 0x0000
62 #define CYGARC_HAL_LPC24XX_REG_WDMOD_WDEN (1<<0)
63 #define CYGARC_HAL_LPC24XX_REG_WDMOD_WDRESET (1<<1)
64 #define CYGARC_HAL_LPC24XX_REG_WDMOD_WDTOF (1<<2)
65 #define CYGARC_HAL_LPC24XX_REG_WDMOD_WDINT (1<<3)
66 #define CYGARC_HAL_LPC24XX_REG_WDTC 0x0004
67 #define CYGARC_HAL_LPC24XX_REG_WDFEED 0x0008
68 #define CYGARC_HAL_LPC24XX_REG_WDFEED_MAGIC1 0xAA
69 #define CYGARC_HAL_LPC24XX_REG_WDFEED_MAGIC2 0x55
70 #define CYGARC_HAL_LPC24XX_REG_WDTV 0x000C
73 //=============================================================================
76 #define CYGARC_HAL_LPC24XX_REG_TIMER0_BASE 0xE0004000
77 #define CYGARC_HAL_LPC24XX_REG_TIMER1_BASE 0xE0008000
78 #define CYGARC_HAL_LPC24XX_REG_TIMER2_BASE 0xE0070000
79 #define CYGARC_HAL_LPC24XX_REG_TIMER3_BASE 0xE0074000
81 // Registers are offsets from base for each timer
82 #define CYGARC_HAL_LPC24XX_REG_TxIR 0x0000
83 #define CYGARC_HAL_LPC24XX_REG_TxIR_MR0 (1<<0)
84 #define CYGARC_HAL_LPC24XX_REG_TxIR_MR1 (1<<1)
85 #define CYGARC_HAL_LPC24XX_REG_TxIR_MR2 (1<<2)
86 #define CYGARC_HAL_LPC24XX_REG_TxIR_MR3 (1<<3)
87 #define CYGARC_HAL_LPC24XX_REG_TxIR_CR0 (1<<4)
88 #define CYGARC_HAL_LPC24XX_REG_TxIR_CR1 (1<<5)
89 #define CYGARC_HAL_LPC24XX_REG_TxIR_CR2 (1<<6)
90 #define CYGARC_HAL_LPC24XX_REG_TxIR_CR3 (1<<7)
91 #define CYGARC_HAL_LPC24XX_REG_TxTCR 0x0004
92 #define CYGARC_HAL_LPC24XX_REG_TxTCR_CTR_ENABLE (1<<0)
93 #define CYGARC_HAL_LPC24XX_REG_TxTCR_CTR_RESET (1<<1)
94 #define CYGARC_HAL_LPC24XX_REG_TxTC 0x0008
95 #define CYGARC_HAL_LPC24XX_REG_TxPR 0x000C
96 #define CYGARC_HAL_LPC24XX_REG_TxPC 0x0010
97 #define CYGARC_HAL_LPC24XX_REG_TxMCR 0x0014
98 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_INT (1<<0)
99 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_RESET (1<<1)
100 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR0_STOP (1<<2)
101 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR1_INT (1<<3)
102 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR1_RESET (1<<4)
103 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR1_STOP (1<<5)
104 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR2_INT (1<<6)
105 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR2_RESET (1<<7)
106 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR2_STOP (1<<8)
107 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR3_INT (1<<9)
108 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR3_RESET (1<<10)
109 #define CYGARC_HAL_LPC24XX_REG_TxMCR_MR3_STOP (1<<11)
110 #define CYGARC_HAL_LPC24XX_REG_TxMR0 0x0018
111 #define CYGARC_HAL_LPC24XX_REG_TxMR1 0x001C
112 #define CYGARC_HAL_LPC24XX_REG_TxMR2 0x0020
113 #define CYGARC_HAL_LPC24XX_REG_TxMR3 0x0024
114 #define CYGARC_HAL_LPC24XX_REG_TxCCR 0x0028
115 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR0_RISE (1<<0)
116 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR0_FALL (1<<1)
117 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR0 (1<<2)
118 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR1_RISE (1<<3)
119 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR1_FALL (1<<4)
120 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR1 (1<<5)
121 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR2_RISE (1<<6)
122 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR2_FALL (1<<7)
123 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR2 (1<<8)
124 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR3_RISE (1<<9)
125 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR3_FALL (1<<10)
126 #define CYGARC_HAL_LPC24XX_REG_TxCCR_INT_CR3 (1<<11)
127 #define CYGARC_HAL_LPC24XX_REG_TxCR0 0x002C
128 #define CYGARC_HAL_LPC24XX_REG_TxCR1 0x0030
129 #define CYGARC_HAL_LPC24XX_REG_TxCR2 0x0034
130 #define CYGARC_HAL_LPC24XX_REG_TxCR3 0x0038
131 #define CYGARC_HAL_LPC24XX_REG_TxEMR 0x003C
132 #define CYGARC_HAL_LPC24XX_REG_TxEMR_EM0 (1<<0)
133 #define CYGARC_HAL_LPC24XX_REG_TxEMR_EM1 (1<<1)
134 #define CYGARC_HAL_LPC24XX_REG_TxEMR_EM2 (1<<2)
135 #define CYGARC_HAL_LPC24XX_REG_TxEMR_EM3 (1<<3)
137 //=============================================================================
140 #define CYGARC_HAL_LPC24XX_REG_UART0_BASE 0xE000C000
141 #define CYGARC_HAL_LPC24XX_REG_UART1_BASE 0xE0010000
142 #define CYGARC_HAL_LPC24XX_REG_UART2_BASE 0xE0078000
143 #define CYGARC_HAL_LPC24XX_REG_UART3_BASE 0xE007C000
145 // Registers are offsets from base for each UART
146 #define CYGARC_HAL_LPC24XX_REG_UxRBR 0x0000 // DLAB=0 read
147 #define CYGARC_HAL_LPC24XX_REG_UxTHR 0x0000 // DLAB=0 write
148 #define CYGARC_HAL_LPC24XX_REG_UxDLL 0x0000 // DLAB=1 r/w
149 #define CYGARC_HAL_LPC24XX_REG_UxIER 0x0004 // DLAB=0
150 #define CYGARC_HAL_LPC24XX_REG_UxIER_RXDATA_INT (1<<0)
151 #define CYGARC_HAL_LPC24XX_REG_UxIER_THRE_INT (1<<1)
152 #define CYGARC_HAL_LPC24XX_REG_UxIER_RXLS_INT (1<<2)
153 #define CYGARC_HAL_LPC24XX_REG_U1IER_RXMS_INT (1<<3) // U1 only
154 #define CYGARC_HAL_LPC24XX_REG_UxDLM 0x0004 // DLAB=1
156 #define CYGARC_HAL_LPC24XX_REG_UxIIR 0x0008 // read
157 #define CYGARC_HAL_LPC24XX_REG_UxIIR_IIR0 (1<<0)
158 #define CYGARC_HAL_LPC24XX_REG_UxIIR_IIR1 (1<<1)
159 #define CYGARC_HAL_LPC24XX_REG_UxIIR_IIR2 (1<<2)
160 #define CYGARC_HAL_LPC24XX_REG_UxIIR_IIR3 (1<<3)
161 #define CYGARC_HAL_LPC24XX_REG_UxIIR_FIFOS (0xB0)
163 #define CYGARC_HAL_LPC24XX_REG_UxFCR 0x0008 // write
164 #define CYGARC_HAL_LPC24XX_REG_UxFCR_FIFO_ENA (1<<0)
165 #define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_FIFO_RESET (1<<1)
166 #define CYGARC_HAL_LPC24XX_REG_UxFCR_TX_FIFO_RESET (1<<2)
167 #define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_TRIGGER_0 (0x00)
168 #define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_TRIGGER_1 (0x40)
169 #define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_TRIGGER_2 (0x80)
170 #define CYGARC_HAL_LPC24XX_REG_UxFCR_RX_TRIGGER_3 (0xB0)
172 #define CYGARC_HAL_LPC24XX_REG_UxLCR 0x000C
173 #define CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_5 (0x00)
174 #define CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_6 (0x01)
175 #define CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_7 (0x02)
176 #define CYGARC_HAL_LPC24XX_REG_UxLCR_WORD_LENGTH_8 (0x03)
177 #define CYGARC_HAL_LPC24XX_REG_UxLCR_STOP_1 (0x00)
178 #define CYGARC_HAL_LPC24XX_REG_UxLCR_STOP_2 (0x04)
179 #define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_ENA (0x08)
180 #define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_ODD (0x00)
181 #define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_EVEN (0x10)
182 #define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_ONE (0x20)
183 #define CYGARC_HAL_LPC24XX_REG_UxLCR_PARITY_ZERO (0x30)
184 #define CYGARC_HAL_LPC24XX_REG_UxLCR_BREAK_ENA (0x40)
185 #define CYGARC_HAL_LPC24XX_REG_UxLCR_DLAB (0x80)
188 // Modem Control Register is UART1 only
189 #define CYGARC_HAL_LPC24XX_REG_U1MCR 0x0010
190 #define CYGARC_HAL_LPC24XX_REG_U1MCR_DTR (1<<0)
191 #define CYGARC_HAL_LPC24XX_REG_U1MCR_RTS (1<<1)
192 #define CYGARC_HAL_LPC24XX_REG_U1MCR_LOOPBACK (1<<4)
194 #define CYGARC_HAL_LPC24XX_REG_UxLSR 0x0014
195 #define CYGARC_HAL_LPC24XX_REG_UxLSR_RDR (1<<0)
196 #define CYGARC_HAL_LPC24XX_REG_UxLSR_OE (1<<1)
197 #define CYGARC_HAL_LPC24XX_REG_UxLSR_PE (1<<2)
198 #define CYGARC_HAL_LPC24XX_REG_UxLSR_FE (1<<3)
199 #define CYGARC_HAL_LPC24XX_REG_UxLSR_BI (1<<4)
200 #define CYGARC_HAL_LPC24XX_REG_UxLSR_THRE (1<<5)
201 #define CYGARC_HAL_LPC24XX_REG_UxLSR_TEMT (1<<6)
202 #define CYGARC_HAL_LPC24XX_REG_UxLSR_RX_FIFO_ERR (1<<7)
204 // Modem Status Register is UART1 only
205 #define CYGARC_HAL_LPC24XX_REG_U1MSR 0x0018
206 #define CYGARC_HAL_LPC24XX_REG_U1MSR_DCTS (1<<0)
207 #define CYGARC_HAL_LPC24XX_REG_U1MSR_DDSR (1<<1)
208 #define CYGARC_HAL_LPC24XX_REG_U1MSR_RI_FALL (1<<2)
209 #define CYGARC_HAL_LPC24XX_REG_U1MSR_DDCD (1<<3)
210 #define CYGARC_HAL_LPC24XX_REG_U1MSR_CTS (1<<4)
211 #define CYGARC_HAL_LPC24XX_REG_U1MSR_DSR (1<<5)
212 #define CYGARC_HAL_LPC24XX_REG_U1MSR_RI (1<<6)
213 #define CYGARC_HAL_LPC24XX_REG_U1MSR_DCD (1<<7)
215 #define CYGARC_HAL_LPC24XX_REG_UxSCR 0x001C
216 #define CYGARC_HAL_LPC24XX_REG_UxACR 0x0020
217 #define CYGARC_HAL_LPC24XX_REG_U3ICR 0x0024
218 #define CYGARC_HAL_LPC24XX_REG_UxFDR 0x0028
219 #define CYCARC_HAL_LPC24XX_REG_UxTER 0x0030
222 //=============================================================================
223 // Pulse Width Modulator (PWM)
225 #define CYGARC_HAL_LPC24XX_REG_PWM0_BASE 0xE0014000
226 #define CYGARC_HAL_LPC24XX_REG_PWM1_BASE 0xE0018000
229 // Registers are offsets from base of this subsystem
230 #define CYGARC_HAL_LPC24XX_REG_PWMIR 0x0000
231 #define CYGARC_HAL_LPC24XX_REG_PWMIR_MR0_INT (1<<0)
232 #define CYGARC_HAL_LPC24XX_REG_PWMIR_MR1_INT (1<<1)
233 #define CYGARC_HAL_LPC24XX_REG_PWMIR_MR2_INT (1<<2)
234 #define CYGARC_HAL_LPC24XX_REG_PWMIR_MR3_INT (1<<3)
235 #define CYGARC_HAL_LPC24XX_REG_PWMIR_MR4_INT (1<<8)
236 #define CYGARC_HAL_LPC24XX_REG_PWMIR_MR5_INT (1<<9)
237 #define CYGARC_HAL_LPC24XX_REG_PWMIR_MR6_INT (1<<10)
238 #define CYGARC_HAL_LPC24XX_REG_PWMTCR 0x0004
239 #define CYGARC_HAL_LPC24XX_REG_PWMTCR_CTR_ENA (1<<0)
240 #define CYGARC_HAL_LPC24XX_REG_PWMTCR_CTR_RESET (1<<1)
241 #define CYGARC_HAL_LPC24XX_REG_PWMTCR_PWM_ENA (1<<3)
242 #define CYGARC_HAL_LPC24XX_REG_PWMTC 0x0008
243 #define CYGARC_HAL_LPC24XX_REG_PWMPR 0x000C
244 #define CYGARC_HAL_LPC24XX_REG_PWMPC 0x0010
245 #define CYGARC_HAL_LPC24XX_REG_PWMMCR 0x0014
246 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR0_INT (1<<0)
247 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR0_RESET (1<<1)
248 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR0_STOP (1<<2)
249 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR1_INT (1<<3)
250 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR1_RESET (1<<4)
251 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR1_STOP (1<<5)
252 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR2_INT (1<<6)
253 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR2_RESET (1<<7)
254 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR2_STOP (1<<8)
255 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR3_INT (1<<9)
256 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR3_RESET (1<<10)
257 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR3_STOP (1<<11)
258 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR4_INT (1<<12)
259 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR4_RESET (1<<13)
260 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR4_STOP (1<<14)
261 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR5_INT (1<<15)
262 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR5_RESET (1<<16)
263 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR5_STOP (1<<17)
264 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR6_INT (1<<18)
265 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR6_RESET (1<<19)
266 #define CYGARC_HAL_LPC24XX_REG_PWMMCR_MR6_STOP (1<<20)
267 #define CYGARC_HAL_LPC24XX_REG_PWMMR0 0x0018
268 #define CYGARC_HAL_LPC24XX_REG_PWMMR1 0x001C
269 #define CYGARC_HAL_LPC24XX_REG_PWMMR2 0x0020
270 #define CYGARC_HAL_LPC24XX_REG_PWMMR3 0x0024
271 #define CYGARC_HAL_LPC24XX_REG_PWMMR4 0x0040
272 #define CYGARC_HAL_LPC24XX_REG_PWMMR5 0x0044
273 #define CYGARC_HAL_LPC24XX_REG_PWMMR6 0x0048
274 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR 0x004C
275 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL1 (1<<1)
276 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL2 (1<<2)
277 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL3 (1<<3)
278 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL4 (1<<4)
279 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL5 (1<<5)
280 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_SEL6 (1<<6)
281 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA1 (1<<9)
282 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA2 (1<<10)
283 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA3 (1<<11)
284 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA4 (1<<12)
285 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA5 (1<<13)
286 #define CYGARC_HAL_LPC24XX_REG_PWMMPCR_ENA6 (1<<14)
287 #define CYGARC_HAL_LPC24XX_REG_PWMLER 0x0050
288 #define CYGARC_HAL_LPC24XX_REG_PWMLER_M0_ENA (1<<0)
289 #define CYGARC_HAL_LPC24XX_REG_PWMLER_M1_ENA (1<<1)
290 #define CYGARC_HAL_LPC24XX_REG_PWMLER_M2_ENA (1<<2)
291 #define CYGARC_HAL_LPC24XX_REG_PWMLER_M3_ENA (1<<3)
292 #define CYGARC_HAL_LPC24XX_REG_PWMLER_M4_ENA (1<<4)
293 #define CYGARC_HAL_LPC24XX_REG_PWMLER_M5_ENA (1<<5)
294 #define CYGARC_HAL_LPC24XX_REG_PWMLER_M6_ENA (1<<6)
296 #define CYGARC_HAL_LPC24XX_REG_PWMCTCR 0x0070
298 //=============================================================================
301 #define CYGARC_HAL_LPC24XX_REG_I2C0_BASE 0xE001C000
302 #define CYGARC_HAL_LPC24XX_REG_I2C1_BASE 0xE005C000
303 #define CYGARC_HAL_LPC24XX_REG_I2C2_BASE 0xE0080000
306 // Registers are offsets from base of this subsystem
307 #define CYGARC_HAL_LPC24XX_REG_I2CONSET 0x0000
308 #define CYGARC_HAL_LPC24XX_REG_I2CONSET_AA (1<<2)
309 #define CYGARC_HAL_LPC24XX_REG_I2CONSET_SI (1<<3)
310 #define CYGARC_HAL_LPC24XX_REG_I2CONSET_STO (1<<4)
311 #define CYGARC_HAL_LPC24XX_REG_I2CONSET_STA (1<<5)
312 #define CYGARC_HAL_LPC24XX_REG_I2CONSET_I2EN (1<<6)
313 #define CYGARC_HAL_LPC24XX_REG_I2STAT 0x0004
314 #define CYGARC_HAL_LPC24XX_REG_I2STAT_SHIFT 3
315 #define CYGARC_HAL_LPC24XX_REG_I2DAT 0x0008
316 #define CYGARC_HAL_LPC24XX_REG_I2ADR 0x000C
317 #define CYGARC_HAL_LPC24XX_REG_I2ADR_GC (1<<0)
318 #define CYGARC_HAL_LPC24XX_REG_I2SCLH 0x0010
319 #define CYGARC_HAL_LPC24XX_REG_I2SCLL 0x0014
320 #define CYGARC_HAL_LPC24XX_REG_I2CONCLR 0x0018
321 #define CYGARC_HAL_LPC24XX_REG_I2CONCLR_AAC (1<<2)
322 #define CYGARC_HAL_LPC24XX_REG_I2CONCLR_SIC (1<<3)
323 #define CYGARC_HAL_LPC24XX_REG_I2CONCLR_STAC (1<<5)
324 #define CYGARC_HAL_LPC24XX_REG_I2CONCLR_I2ENC (1<<6)
326 //=============================================================================
329 #define CYGARC_HAL_LPC24XX_REG_SPI0_BASE 0xE0020000
330 #define CYGARC_HAL_LPC24XX_REG_SPI1_BASE 0xE0030000
332 // Registers are offsets from base of this subsystem
333 #define CYGARC_HAL_LPC24XX_REG_SPI_SPCR 0x0000
334 #define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_CPHA (1<<3)
335 #define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_CPOL (1<<4)
336 #define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_MSTR (1<<5)
337 #define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_LSBF (1<<6)
338 #define CYGARC_HAL_LPC24XX_REG_SPI_SPCR_SPIE (1<<7)
339 #define CYGARC_HAL_LPC24XX_REG_SPI_SPSR 0x0004
340 #define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_ABRT (1<<3)
341 #define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_MODF (1<<4)
342 #define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_ROVR (1<<5)
343 #define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_WCOL (1<<6)
344 #define CYGARC_HAL_LPC24XX_REG_SPI_SPSR_SPIF (1<<7)
345 #define CYGARC_HAL_LPC24XX_REG_SPI_SPDR 0x0008
346 #define CYGARC_HAL_LPC24XX_REG_SPI_SPCCR 0x000C
347 #define CYGARC_HAL_LPC24XX_REG_SPI_SPINT 0x001C
350 //=============================================================================
353 #define CYGARC_HAL_LPC24XX_REG_RTC_BASE 0xE0024000
355 // Registers are offsets from base of this subsystem
357 #define CYGARC_HAL_LPC24XX_REG_RTC_ILR 0x0000
358 #define CYGARC_HAL_LPC24XX_REG_RTC_ILR_CIF (1<<0)
359 #define CYGARC_HAL_LPC24XX_REG_RTC_ILR_ALF (1<<1)
360 #define CYGARC_HAL_LPC24XX_REG_RTC_CTC 0x0004
361 #define CYGARC_HAL_LPC24XX_REG_RTC_CCR 0x0008
362 #define CYGARC_HAL_LPC24XX_REG_RTC_CCR_CLKEN (1<<0)
363 #define CYGARC_HAL_LPC24XX_REG_RTC_CCR_CTCRST (1<<1)
364 #define CYGARC_HAL_LPC24XX_REG_RTC_CIIR 0x000C
365 #define CYGARC_HAL_LPC24XX_REG_RTC_AMR 0x0010
366 #define CYGARC_HAL_LPC24XX_REG_RTC_CTIME0 0x0014
367 #define CYGARC_HAL_LPC24XX_REG_RTC_CTIME1 0x0018
368 #define CYGARC_HAL_LPC24XX_REG_RTC_CTIME2 0x001C
369 #define CYGARC_HAL_LPC24XX_REG_RTC_SEC 0x0020
370 #define CYGARC_HAL_LPC24XX_REG_RTC_MIN 0x0024
371 #define CYGARC_HAL_LPC24XX_REG_RTC_HOUR 0x0028
372 #define CYGARC_HAL_LPC24XX_REG_RTC_DOM 0x002C
373 #define CYGARC_HAL_LPC24XX_REG_RTC_DOW 0x0030
374 #define CYGARC_HAL_LPC24XX_REG_RTC_DOY 0x0034
375 #define CYGARC_HAL_LPC24XX_REG_RTC_MONTH 0x0038
376 #define CYGARC_HAL_LPC24XX_REG_RTC_YEAR 0x003C
377 #define CYGARC_HAL_LPC24XX_REG_RTC_ALSEC 0x0060
378 #define CYGARC_HAL_LPC24XX_REG_RTC_ALMIN 0x0064
379 #define CYGARC_HAL_LPC24XX_REG_RTC_ALHOUR 0x0068
380 #define CYGARC_HAL_LPC24XX_REG_RTC_ALDOM 0x006C
381 #define CYGARC_HAL_LPC24XX_REG_RTC_ALDOW 0x0070
382 #define CYGARC_HAL_LPC24XX_REG_RTC_ALDOY 0x0074
383 #define CYGARC_HAL_LPC24XX_REG_RTC_ALMON 0x0078
384 #define CYGARC_HAL_LPC24XX_REG_RTC_ALYEAR 0x007C
385 #define CYGARC_HAL_LPC24XX_REG_RTC_PREINT 0x0080
386 #define CYGARC_HAL_LPC24XX_REG_RTC_PREFRAC 0x0084
388 //=============================================================================
391 #define CYGARC_HAL_LPC24XX_REG_IO_BASE 0xE0028000
392 #define CYGARC_HAL_LPC24XX_REG_FIO_BASE 0x3FFFC000
394 // Registers are offsets from base of this subsystem
395 #define CYGARC_HAL_LPC24XX_REG_IO0PIN 0x000
396 #define CYGARC_HAL_LPC24XX_REG_IO0SET 0x004
397 #define CYGARC_HAL_LPC24XX_REG_IO0DIR 0x008
398 #define CYGARC_HAL_LPC24XX_REG_IO0CLR 0x00C
400 #define CYGARC_HAL_LPC24XX_REG_IO1PIN 0x010
401 #define CYGARC_HAL_LPC24XX_REG_IO1SET 0x014
402 #define CYGARC_HAL_LPC24XX_REG_IO1DIR 0x018
403 #define CYGARC_HAL_LPC24XX_REG_IO1CLR 0x01C
405 #define CYGARC_HAL_LPC24XX_REG_FIO0DIR 0x0000
406 #define CYGARC_HAL_LPC24XX_REG_FIO1DIR 0x0020
407 #define CYGARC_HAL_LPC24XX_REG_FIO2DIR 0x0040
408 #define CYGARC_HAL_LPC24XX_REG_FIO3DIR 0x0050
409 #define CYGARC_HAL_LPC24XX_REG_FIO4DIR 0x0080
411 #define CYGARC_HAL_LPC24XX_REG_FIO0SET 0x0018
412 #define CYGARC_HAL_LPC24XX_REG_FIO1SET 0x0038
413 #define CYGARC_HAL_LPC24XX_REG_FIO2SET 0x0058
414 #define CYGARC_HAL_LPC24XX_REG_FIO3SET 0x0078
415 #define CYGARC_HAL_LPC24XX_REG_FIO4SET 0x0098
417 #define CYGARC_HAL_LPC24XX_REG_FIO0CLR 0x001C
418 #define CYGARC_HAL_LPC24XX_REG_FIO1CLR 0x003C
419 #define CYGARC_HAL_LPC24XX_REG_FIO2CLR 0x005C
420 #define CYGARC_HAL_LPC24XX_REG_FIO3CLR 0x007C
421 #define CYGARC_HAL_LPC24XX_REG_FIO4CLR 0x009C
423 #define CYGARC_HAL_LPC24XX_REG_FIO0PIN 0x0014
424 #define CYGARC_HAL_LPC24XX_REG_FIO1PIN 0x0034
425 #define CYGARC_HAL_LPC24XX_REG_FIO2PIN 0x0054
426 #define CYGARC_HAL_LPC24XX_REG_FIO3PIN 0x0074
427 #define CYGARC_HAL_LPC24XX_REG_FIO4PIN 0x0094
429 #define CYGARC_HAL_LPC24XX_REG_FIO0MASK 0x0010
430 #define CYGARC_HAL_LPC24XX_REG_FIO1MASK 0x0030
431 #define CYGARC_HAL_LPC24XX_REG_FIO2MASK 0x0050
432 #define CYGARC_HAL_LPC24XX_REG_FIO3MASK 0x0070
433 #define CYGARC_HAL_LPC24XX_REG_FIO4MASK 0x0090
437 //=============================================================================
438 // Pin Connect Block (PIN)
440 #define CYGARC_HAL_LPC24XX_REG_PIN_BASE 0xE002C000
442 #define CYGARC_HAL_LPC24XX_REG_PINSEL0 0x000
443 #define CYGARC_HAL_LPC24XX_REG_PINSEL1 0x004
444 #define CYGARC_HAL_LPC24XX_REG_PINSEL2 0x008
445 #define CYGARC_HAL_LPC24XX_REG_PINSEL3 0x00C
446 #define CYGARC_HAL_LPC24XX_REG_PINSEL4 0x010
447 #define CYGARC_HAL_LPC24XX_REG_PINSEL5 0x014
448 #define CYGARC_HAL_LPC24XX_REG_PINSEL6 0x018
449 #define CYGARC_HAL_LPC24XX_REG_PINSEL7 0x01C
450 #define CYGARC_HAL_LPC24XX_REG_PINSEL8 0x020
451 #define CYGARC_HAL_LPC24XX_REG_PINSEL9 0x024
452 #define CYGARC_HAL_LPC24XX_REG_PINSEL10 0x028
453 #define CYGARC_HAL_LPC24XX_REG_PINSEL11 0x02C
455 #define CYGARC_HAL_LPC24XX_REG_PINMODE0 0x040
456 #define CYGARC_HAL_LPC24XX_REG_PINMODE1 0x044
457 #define CYGARC_HAL_LPC24XX_REG_PINMODE2 0x048
458 #define CYGARC_HAL_LPC24XX_REG_PINMODE3 0x04C
459 #define CYGARC_HAL_LPC24XX_REG_PINMODE4 0x050
460 #define CYGARC_HAL_LPC24XX_REG_PINMODE5 0x054
461 #define CYGARC_HAL_LPC24XX_REG_PINMODE6 0x058
462 #define CYGARC_HAL_LPC24XX_REG_PINMODE7 0x05C
463 #define CYGARC_HAL_LPC24XX_REG_PINMODE8 0x060
464 #define CYGARC_HAL_LPC24XX_REG_PINMODE9 0x064
466 #define CYGARC_HAL_LPC24XX_SET_PIN_FUN(_regval_, _pin_, _func_) \
467 (_regval_) = ((_regval_) & ~(0x3 << ((_pin_) << 1))) | ((_func_) << ((_pin_) << 1))
470 //=============================================================================
471 // SSP - Synchronous Serial Port
472 #define CYGARC_HAL_LPC24XX_REG_SSP0_BASE 0xE0068000
473 #define CYGARC_HAL_LPC24XX_REG_SSP1_BASE 0xE0030000
475 #define CYGARC_HAL_LPC24XX_REG_SSP_CR0 0x0000
476 #define CYGARC_HAL_LPC24XX_REG_SSP_CR1 0x0004
477 #define CYGARC_HAL_LPC24XX_REG_SSP_DR 0x0008
478 #define CYGARC_HAL_LPC24XX_REG_SSP_SR 0x000C
479 #define CYGARC_HAL_LPC24XX_REG_SSP_CPSR 0x0010
480 #define CYGARC_HAL_LPC24XX_REG_SSP_IMSC 0x0014
481 #define CYGARC_HAL_LPC24XX_REG_SSP_RIS 0x0018
482 #define CYGARC_HAL_LPC24XX_REG_SSP_MIS 0x001C
483 #define CYGARC_HAL_LPC24XX_REG_SSP_ICR 0x0020
484 #define CYGARC_HAL_LPC24XX_REG_SSP_DMACR 0x0024
487 //=============================================================================
490 #define CYGARC_HAL_LPC24XX_REG_AD_BASE 0xE0034000
492 // Registers are offsets from base of this subsystem
493 #define CYGARC_HAL_LPC24XX_REG_ADCR 0x0000
494 #define CYGARC_HAL_LPC24XX_REG_ADCR_BURST (1<<16)
495 #define CYGARC_HAL_LPC24XX_REG_ADCR_PDN (1<<21)
496 #define CYGARC_HAL_LPC24XX_REG_ADCR_EDGE (1<<27)
497 #define CYGARC_HAL_LPC24XX_REG_ADGDR 0x0004
498 #define CYGARC_HAL_LPC24XX_REG_ADSTAT 0x0030
499 #define CYGARC_HAL_LPC24XX_REG_ADINTEN 0x000C
500 #define CYGARC_HAL_LPC24XX_REG_ADDR0 0x0010
501 #define CYGARC_HAL_LPC24XX_REG_ADDR1 0x0018
502 #define CYGARC_HAL_LPC24XX_REG_ADDR2 0x0018
503 #define CYGARC_HAL_LPC24XX_REG_ADDR3 0x001C
504 #define CYGARC_HAL_LPC24XX_REG_ADDR4 0x0020
505 #define CYGARC_HAL_LPC24XX_REG_ADDR5 0x0024
506 #define CYGARC_HAL_LPC24XX_REG_ADDR6 0x0028
507 #define CYGARC_HAL_LPC24XX_REG_ADDR7 0x002C
510 //=============================================================================
512 #define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_RAM 0xE0038000
513 #define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_BASE 0xE003C000
514 #define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_AFMR 0x0000
515 #define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_SFF_sa 0x0004
516 #define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_SFF_GRP_sa 0x0008
517 #define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_EFF_sa 0x000C
518 #define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_EFF_GRP_sa 0x0010
519 #define CYGARC_HAL_LPC24XX_REG_CAN_ACCFILT_END 0x0014
521 #define CYGARC_HAL_LPC24XX_REG_CAN_COMMON_BASE 0xE0040000
522 #define CYGARC_HAL_LPC24XX_REG_CAN_TxSR 0x0000
523 #define CYGARC_HAL_LPC24XX_REG_CAN_RxSR 0x0004
524 #define CYGARC_HAL_LPC24XX_REG_CAN_MSR 0x0008
526 #define CYGARC_HAL_LPC24XX_REG_CAN0_BASE 0xE0044000
527 #define CYGARC_HAL_LPC24XX_REG_CAN1_BASE 0xE0048000
528 #define CYCARC_HAL_LPC24XX_REG_CANx_MOD 0x0000
529 #define CYCARC_HAL_LPC24XX_REG_CANx_CMR 0x0000
530 #define CYCARC_HAL_LPC24XX_REG_CANx_GSR 0x0000
531 #define CYCARC_HAL_LPC24XX_REG_CANx_ICR 0x0000
532 #define CYCARC_HAL_LPC24XX_REG_CANx_IER 0x0000
533 #define CYCARC_HAL_LPC24XX_REG_CANx_BTR 0x0000
534 #define CYCARC_HAL_LPC24XX_REG_CANx_EWL 0x0000
535 #define CYCARC_HAL_LPC24XX_REG_CANx_SR 0x0000
536 #define CYCARC_HAL_LPC24XX_REG_CANx_RFS 0x0000
537 #define CYCARC_HAL_LPC24XX_REG_CANx_RID 0x0000
538 #define CYCARC_HAL_LPC24XX_REG_CANx_RDA 0x0000
539 #define CYCARC_HAL_LPC24XX_REG_CANx_RDB 0x0000
540 #define CYCARC_HAL_LPC24XX_REG_CANx_RFI1 0x0000
541 #define CYCARC_HAL_LPC24XX_REG_CANx_TID1 0x0000
542 #define CYCARC_HAL_LPC24XX_REG_CANx_TDA1 0x0000
543 #define CYCARC_HAL_LPC24XX_REG_CANx_TDB1 0x0000
544 #define CYCARC_HAL_LPC24XX_REG_CANx_RFI2 0x0000
545 #define CYCARC_HAL_LPC24XX_REG_CANx_TID2 0x0000
546 #define CYCARC_HAL_LPC24XX_REG_CANx_TDA2 0x0000
547 #define CYCARC_HAL_LPC24XX_REG_CANx_TDB2 0x0000
548 #define CYCARC_HAL_LPC24XX_REG_CANx_RFI3 0x0000
549 #define CYCARC_HAL_LPC24XX_REG_CANx_TID3 0x0000
550 #define CYCARC_HAL_LPC24XX_REG_CANx_TDA3 0x0000
551 #define CYCARC_HAL_LPC24XX_REG_CANx_TDB3 0x0000
554 //=============================================================================
556 #define CYGARC_HAL_LPC24XX_REG_DAC_BASE 0xE006C000
559 //=============================================================================
561 #define CYGARC_HAL_LPC24XX_REG_BATTERY_RAM 0xE0084000
564 //=============================================================================
566 #define CYGARC_HAL_LPC24XX_REG_I2S_BASE 0xE0088000
568 #define CYGARC_HAL_LPC24XX_REG_I2S_DAO 0x0000
569 #define CYGARC_HAL_LPC24XX_REG_I2S_DAI 0x0004
570 #define CYGARC_HAL_LPC24XX_REG_I2S_TXFIFO 0x0008
571 #define CYGARC_HAL_LPC24XX_REG_I2S_RXFIFO 0x000C
572 #define CYGARC_HAL_LPC24XX_REG_I2S_STATE 0x0010
573 #define CYGARC_HAL_LPC24XX_REG_I2S_DMA1 0x0014
574 #define CYGARC_HAL_LPC24XX_REG_I2S_DMA2 0x0018
575 #define CYGARC_HAL_LPC24XX_REG_I2S_IRQ 0x001C
576 #define CYGARC_HAL_LPC24XX_REG_I2S_TXRATE 0x0020
577 #define CYGARC_HAL_LPC24XX_REG_I2S_RXRATE 0x0024
581 //=============================================================================
582 // SD/MMC Card Interface
583 #define CYGARC_HAL_LPC24XX_REG_SD_MMC_BASE 0xE008C000
586 //=============================================================================
587 // System Control Block
589 #define CYGARC_HAL_LPC24XX_REG_SCB_BASE 0xE01FC000
591 // Registers are offsets from base of this subsystem
593 // Memory accelerator module
594 #define CYGARC_HAL_LPC24XX_REG_MAMCR 0x0000
595 #define CYGARC_HAL_LPC24XX_REG_MAMCR_DISABLED 0x00
596 #define CYGARC_HAL_LPC24XX_REG_MAMCR_PARTIAL 0x01
597 #define CYGARC_HAL_LPC24XX_REG_MAMCR_FULL 0x02
598 #define CYGARC_HAL_LPC24XX_REG_MAMTIM 0x0004
600 // Memory mapping control
601 #define CYGARC_HAL_LPC24XX_REG_MEMMAP 0x0040
604 #define CYGARC_HAL_LPC24XX_REG_PLLCON 0x0080
605 #define CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE (1<<0)
606 #define CYGARC_HAL_LPC24XX_REG_PLLCON_PLLC (1<<1)
607 #define CYGARC_HAL_LPC24XX_REG_PLLCFG 0x0084
608 #define CYGARC_HAL_LPC24XX_REG_PLLSTAT 0x0088
609 #define CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLE (1<<24)
610 #define CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC (1<<25)
611 #define CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLOCK (1<<26)
612 #define CYGARC_HAL_LPC24XX_REG_PLLFEED 0x008C
615 #define CYGARC_HAL_LPC24XX_REG_PCON 0x00C0
616 #define CYGARC_HAL_LPC24XX_REG_PCON_IDL (1<<0)
617 #define CYGARC_HAL_LPC24XX_REG_PCON_PD (1<<1)
618 #define CYGARC_HAL_LPC24XX_REG_PCONP 0x00C4
619 #define CYGARC_HAL_LPC24XX_REG_PCONP_TIM0 (1<<1)
620 #define CYGARC_HAL_LPC24XX_REG_PCONP_TIM1 (1<<2)
621 #define CYGARC_HAL_LPC24XX_REG_PCONP_URT0 (1<<3)
622 #define CYGARC_HAL_LPC24XX_REG_PCONP_URT1 (1<<4)
623 #define CYGARC_HAL_LPC24XX_REG_PCONP_PWM0 (1<<5)
624 #define CYGARC_HAL_LPC24XX_REG_PCONP_PWM1 (1<<6)
625 #define CYGARC_HAL_LPC24XX_REG_PCONP_I2C0 (1<<7)
626 #define CYGARC_HAL_LPC24XX_REG_PCONP_SPI (1<<8)
627 #define CYGARC_HAL_LPC24XX_REG_PCONP_RTC (1<<9)
628 #define CYGARC_HAL_LPC24XX_REG_PCONP_SSP1 (1<<10)
629 #define CYGARC_HAL_LPC24XX_REG_PCONP_EMC (1<<11)
630 #define CYGARC_HAL_LPC24XX_REG_PCONP_AD (1<<12)
631 #define CYGARC_HAL_LPC24XX_REG_PCONP_CAN1 (1<<13)
632 #define CYGARC_HAL_LPC24XX_REG_PCONP_CAN2 (1<<14)
633 #define CYGARC_HAL_LPC24XX_REG_PCONP_I2C1 (1<<19)
634 #define CYGARC_HAL_LPC24XX_REG_PCONP_LCD (1<<20)
635 #define CYGARC_HAL_LPC24XX_REG_PCONP_SSP0 (1<<21)
636 #define CYGARC_HAL_LPC24XX_REG_PCONP_TIM2 (1<<22)
637 #define CYGARC_HAL_LPC24XX_REG_PCONP_TIM3 (1<<23)
638 #define CYGARC_HAL_LPC24XX_REG_PCONP_URT2 (1<<24)
639 #define CYGARC_HAL_LPC24XX_REG_PCONP_URT3 (1<<25)
640 #define CYGARC_HAL_LPC24XX_REG_PCONP_I2C2 (1<<26)
641 #define CYGARC_HAL_LPC24XX_REG_PCONP_I2S (1<<27)
642 #define CYGARC_HAL_LPC24XX_REG_PCONP_SD (1<<28)
643 #define CYGARC_HAL_LPC24XX_REG_PCONP_DMA (1<<29)
644 #define CYGARC_HAL_LPC24XX_REG_PCONP_ENET (1<<30)
645 #define CYGARC_HAL_LPC24XX_REG_PCONP_USB (1<<31)
647 // External interrupt inputs
648 #define CYGARC_HAL_LPC24XX_REG_EXTINT 0x0140
649 #define CYGARC_HAL_LPC24XX_REG_EXTMODE 0x0148
650 #define CYGARC_HAL_LPC24XX_REG_EXTPOLAR 0x014C
652 #define CYGARC_HAL_LPC24XX_REG_EXTxxx_INT0 (1<<0)
653 #define CYGARC_HAL_LPC24XX_REG_EXTxxx_INT1 (1<<1)
654 #define CYGARC_HAL_LPC24XX_REG_EXTxxx_INT2 (1<<2)
655 #define CYGARC_HAL_LPC24XX_REG_EXTxxx_INT3 (1<<3)
657 // Reset source identification register
658 #define CYGARC_HAL_LPC24XX_REG_RSID 0x0180
659 #define CYGARC_HAL_LPC24XX_REG_RSID_POR (1<<0)
660 #define CYGARC_HAL_LPC24XX_REG_RSID_EXTR (1<<1)
661 #define CYGARC_HAL_LPC24XX_REG_RSID_WDTR (1<<2)
662 #define CYGARC_HAL_LPC24XX_REG_RSID_BODR (1<<3)
664 // System control and status register
665 #define CYGARC_HAL_LPC24XX_REG_SCS 0x01A0
666 #define CYGARC_HAL_LPC24XX_REG_SCS_OSCEN 0x20
667 #define CYGARC_HAL_LPC24XX_REG_SCS_OSCSTAT 0x40
669 // Clock source selection register
670 #define CYGARC_HAL_LPC24XX_REG_CLKSRCSEL 0x010C
671 #define CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_IRC 0x00
672 #define CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_MAIN 0x01
673 #define CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_RTC 0x10
675 #define CYGARC_HAL_LPC24XX_REG_CCLKCFG 0x0104
676 #define CYGARC_HAL_LPC24XX_REG_USBCLKCFG 0x0108
677 #define CYGARC_HAL_LPC24XX_REG_IRCTRIM 0x01A4
678 #define CYGARC_HAL_LPC24XX_REG_PCLKSEL0 0x01A8
679 #define CYGARC_HAL_LPC24XX_REG_PCLKSEL1 0x01AC
680 #define CYGARC_HAL_LPC24XX_REG_INTWAKE 0x0144
683 //=============================================================================
684 // External Memory Controller
685 #define CYGARC_HAL_LPC24XX_REG_EMC_BASE 0xFFE08000
687 #define CYGARC_HAL_LPC24XX_REG_EMC_CTRL 0x0000
688 #define CYGARC_HAL_LPC24XX_REG_EMC_CTRL_EN (1 << 0)
689 #define CYGARC_HAL_LPC24XX_REG_EMC_CTRL_ADDRMIRR (1 << 1)
690 #define CYGARC_HAL_LPC24XX_REG_EMC_CTRL_LOWPOW (1 << 2)
691 #define CYGARC_HAL_LPC24XX_REG_EMC_STATUS 0x0004
692 #define CYGARC_HAL_LPC24XX_REG_EMC_CONFIG 0x0008
693 #define CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL 0x0020
694 #define CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH 0x0024
695 #define CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG 0x0028
696 #define CYGARC_HAL_LPC24XX_REG_EMCD_RP 0x0030
697 #define CYGARC_HAL_LPC24XX_REG_EMCD_RAS 0x0034
698 #define CYGARC_HAL_LPC24XX_REG_EMCD_SREX 0x0038
699 #define CYGARC_HAL_LPC24XX_REG_EMCD_APR 0x003C
700 #define CYGARC_HAL_LPC24XX_REG_EMCD_DAL 0x0040
701 #define CYGARC_HAL_LPC24XX_REG_EMCD_WR 0x0044
702 #define CYGARC_HAL_LPC24XX_REG_EMCD_RC 0x0048
703 #define CYGARC_HAL_LPC24XX_REG_EMCD_RFC 0x004C
704 #define CYGARC_HAL_LPC24XX_REG_EMCD_XSR 0x0050
705 #define CYGARC_HAL_LPC24XX_REG_EMCD_RRD 0x0054
706 #define CYGARC_HAL_LPC24XX_REG_EMCD_MRD 0x0058
707 #define CYGARC_HAL_LPC24XX_REG_EMCS_EXT_WAIT 0x0080
709 #define CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0 0x0100
710 #define CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0 0x0104
711 #define CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG1 0x0120
712 #define CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS1 0x0124
713 #define CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG2 0x0140
714 #define CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS2 0x0144
715 #define CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG3 0x0160
716 #define CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS3 0x0164
718 #define CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG0 0x0200
719 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN0 0x0204
720 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN0 0x0208
721 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD0 0x020C
722 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE0 0x0210
723 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR0 0x0214
724 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN0 0x0218
726 #define CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG1 0x0220
727 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN1 0x0224
728 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN1 0x0228
729 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD1 0x022C
730 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE1 0x0230
731 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR1 0x0234
732 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN1 0x0238
734 #define CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG2 0x0240
735 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN2 0x0244
736 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN2 0x0248
737 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD2 0x024C
738 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE2 0x0250
739 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR2 0x0254
740 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN2 0x0258
742 #define CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG3 0x0260
743 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN3 0x0264
744 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN3 0x0268
745 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD3 0x026C
746 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE3 0x0270
747 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR3 0x0274
748 #define CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN3 0x0278
751 //=============================================================================
752 // Vectored Interrupt Controller (VIC)
754 #define CYGARC_HAL_LPC24XX_REG_VIC_BASE 0xFFFFF000
756 // Registers are offsets from base of this subsystem
758 #define CYGARC_HAL_LPC24XX_REG_VICIRQSTAT 0x000
759 #define CYGARC_HAL_LPC24XX_REG_VICFIQSTAT 0x004
760 #define CYGARC_HAL_LPC24XX_REG_VICRAWINTR 0x008
761 #define CYGARC_HAL_LPC24XX_REG_VICINTSELECT 0x00C
762 #define CYGARC_HAL_LPC24XX_REG_VICINTENABLE 0x010
763 #define CYGARC_HAL_LPC24XX_REG_VICINTENCLEAR 0x014
764 #define CYGARC_HAL_LPC24XX_REG_VICSOFTINT 0x018
765 #define CYGARC_HAL_LPC24XX_REG_VICSOFTINTCLEAR 0x01C
766 #define CYGARC_HAL_LPC24XX_REG_VICPROTECTION 0x020
767 #define CYGARC_HAL_LPC24XX_REG_VICSWPRIOMASK 0x020
769 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR0 0x100
770 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR1 0x104
771 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR2 0x108
772 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR3 0x10C
773 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR4 0x110
774 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR5 0x114
775 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR6 0x118
776 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR7 0x11C
777 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR8 0x120
778 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR9 0x124
779 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR10 0x128
780 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR11 0x12C
781 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR12 0x130
782 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR13 0x134
783 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR14 0x138
784 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR15 0x13C
785 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR16 0x140
786 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR17 0x144
787 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR18 0x148
788 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR19 0x14C
789 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR20 0x150
790 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR21 0x154
791 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR22 0x158
792 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR23 0x15C
793 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR24 0x160
794 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR25 0x164
795 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR26 0x168
796 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR27 0x16C
797 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR28 0x170
798 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR29 0x174
799 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR30 0x178
800 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR31 0x17C
802 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO0 0x200
803 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO1 0x204
804 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO2 0x208
805 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO3 0x20C
806 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO4 0x210
807 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO5 0x214
808 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO6 0x218
809 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO7 0x21C
810 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO8 0x220
811 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO9 0x224
812 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO10 0x228
813 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO11 0x22C
814 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO12 0x230
815 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO13 0x234
816 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO14 0x238
817 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO15 0x23C
818 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO16 0x240
819 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO17 0x244
820 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO18 0x248
821 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO19 0x24C
822 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO20 0x250
823 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO21 0x254
824 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO22 0x258
825 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO23 0x25C
826 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO24 0x260
827 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO25 0x264
828 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO26 0x268
829 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO27 0x26C
830 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO28 0x270
831 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO29 0x274
832 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO30 0x278
833 #define CYGARC_HAL_LPC24XX_REG_VICVECTPRIO31 0x27C
836 #define CYGARC_HAL_LPC24XX_REG_VICVECTADDR 0xF00
838 //-----------------------------------------------------------------------------
840 #endif // CYGONCE_HAL_VAR_IO_H