unified MX27, MX25, MX37 trees
[karo-tx-redboot.git] / packages / hal / arm / lpc2xxx / var / v2_0 / include / var_io.h
1 #ifndef CYGONCE_HAL_VAR_IO_H
2 #define CYGONCE_HAL_VAR_IO_H
3 //=============================================================================
4 //
5 //      var_io.h
6 //
7 //      Variant specific registers
8 //
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 2004 eCosCentric Limited
14 //
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
18 //
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
22 // for more details.
23 //
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 //
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
34 //
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
37 // -------------------------------------------
38 //####ECOSGPLCOPYRIGHTEND####
39 //=============================================================================
40 //#####DESCRIPTIONBEGIN####
41 //
42 // Author(s):   jlarmour
43 // Contributors:
44 // Date:        2004-07-23
45 // Purpose:     Philips LPC2xxx variant specific registers
46 // Description: 
47 // Usage:       #include <cyg/hal/var_io.h>
48 //
49 //####DESCRIPTIONEND####
50 //
51 //=============================================================================
52
53 #include <pkgconf/hal_arm_lpc2xxx.h>  // variant chip model selection.
54 #include <cyg/hal/plf_io.h>
55
56 //=============================================================================
57 // Watchdog (WD)
58
59 #define CYGARC_HAL_LPC2XXX_REG_WD_BASE                   0xE0000000
60
61 // Registers are offsets from base of this subsystem
62 #define CYGARC_HAL_LPC2XXX_REG_WDMOD                     0x0000
63 #define CYGARC_HAL_LPC2XXX_REG_WDMOD_WDEN                (1<<0)
64 #define CYGARC_HAL_LPC2XXX_REG_WDMOD_WDRESET             (1<<1)
65 #define CYGARC_HAL_LPC2XXX_REG_WDMOD_WDTOF               (1<<2)
66 #define CYGARC_HAL_LPC2XXX_REG_WDMOD_WDINT               (1<<3)
67 #define CYGARC_HAL_LPC2XXX_REG_WDTC                      0x0004
68 #define CYGARC_HAL_LPC2XXX_REG_WDFEED                    0x0008
69 #define CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC1             0xAA
70 #define CYGARC_HAL_LPC2XXX_REG_WDFEED_MAGIC2             0x55
71 #define CYGARC_HAL_LPC2XXX_REG_WDTV                      0x000C
72
73 //=============================================================================
74 // Timers (Tx)
75
76 #define CYGARC_HAL_LPC2XXX_REG_TIMER0_BASE               0xE0004000
77 #define CYGARC_HAL_LPC2XXX_REG_TIMER1_BASE               0xE0008000
78
79 // Registers are offsets from base for each timer
80 #define CYGARC_HAL_LPC2XXX_REG_TxIR                      0x0000
81 #define CYGARC_HAL_LPC2XXX_REG_TxIR_MR0                  (1<<0)
82 #define CYGARC_HAL_LPC2XXX_REG_TxIR_MR1                  (1<<1)
83 #define CYGARC_HAL_LPC2XXX_REG_TxIR_MR2                  (1<<2)
84 #define CYGARC_HAL_LPC2XXX_REG_TxIR_MR3                  (1<<3)
85 #define CYGARC_HAL_LPC2XXX_REG_TxIR_CR0                  (1<<4)
86 #define CYGARC_HAL_LPC2XXX_REG_TxIR_CR1                  (1<<5)
87 #define CYGARC_HAL_LPC2XXX_REG_TxIR_CR2                  (1<<6)
88 #define CYGARC_HAL_LPC2XXX_REG_TxIR_CR3                  (1<<7)
89 #define CYGARC_HAL_LPC2XXX_REG_TxTCR                     0x0004
90 #define CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_ENABLE          (1<<0)
91 #define CYGARC_HAL_LPC2XXX_REG_TxTCR_CTR_RESET           (1<<1)
92 #define CYGARC_HAL_LPC2XXX_REG_TxTC                      0x0008
93 #define CYGARC_HAL_LPC2XXX_REG_TxPR                      0x000C
94 #define CYGARC_HAL_LPC2XXX_REG_TxPC                      0x0010
95 #define CYGARC_HAL_LPC2XXX_REG_TxMCR                     0x0014
96 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_INT             (1<<0)
97 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_RESET           (1<<1)
98 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR0_STOP            (1<<2)
99 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR1_INT             (1<<3)
100 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR1_RESET           (1<<4)
101 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR1_STOP            (1<<5)
102 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR2_INT             (1<<6)
103 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR2_RESET           (1<<7)
104 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR2_STOP            (1<<8)
105 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR3_INT             (1<<9)
106 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR3_RESET           (1<<10)
107 #define CYGARC_HAL_LPC2XXX_REG_TxMCR_MR3_STOP            (1<<11)
108 #define CYGARC_HAL_LPC2XXX_REG_TxMR0                     0x0018
109 #define CYGARC_HAL_LPC2XXX_REG_TxMR1                     0x001C
110 #define CYGARC_HAL_LPC2XXX_REG_TxMR2                     0x0020
111 #define CYGARC_HAL_LPC2XXX_REG_TxMR3                     0x0024
112 #define CYGARC_HAL_LPC2XXX_REG_TxCCR                     0x0028
113 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR0_RISE        (1<<0)
114 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR0_FALL        (1<<1)
115 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR0             (1<<2)
116 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR1_RISE        (1<<3)
117 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR1_FALL        (1<<4)
118 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR1             (1<<5)
119 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR2_RISE        (1<<6)
120 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR2_FALL        (1<<7)
121 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR2             (1<<8)
122 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR3_RISE        (1<<9)
123 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR3_FALL        (1<<10)
124 #define CYGARC_HAL_LPC2XXX_REG_TxCCR_INT_CR3             (1<<11)
125 #define CYGARC_HAL_LPC2XXX_REG_TxCR0                     0x002C
126 #define CYGARC_HAL_LPC2XXX_REG_TxCR1                     0x0030
127 #define CYGARC_HAL_LPC2XXX_REG_TxCR2                     0x0034
128 #define CYGARC_HAL_LPC2XXX_REG_TxCR3                     0x0038
129 #define CYGARC_HAL_LPC2XXX_REG_TxEMR                     0x003C
130 #define CYGARC_HAL_LPC2XXX_REG_TxEMR_EM0                 (1<<0)
131 #define CYGARC_HAL_LPC2XXX_REG_TxEMR_EM1                 (1<<1)
132 #define CYGARC_HAL_LPC2XXX_REG_TxEMR_EM2                 (1<<2)
133 #define CYGARC_HAL_LPC2XXX_REG_TxEMR_EM3                 (1<<3)
134
135 //=============================================================================
136 // UARTs (Ux)
137
138 #define CYGARC_HAL_LPC2XXX_REG_UART0_BASE                0xE000C000
139 #define CYGARC_HAL_LPC2XXX_REG_UART1_BASE                0xE0010000
140
141 // Registers are offsets from base for each UART
142 #define CYGARC_HAL_LPC2XXX_REG_UxRBR                     0x0000 // DLAB=0 read
143 #define CYGARC_HAL_LPC2XXX_REG_UxTHR                     0x0000 // DLAB=0 write
144 #define CYGARC_HAL_LPC2XXX_REG_UxDLL                     0x0000 // DLAB=1 r/w
145 #define CYGARC_HAL_LPC2XXX_REG_UxIER                     0x0004 // DLAB=0
146 #define CYGARC_HAL_LPC2XXX_REG_UxIER_RXDATA_INT          (1<<0)
147 #define CYGARC_HAL_LPC2XXX_REG_UxIER_THRE_INT            (1<<1)
148 #define CYGARC_HAL_LPC2XXX_REG_UxIER_RXLS_INT            (1<<2)
149 #define CYGARC_HAL_LPC2XXX_REG_U1IER_RXMS_INT            (1<<3) // U1 only
150 #define CYGARC_HAL_LPC2XXX_REG_UxDLM                     0x0004 // DLAB=1
151
152 #define CYGARC_HAL_LPC2XXX_REG_UxIIR                     0x0008 // read
153 #define CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR0                (1<<0)
154 #define CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR1                (1<<1)
155 #define CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR2                (1<<2)
156 #define CYGARC_HAL_LPC2XXX_REG_UxIIR_IIR3                (1<<3)
157 #define CYGARC_HAL_LPC2XXX_REG_UxIIR_FIFOS               (0xB0)
158
159 #define CYGARC_HAL_LPC2XXX_REG_UxFCR                     0x0008 // write
160 #define CYGARC_HAL_LPC2XXX_REG_UxFCR_FIFO_ENA            (1<<0)
161 #define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_FIFO_RESET       (1<<1)
162 #define CYGARC_HAL_LPC2XXX_REG_UxFCR_TX_FIFO_RESET       (1<<2)
163 #define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_TRIGGER_0        (0x00)
164 #define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_TRIGGER_1        (0x40)
165 #define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_TRIGGER_2        (0x80)
166 #define CYGARC_HAL_LPC2XXX_REG_UxFCR_RX_TRIGGER_3        (0xB0)
167
168 #define CYGARC_HAL_LPC2XXX_REG_UxLCR                     0x000C
169 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_5       (0x00)
170 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_6       (0x01)
171 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_7       (0x02)
172 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_WORD_LENGTH_8       (0x03)
173 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_STOP_1              (0x00)
174 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_STOP_2              (0x04)
175 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_ENA          (0x08)
176 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_ODD          (0x00)
177 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_EVEN         (0x10)
178 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_ONE          (0x20)
179 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_PARITY_ZERO         (0x30)
180 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_BREAK_ENA           (0x40)
181 #define CYGARC_HAL_LPC2XXX_REG_UxLCR_DLAB                (0x80)
182
183
184 // Modem Control Register is UART1 only
185 #define CYGARC_HAL_LPC2XXX_REG_U1MCR                     0x0010
186 #define CYGARC_HAL_LPC2XXX_REG_U1MCR_DTR                 (1<<0)
187 #define CYGARC_HAL_LPC2XXX_REG_U1MCR_RTS                 (1<<1)
188 #define CYGARC_HAL_LPC2XXX_REG_U1MCR_LOOPBACK            (1<<4)
189
190 #define CYGARC_HAL_LPC2XXX_REG_UxLSR                     0x0014
191 #define CYGARC_HAL_LPC2XXX_REG_UxLSR_RDR                 (1<<0)
192 #define CYGARC_HAL_LPC2XXX_REG_UxLSR_OE                  (1<<1)
193 #define CYGARC_HAL_LPC2XXX_REG_UxLSR_PE                  (1<<2)
194 #define CYGARC_HAL_LPC2XXX_REG_UxLSR_FE                  (1<<3)
195 #define CYGARC_HAL_LPC2XXX_REG_UxLSR_BI                  (1<<4)
196 #define CYGARC_HAL_LPC2XXX_REG_UxLSR_THRE                (1<<5)
197 #define CYGARC_HAL_LPC2XXX_REG_UxLSR_TEMT                (1<<6)
198 #define CYGARC_HAL_LPC2XXX_REG_UxLSR_RX_FIFO_ERR         (1<<7)
199
200 // Modem Status Register is UART1 only
201 #define CYGARC_HAL_LPC2XXX_REG_U1MSR                     0x0018
202 #define CYGARC_HAL_LPC2XXX_REG_U1MSR_DCTS                (1<<0)
203 #define CYGARC_HAL_LPC2XXX_REG_U1MSR_DDSR                (1<<1)
204 #define CYGARC_HAL_LPC2XXX_REG_U1MSR_RI_FALL             (1<<2)
205 #define CYGARC_HAL_LPC2XXX_REG_U1MSR_DDCD                (1<<3)
206 #define CYGARC_HAL_LPC2XXX_REG_U1MSR_CTS                 (1<<4)
207 #define CYGARC_HAL_LPC2XXX_REG_U1MSR_DSR                 (1<<5)
208 #define CYGARC_HAL_LPC2XXX_REG_U1MSR_RI                  (1<<6)
209 #define CYGARC_HAL_LPC2XXX_REG_U1MSR_DCD                 (1<<7)
210
211 #define CYGARC_HAL_LPC2XXX_REG_UxSCR                     0x001C
212
213 //=============================================================================
214 // Pulse Width Modulator (PWM)
215
216 #define CYGARC_HAL_LPC2XXX_REG_PWM_BASE                  0xE0014000
217
218 // Registers are offsets from base of this subsystem
219 #define CYGARC_HAL_LPC2XXX_REG_PWMIR                     0x0000
220 #define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR0_INT             (1<<0)
221 #define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR1_INT             (1<<1)
222 #define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR2_INT             (1<<2)
223 #define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR3_INT             (1<<3)
224 #define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR4_INT             (1<<8)
225 #define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR5_INT             (1<<9)
226 #define CYGARC_HAL_LPC2XXX_REG_PWMIR_MR6_INT             (1<<10)
227 #define CYGARC_HAL_LPC2XXX_REG_PWMTCR                    0x0004
228 #define CYGARC_HAL_LPC2XXX_REG_PWMTCR_CTR_ENA            (1<<0)
229 #define CYGARC_HAL_LPC2XXX_REG_PWMTCR_CTR_RESET          (1<<1)
230 #define CYGARC_HAL_LPC2XXX_REG_PWMTCR_PWM_ENA            (1<<3)
231 #define CYGARC_HAL_LPC2XXX_REG_PWMTC                     0x0008
232 #define CYGARC_HAL_LPC2XXX_REG_PWMPR                     0x000C
233 #define CYGARC_HAL_LPC2XXX_REG_PWMPC                     0x0010
234 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR                    0x0014
235 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR0_INT            (1<<0)
236 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR0_RESET          (1<<1)
237 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR0_STOP           (1<<2)
238 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR1_INT            (1<<3)
239 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR1_RESET          (1<<4)
240 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR1_STOP           (1<<5)
241 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR2_INT            (1<<6)
242 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR2_RESET          (1<<7)
243 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR2_STOP           (1<<8)
244 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR3_INT            (1<<9)
245 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR3_RESET          (1<<10)
246 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR3_STOP           (1<<11)
247 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR4_INT            (1<<12)
248 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR4_RESET          (1<<13)
249 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR4_STOP           (1<<14)
250 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR5_INT            (1<<15)
251 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR5_RESET          (1<<16)
252 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR5_STOP           (1<<17)
253 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR6_INT            (1<<18)
254 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR6_RESET          (1<<19)
255 #define CYGARC_HAL_LPC2XXX_REG_PWMMCR_MR6_STOP           (1<<20)
256 #define CYGARC_HAL_LPC2XXX_REG_PWMMR0                    0x0018
257 #define CYGARC_HAL_LPC2XXX_REG_PWMMR1                    0x001C
258 #define CYGARC_HAL_LPC2XXX_REG_PWMMR2                    0x0020
259 #define CYGARC_HAL_LPC2XXX_REG_PWMMR3                    0x0024
260 #define CYGARC_HAL_LPC2XXX_REG_PWMMR4                    0x0040
261 #define CYGARC_HAL_LPC2XXX_REG_PWMMR5                    0x0044
262 #define CYGARC_HAL_LPC2XXX_REG_PWMMR6                    0x0048
263 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR                   0x004C
264 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL1              (1<<1)
265 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL2              (1<<2)
266 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL3              (1<<3)
267 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL4              (1<<4)
268 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL5              (1<<5)
269 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_SEL6              (1<<6)
270 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA1              (1<<9)
271 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA2              (1<<10)
272 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA3              (1<<11)
273 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA4              (1<<12)
274 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA5              (1<<13)
275 #define CYGARC_HAL_LPC2XXX_REG_PWMMPCR_ENA6              (1<<14)
276 #define CYGARC_HAL_LPC2XXX_REG_PWMLER                    0x0050
277 #define CYGARC_HAL_LPC2XXX_REG_PWMLER_M0_ENA             (1<<0)
278 #define CYGARC_HAL_LPC2XXX_REG_PWMLER_M1_ENA             (1<<1)
279 #define CYGARC_HAL_LPC2XXX_REG_PWMLER_M2_ENA             (1<<2)
280 #define CYGARC_HAL_LPC2XXX_REG_PWMLER_M3_ENA             (1<<3)
281 #define CYGARC_HAL_LPC2XXX_REG_PWMLER_M4_ENA             (1<<4)
282 #define CYGARC_HAL_LPC2XXX_REG_PWMLER_M5_ENA             (1<<5)
283 #define CYGARC_HAL_LPC2XXX_REG_PWMLER_M6_ENA             (1<<6)
284
285 //=============================================================================
286 // I2C (I2)
287
288 #define CYGARC_HAL_LPC2XXX_REG_I2_BASE                   0xE001C000
289
290 // Registers are offsets from base of this subsystem
291 #define CYGARC_HAL_LPC2XXX_REG_I2CONSET                  0x0000
292 #define CYGARC_HAL_LPC2XXX_REG_I2CONSET_AA               (1<<2)
293 #define CYGARC_HAL_LPC2XXX_REG_I2CONSET_SI               (1<<3)
294 #define CYGARC_HAL_LPC2XXX_REG_I2CONSET_STO              (1<<4)
295 #define CYGARC_HAL_LPC2XXX_REG_I2CONSET_STA              (1<<5)
296 #define CYGARC_HAL_LPC2XXX_REG_I2CONSET_I2EN             (1<<6)
297 #define CYGARC_HAL_LPC2XXX_REG_I2STAT                    0x0004
298 #define CYGARC_HAL_LPC2XXX_REG_I2STAT_SHIFT              3
299 #define CYGARC_HAL_LPC2XXX_REG_I2DAT                     0x0008
300 #define CYGARC_HAL_LPC2XXX_REG_I2ADR                     0x000C
301 #define CYGARC_HAL_LPC2XXX_REG_I2ADR_GC                  (1<<0)
302 #define CYGARC_HAL_LPC2XXX_REG_I2SCLH                    0x0010
303 #define CYGARC_HAL_LPC2XXX_REG_I2SCLL                    0x0014
304 #define CYGARC_HAL_LPC2XXX_REG_I2CONCLR                  0x0018
305 #define CYGARC_HAL_LPC2XXX_REG_I2CONCLR_AAC              (1<<2)
306 #define CYGARC_HAL_LPC2XXX_REG_I2CONCLR_SIC              (1<<3)
307 #define CYGARC_HAL_LPC2XXX_REG_I2CONCLR_STAC             (1<<5)
308 #define CYGARC_HAL_LPC2XXX_REG_I2CONCLR_I2ENC            (1<<6)
309
310 //=============================================================================
311 // SPI (S)
312
313 #define CYGARC_HAL_LPC2XXX_REG_SPI0_BASE                  0xE0020000
314 #define CYGARC_HAL_LPC2XXX_REG_SPI1_BASE                  0xE0030000
315
316 // Registers are offsets from base of this subsystem
317 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR                   0x0000
318 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_CPHA              (1<<3)
319 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_CPOL              (1<<4)
320 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_MSTR              (1<<5)
321 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_LSBF              (1<<6)
322 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPCR_SPIE              (1<<7)
323 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR                   0x0004
324 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_ABRT              (1<<3)
325 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_MODF              (1<<4)
326 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_ROVR              (1<<5)
327 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_WCOL              (1<<6)
328 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPSR_SPIF              (1<<7)
329 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPDR                   0x0008
330 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPCCR                  0x000C
331 #define CYGARC_HAL_LPC2XXX_REG_SPI_SPINT                  0x001C
332
333
334 //=============================================================================
335 // RTC
336
337 #define CYGARC_HAL_LPC2XXX_REG_RTC_BASE                   0xE0024000
338
339 // Registers are offsets from base of this subsystem
340
341 #define CYGARC_HAL_LPC2XXX_REG_RTC_ILR                    0x0000
342 #define CYGARC_HAL_LPC2XXX_REG_RTC_ILR_CIF                (1<<0)
343 #define CYGARC_HAL_LPC2XXX_REG_RTC_ILR_ALF                (1<<1)
344 #define CYGARC_HAL_LPC2XXX_REG_RTC_CTC                    0x0004
345 #define CYGARC_HAL_LPC2XXX_REG_RTC_CCR                    0x0008
346 #define CYGARC_HAL_LPC2XXX_REG_RTC_CCR_CLKEN              (1<<0)
347 #define CYGARC_HAL_LPC2XXX_REG_RTC_CCR_CTCRST             (1<<1)
348 #define CYGARC_HAL_LPC2XXX_REG_RTC_CIIR                   0x000C
349 #define CYGARC_HAL_LPC2XXX_REG_RTC_AMR                    0x0010
350 #define CYGARC_HAL_LPC2XXX_REG_RTC_CTIME0                 0x0014
351 #define CYGARC_HAL_LPC2XXX_REG_RTC_CTIME1                 0x0018
352 #define CYGARC_HAL_LPC2XXX_REG_RTC_CTIME2                 0x001C
353 #define CYGARC_HAL_LPC2XXX_REG_RTC_SEC                    0x0020
354 #define CYGARC_HAL_LPC2XXX_REG_RTC_MIN                    0x0024
355 #define CYGARC_HAL_LPC2XXX_REG_RTC_HOUR                   0x0028
356 #define CYGARC_HAL_LPC2XXX_REG_RTC_DOM                    0x002C
357 #define CYGARC_HAL_LPC2XXX_REG_RTC_DOW                    0x0030
358 #define CYGARC_HAL_LPC2XXX_REG_RTC_DOY                    0x0034
359 #define CYGARC_HAL_LPC2XXX_REG_RTC_MONTH                  0x0038
360 #define CYGARC_HAL_LPC2XXX_REG_RTC_YEAR                   0x003C
361 #define CYGARC_HAL_LPC2XXX_REG_RTC_ALSEC                  0x0060
362 #define CYGARC_HAL_LPC2XXX_REG_RTC_ALMIN                  0x0064
363 #define CYGARC_HAL_LPC2XXX_REG_RTC_ALHOUR                 0x0068
364 #define CYGARC_HAL_LPC2XXX_REG_RTC_ALDOM                  0x006C
365 #define CYGARC_HAL_LPC2XXX_REG_RTC_ALDOW                  0x0070
366 #define CYGARC_HAL_LPC2XXX_REG_RTC_ALDOY                  0x0074
367 #define CYGARC_HAL_LPC2XXX_REG_RTC_ALMON                  0x0078
368 #define CYGARC_HAL_LPC2XXX_REG_RTC_ALYEAR                 0x007C
369 #define CYGARC_HAL_LPC2XXX_REG_RTC_PREINT                 0x0080
370 #define CYGARC_HAL_LPC2XXX_REG_RTC_PREFRAC                0x0084
371
372 //=============================================================================
373 // GPIO (IO)
374
375 #define CYGARC_HAL_LPC2XXX_REG_IO_BASE                   0xE0028000
376
377 #if defined(CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC210X)
378
379 // Registers are offsets from base of this subsystem
380 #define CYGARC_HAL_LPC2XXX_REG_IOPIN                     0x000
381 #define CYGARC_HAL_LPC2XXX_REG_IOSET                     0x004
382 #define CYGARC_HAL_LPC2XXX_REG_IODIR                     0x008
383 #define CYGARC_HAL_LPC2XXX_REG_IOCLR                     0x00C
384
385 #else
386
387 // Registers are offsets from base of this subsystem
388 #define CYGARC_HAL_LPC2XXX_REG_IO0PIN                    0x000
389 #define CYGARC_HAL_LPC2XXX_REG_IO0SET                    0x004
390 #define CYGARC_HAL_LPC2XXX_REG_IO0DIR                    0x008
391 #define CYGARC_HAL_LPC2XXX_REG_IO0CLR                    0x00C
392
393 #define CYGARC_HAL_LPC2XXX_REG_IO1PIN                    0x010
394 #define CYGARC_HAL_LPC2XXX_REG_IO1SET                    0x014
395 #define CYGARC_HAL_LPC2XXX_REG_IO1DIR                    0x018
396 #define CYGARC_HAL_LPC2XXX_REG_IO1CLR                    0x01C
397
398 #define CYGARC_HAL_LPC2XXX_REG_IO2PIN                    0x020
399 #define CYGARC_HAL_LPC2XXX_REG_IO2SET                    0x024
400 #define CYGARC_HAL_LPC2XXX_REG_IO2DIR                    0x028
401 #define CYGARC_HAL_LPC2XXX_REG_IO2CLR                    0x02C
402
403 #define CYGARC_HAL_LPC2XXX_REG_IO3PIN                    0x030
404 #define CYGARC_HAL_LPC2XXX_REG_IO3SET                    0x034
405 #define CYGARC_HAL_LPC2XXX_REG_IO3DIR                    0x038
406 #define CYGARC_HAL_LPC2XXX_REG_IO3CLR                    0x03C
407
408 #endif
409
410 //=============================================================================
411 // Pin Connect Block (PIN)
412
413 #define CYGARC_HAL_LPC2XXX_REG_PIN_BASE                  0xE002C000
414
415 // Registers are offsets from base of this subsystem
416 #define CYGARC_HAL_LPC2XXX_REG_PINSEL0                   0x000
417 #define CYGARC_HAL_LPC2XXX_REG_PINSEL1                   0x004
418 #define CYGARC_HAL_LPC2XXX_REG_PINSEL2                   0x014
419
420 //=============================================================================
421 // ADC (AD)
422
423 #define CYGARC_HAL_LPC2XXX_REG_AD_BASE                  0xE0034000
424
425 // Registers are offsets from base of this subsystem
426 #define CYGARC_HAL_LPC2XXX_REG_ADCR                     0x0000
427 #define CYGARC_HAL_LPC2XXX_REG_ADCR_BURST               (1<<16)
428 #define CYGARC_HAL_LPC2XXX_REG_ADCR_PDN                 (1<<21)
429 #define CYGARC_HAL_LPC2XXX_REG_ADCR_EDGE                (1<<27)
430 #define CYGARC_HAL_LPC2XXX_REG_ADDR                     0x0004
431 #define CYGARC_HAL_LPC2XXX_REG_ADDR_OVERRUN             (1<<30)
432 #define CYGARC_HAL_LPC2XXX_REG_ADDR_DONE                (1<<31)
433
434 //=============================================================================
435 // System Control Block
436
437 #define CYGARC_HAL_LPC2XXX_REG_SCB_BASE                 0xE01FC000
438
439 // Registers are offsets from base of this subsystem
440
441 // Memory accelerator module
442 #define CYGARC_HAL_LPC2XXX_REG_MAMCR                    0x0000
443 #define CYGARC_HAL_LPC2XXX_REG_MAMCR_DISABLED           0x00
444 #define CYGARC_HAL_LPC2XXX_REG_MAMCR_PARTIAL            0x01
445 #define CYGARC_HAL_LPC2XXX_REG_MAMCR_FULL               0x02
446 #define CYGARC_HAL_LPC2XXX_REG_MAMTIM                   0x0004
447
448 // Memory mapping control
449 #define CYGARC_HAL_LPC2XXX_REG_MEMMAP                   0x0040
450
451 // PLL
452 #define CYGARC_HAL_LPC2XXX_REG_PLLCON                   0x0080
453 #define CYGARC_HAL_LPC2XXX_REG_PLLCON_PLLE              (1<<0)
454 #define CYGARC_HAL_LPC2XXX_REG_PLLCON_PLLC              (1<<1)
455 #define CYGARC_HAL_LPC2XXX_REG_PLLCFG                   0x0084
456 #define CYGARC_HAL_LPC2XXX_REG_PLLSTAT                  0x0088
457 #define CYGARC_HAL_LPC2XXX_REG_PLLSTAT_PLLE              0x100      // (1<<8)
458 #define CYGARC_HAL_LPC2XXX_REG_PLLSTAT_PLLC              0x200      // (1<<9)
459 #define CYGARC_HAL_LPC2XXX_REG_PLLSTAT_PLOCK             0x400      // (1<<10)
460 #define CYGARC_HAL_LPC2XXX_REG_PLLFEED                  0x008C
461
462 // Power Control
463 #define CYGARC_HAL_LPC2XXX_REG_PCON                     0x00C0
464 #define CYGARC_HAL_LPC2XXX_REG_PCON_IDL                 (1<<0)
465 #define CYGARC_HAL_LPC2XXX_REG_PCON_PD                  (1<<1)
466 #define CYGARC_HAL_LPC2XXX_REG_PCONP                    0x00C4
467 #define CYGARC_HAL_LPC2XXX_REG_PCONP_TIM0               (1<<1)
468 #define CYGARC_HAL_LPC2XXX_REG_PCONP_TIM1               (1<<2)
469 #define CYGARC_HAL_LPC2XXX_REG_PCONP_URT0               (1<<3)
470 #define CYGARC_HAL_LPC2XXX_REG_PCONP_URT1               (1<<4)
471 #define CYGARC_HAL_LPC2XXX_REG_PCONP_PWM0               (1<<5)
472 #define CYGARC_HAL_LPC2XXX_REG_PCONP_I2C                (1<<7)
473 #define CYGARC_HAL_LPC2XXX_REG_PCONP_SPI0               (1<<8)
474 #define CYGARC_HAL_LPC2XXX_REG_PCONP_RTC                (1<<9)
475 #define CYGARC_HAL_LPC2XXX_REG_PCONP_SPI1               (1<<10)
476 #define CYGARC_HAL_LPC2XXX_REG_PCONP_AD                 (1<<12)
477
478 // VPB Divider
479 #define CYGARC_HAL_LPC2XXX_REG_VPBDIV                   0x0100
480
481 // External interrupt inputs
482 #define CYGARC_HAL_LPC2XXX_REG_EXTINT                   0x0140
483 #define CYGARC_HAL_LPC2XXX_REG_EXTWAKE                  0x0144
484 #define CYGARC_HAL_LPC2XXX_REG_EXTMODE                  0x0148
485 #define CYGARC_HAL_LPC2XXX_REG_EXTPOLAR                 0x014C
486
487 #define CYGARC_HAL_LPC2XXX_REG_EXTxxx_INT0              (1<<0)
488 #define CYGARC_HAL_LPC2XXX_REG_EXTxxx_INT1              (1<<1)
489 #define CYGARC_HAL_LPC2XXX_REG_EXTxxx_INT2              (1<<2)
490 #define CYGARC_HAL_LPC2XXX_REG_EXTxxx_INT3              (1<<3)
491
492
493 //=============================================================================
494 // External Memory Controller
495
496 #if defined(CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC22XX)
497
498 #define CYGARC_HAL_LPC2XXX_REG_BCFG0                    0xFFE00000
499 #define CYGARC_HAL_LPC2XXX_REG_BCFG1                    0xFFE00004
500 #define CYGARC_HAL_LPC2XXX_REG_BCFG2                    0xFFE00008
501 #define CYGARC_HAL_LPC2XXX_REG_BCFG3                    0xFFE0000C
502
503 #define CYGARC_HAL_LPC2XXX_REG_BCFGx_RBLE               (1<<10)
504 #define CYGARC_HAL_LPC2XXX_REG_BCFGx_BUSERR             (1<<24)
505 #define CYGARC_HAL_LPC2XXX_REG_BCFGx_WPERR              (1<<25)
506 #define CYGARC_HAL_LPC2XXX_REG_BCFGx_WP                 (1<<26)
507 #define CYGARC_HAL_LPC2XXX_REG_BCFGx_BM                 (1<<27)
508 #define CYGARC_HAL_LPC2XXX_REG_BCFGx_MW_8BIT            (0x00000000)
509 #define CYGARC_HAL_LPC2XXX_REG_BCFGx_MW_16BIT           (0x10000000)
510 #define CYGARC_HAL_LPC2XXX_REG_BCFGx_MW_32BIT           (0x20000000)
511
512 #endif
513
514 //=============================================================================
515 // Vectored Interrupt Controller (VIC)
516
517 #define CYGARC_HAL_LPC2XXX_REG_VIC_BASE                 0xFFFFF000
518
519 // Registers are offsets from base of this subsystem
520
521 #define CYGARC_HAL_LPC2XXX_REG_VICIRQSTAT               0x0000
522 #define CYGARC_HAL_LPC2XXX_REG_VICFIQSTAT               0x0004
523 #define CYGARC_HAL_LPC2XXX_REG_VICRAWINTR               0x0008
524 #define CYGARC_HAL_LPC2XXX_REG_VICINTSELECT             0x000C
525 #define CYGARC_HAL_LPC2XXX_REG_VICINTENABLE             0x0010
526 #define CYGARC_HAL_LPC2XXX_REG_VICINTENCLEAR            0x0014
527 #define CYGARC_HAL_LPC2XXX_REG_VICSOFTINT               0x0018
528 #define CYGARC_HAL_LPC2XXX_REG_VICSOFTINTCLEAR          0x001C
529 #define CYGARC_HAL_LPC2XXX_REG_VICPROTECTION            0x0020
530 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR              0x0030
531 #define CYGARC_HAL_LPC2XXX_REG_VICDEFVECTADDR           0x0034
532
533 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR0             0x0100
534 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR1             0x0104
535 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR2             0x0108
536 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR3             0x010C
537 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR4             0x0110
538 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR5             0x0114
539 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR6             0x0118
540 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR7             0x011C
541 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR8             0x0120
542 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR9             0x0124
543 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR10            0x0128
544 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR11            0x012C
545 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR12            0x0130
546 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR13            0x0134
547 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR14            0x0138
548 #define CYGARC_HAL_LPC2XXX_REG_VICVECTADDR15            0x013C
549
550 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL0             0x0200
551 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL1             0x0204
552 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL2             0x0208
553 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL3             0x020C
554 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL4             0x0210
555 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL5             0x0214
556 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL6             0x0218
557 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL7             0x021C
558 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL8             0x0220
559 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL9             0x0224
560 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL10            0x0228
561 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL11            0x022C
562 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL12            0x0230
563 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL13            0x0234
564 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL14            0x0238
565 #define CYGARC_HAL_LPC2XXX_REG_VICVECTCNTL15            0x023C
566
567
568 //-----------------------------------------------------------------------------
569 // end of var_io.h
570 #endif // CYGONCE_HAL_VAR_IO_H