1 #ifndef CYGONCE_HAL_VAR_IO_H
2 #define CYGONCE_HAL_VAR_IO_H
3 //=============================================================================
7 // Variant specific registers
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2006 eCosCentric Ltd.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): Ilija Koco <ilijak@siva.com.mk>
46 // Purpose: MAC7100 variant specific registers
47 // Description: based on freescale's mac7100.h
48 // Usage: #include <cyg/hal/var_io.h>
50 //####DESCRIPTIONEND####
52 //=============================================================================
54 #include <cyg/hal/plf_io.h>
56 #if !defined HAL_IO_MACROS_NO_ADDRESS_MUNGING
57 #define HAL_IO_MACROS_NO_ADDRESS_MUNGING 1
58 #endif // HAL_IO_MACROS_NO_ADDRESS_MUNGING
60 // *********************************************************************
64 // *********************************************************************
66 // Interrupt Controller Definitions
67 #define MAC7100_INTC_BASE (0xFC048000)
69 #define MAC7100_IPRH_OFFSET (0x0000)
70 #define MAC7100_IPRL_OFFSET (0x0004)
71 #define MAC7100_IMRH_OFFSET (0x0008)
72 #define MAC7100_IMRL_OFFSET (0x000C)
73 #define MAC7100_INTFRCH_OFFSET (0x0010)
74 #define MAC7100_INTFRCL_OFFSET (0x0014)
75 #define MAC7100_ICONFIG_OFFSET (0x001B)
76 #define MAC7100_SIMR_OFFSET (0x001C)
77 #define MAC7100_CIMR_OFFSET (0x001D)
78 #define MAC7100_CLMASK_OFFSET (0x001E) // CLMASK - Current Level Mask Register
79 #define MAC7100_SLMASK_OFFSET (0x001F) // SLMASK - Saved Level Mask Register
80 #define MAC7100_ICR_OFFSET (0x0040)
81 #define MAC7100_IRQIACK_OFFSET (0x00EC)
82 #define MAC7100_FIQIACK_OFFSET (0x00F0)
84 #define MAC7100_INTC_IPRH(intc_base) (intc_base + MAC7100_IPRH_OFFSET)
85 #define MAC7100_INTC_IPRL(intc_base) (intc_base + MAC7100_IPRL_OFFSET)
86 #define MAC7100_INTC_IMRH(intc_base) (intc_base + MAC7100_IMRH_OFFSET)
87 #define MAC7100_INTC_IMRL(intc_base) (intc_base + MAC7100_IMRL_OFFSET)
88 #define MAC7100_INTC_INTFRC(intc_base) (intc_base + MAC7100_INTFRCH_OFFSET)
89 #define MAC7100_INTC_INTFRCH(intc_base) (intc_base + MAC7100_INTFRCH_OFFSET)
90 #define MAC7100_INTC_INTFRCL(intc_base) (intc_base + MAC7100_INTFRCL_OFFSET)
91 #define MAC7100_INTC_ICONFIG(intc_base) (intc_base + MAC7100_ICONFIG_OFFSET)
92 #define MAC7100_INTC_IRQIACK(intc_base) (intc_base + MAC7100_IRQIACK_OFFSET)
93 #define MAC7100_INTC_FIQIACK(intc_base) (intc_base + MAC7100_FIQIACK_OFFSET)
94 #define MAC7100_INTC_ICR(intc_base,src) (intc_base + MAC7100_ICR_OFFSET + src)
95 #define MAC7100_INTC_SIMR(intc_base) (intc_base + MAC7100_SIMR_OFFSET)
96 #define MAC7100_INTC_CIMR(intc_base) (intc_base + MAC7100_CIMR_OFFSET)
97 #define MAC7100_INTC_CLMASK(intc_base) (intc_base + MAC7100_CLMASK_OFFSET)
98 #define MAC7100_INTC_SLMASK(intc_base) (intc_base + MAC7100_SLMASK_OFFSET)
100 #define MAC7100_INTC_INT_LEVEL(lev) (lev)
102 // hardware interrupt source vector numbers
103 #define MAC7100_EDMA0_IV (0)
104 #define MAC7100_EDMA1_IV (1)
105 #define MAC7100_EDMA2_IV (2)
106 #define MAC7100_EDMA3_IV (3)
107 #define MAC7100_EDMA4_IV (4)
108 #define MAC7100_EDMA5_IV (5)
109 #define MAC7100_EDMA6_IV (6)
110 #define MAC7100_EDMA7_IV (7)
111 #define MAC7100_EDMA8_IV (8)
112 #define MAC7100_EDMA9_IV (9)
113 #define MAC7100_EDMA10_IV (10)
114 #define MAC7100_EDMA11_IV (11)
115 #define MAC7100_EDMA12_IV (12)
116 #define MAC7100_EDMA13_IV (13)
117 #define MAC7100_EDMA14_IV (14)
118 #define MAC7100_EDMA15_IV (15)
119 #define MAC7100_EDMA_Error_IV (16)
120 #define MAC7100_MCM_SWT_IV (17)
121 #define MAC7100_CRG_IV (18)
122 #define MAC7100_PIT1_IV (19)
123 #define MAC7100_PIT2_IV (20)
124 #define MAC7100_PIT3_IV (21)
125 #define MAC7100_PIT4_RTI_IV (22)
126 #define MAC7100_VREG_IV (23)
127 #define MAC7100_CAN_A_MB_IV (24)
128 #define MAC7100_CAN_A_MB14_IV (25)
129 #define MAC7100_CAN_A_Error_IV (26)
130 #define MAC7100_CAN_B_MB_IV (27)
131 #define MAC7100_CAN_B_MB14_IV (28)
132 #define MAC7100_CAN_B_Error_IV (29)
133 #define MAC7100_CAN_C_MB_IV (30)
134 #define MAC7100_CAN_C_MB14_IV (31)
135 #define MAC7100_CAN_C_Error_IV (32)
136 #define MAC7100_CAN_D_MB_IV (33)
137 #define MAC7100_CAN_D_MB14_IV (34)
138 #define MAC7100_CAN_D_Error_IV (35)
139 #define MAC7100_I2C_IV (36)
140 #define MAC7100_DSPI_A_IV (37)
141 #define MAC7100_DSPI_B_IV (38)
142 #define MAC7100_ESCI_A_IV (39)
143 #define MAC7100_ESCI_B_IV (40)
144 #define MAC7100_ESCI_C_IV (41)
145 #define MAC7100_ESCI_D_IV (42)
146 #define MAC7100_EMIOS0_IV (43)
147 #define MAC7100_EMIOS1_IV (44)
148 #define MAC7100_EMIOS2_IV (45)
149 #define MAC7100_EMIOS3_IV (46)
150 #define MAC7100_EMIOS4_IV (47)
151 #define MAC7100_EMIOS5_IV (48)
152 #define MAC7100_EMIOS6_IV (49)
153 #define MAC7100_EMIOS7_IV (50)
154 #define MAC7100_EMIOS8_IV (51)
155 #define MAC7100_EMIOS9_IV (52)
156 #define MAC7100_EMIOS10_IV (53)
157 #define MAC7100_EMIOS11_IV (54)
158 #define MAC7100_EMIOS12_IV (55)
159 #define MAC7100_EMIOS13_IV (56)
160 #define MAC7100_EMIOS14_IV (57)
161 #define MAC7100_EMIOS15_IV (58)
162 #define MAC7100_ATD_IV (59)
163 #define MAC7100_CFM_IV (60)
164 #define MAC7100_PIM_IV (61)
165 #define MAC7100_IRQ_IV (62)
166 #define MAC7100_XIRQ_IV (63)
168 #define MAC7100_IRQ_SPURIOUS (-1)
170 // *******************************************************************
173 // Note: eSCI definitions are in cyg/devs/ser_esci.h
174 // *******************************************************************
175 #define CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE 0xFC0C4000
176 #define CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_VECTOR MAC7100_ESCI_A_IV
178 #define CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE 0xFC0C8000
179 #define CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_VECTOR MAC7100_ESCI_B_IV
181 #define CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE 0xFC0CC000
182 #define CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_VECTOR MAC7100_ESCI_C_IV
184 #define CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE 0xFC0D0000
185 #define CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_VECTOR MAC7100_ESCI_D_IV
187 #define CYGNUM_DEV_SER_FREESCALE_ESCI_SYSTEM_CLOCK \
188 (CYGNUM_HAL_ARM_MAC7100_CLOCK_SPEED/2)
189 #define FREESCALE_ESCI_BAUD(baud_rate) \
190 ((CYGNUM_DEV_SER_FREESCALE_ESCI_SYSTEM_CLOCK)/(baud_rate*16))
193 // *********************************************************************
197 // *********************************************************************
199 // Periodic Interrupt Timer Module Definitions
201 #define MAC7100_PIT_BASE (0xFC08C000)
202 #define MAC7100_TLVAL0_OFFSET (0x0000)
203 #define MAC7100_TVAL0_OFFSET (0x0080)
205 #define MAC7100_PIT_TLVAL(pit_base,chan) \
206 (pit_base + MAC7100_TLVAL0_OFFSET + (4 * chan))
207 #define MAC7100_PIT_TVAL(pit_base,chan) \
208 (pit_base + MAC7100_TVAL0_OFFSET + (4 * chan))
210 #define MAC7100_PITFLG_OFFSET (0x0100)
211 #define MAC7100_PITINTEN_OFFSET (0x0104)
212 #define MAC7100_PITINTSEL_OFFSET (0x0108)
213 #define MAC7100_PITEN_OFFSET (0x010C)
214 #define MAC7100_PITCTRL_OFFSET (0x0110)
216 #define MAC7100_PIT_FLAG_RTIF (0x00000001)
217 #define MAC7100_PIT_FLAG_TIF(chan) (0x00000001 << chan)
218 #define MAC7100_PIT_INTSEL_ISEL(chan) (0x00000001 << chan)
219 #define MAC7100_PIT_INTEN_RTIE (0x00000001)
220 #define MAC7100_PIT_INTEN_TIE(chan) (0x00000001 << chan)
222 #define MAC7100_PIT_EN_RTIEN (0x00000001)
223 #define MAC7100_PIT_EN_PEN(chan) (0x00000001 << chan)
225 #define MAC7100_PIT_FLG(pit_base) (pit_base + MAC7100_PITFLG_OFFSET)
226 #define MAC7100_PIT_INTEN(pit_base) (pit_base + MAC7100_PITINTEN_OFFSET)
227 #define MAC7100_PIT_INTSEL(pit_base) (pit_base + MAC7100_PITINTSEL_OFFSET)
228 #define MAC7100_PIT_EN(pit_base) (pit_base + MAC7100_PITEN_OFFSET)
230 #define MAC7100_PIT_CTRL(pit_base) (pit_base + MAC7100_PITCTRL_OFFSET)
231 #define MAC7100_PIT_MDIS (0x01000000)
234 // *********************************************************************
238 // *********************************************************************/
240 #define MAC7100_PIM_BASE (0xFC0E8000)
242 #define MAC7100_PORT_A_OFFSET (0x000)
243 #define MAC7100_PORT_B_OFFSET (0x040)
244 #define MAC7100_PORT_C_OFFSET (0x080)
245 #define MAC7100_PORT_D_OFFSET (0x0C0)
246 #define MAC7100_PORT_E_OFFSET (0x100)
247 #define MAC7100_PORT_F_OFFSET (0x140)
248 #define MAC7100_PORT_G_OFFSET (0x180)
249 #define MAC7100_PORT_H_OFFSET (0x1C0)
250 #define MAC7100_PORT_I_OFFSET (0x200)
252 // PORT Pin Configuration Registers
253 #define MAC7100_PIM_CONFIG(port,pin) (MAC7100_PIM_BASE+port+((pin)*2))
254 // Port Wide Interrupt Flag Register
255 #define MAC7100_PIM_PORTIFR(port) (MAC7100_PIM_BASE+port+0x20)
256 // Port Wide Data Read/Write Register
257 #define MAC7100_PIM_PORTDATA(port) (MAC7100_PIM_BASE+port+0x24)
258 // Port Wide Input Register
259 #define MAC7100_PIM_PORTIR(port) (MAC7100_PIM_BASE+port+0x26)
260 // Port Pin Data Registers
261 #define MAC7100_PIM_DATA(port,pin) (MAC7100_PIM_BASE+port+0x28+pin)
263 // Global Interrupt Status Register
264 #define MAC7100_PIM_GLBLINT (MAC7100_PIM_BASE+0x03C0)
265 // PIM Configuration Register
266 #define MAC7100_PIM_PIMCONFIG (MAC7100_PIM_BASE+0x03C2)
267 // TDI Pin Configuration Register
268 #define MAC7100_PIM_CONFIG_TDI (MAC7100_PIM_BASE+0x03C4)
269 // TDO Pin Configuration Register
270 #define MAC7100_PIM_CONFIG_TDO (MAC7100_PIM_BASE+0x03C6)
271 // TMS Pin Configuration Register
272 #define MAC7100_PIM_CONFIG_TMS (MAC7100_PIM_BASE+0x03C8)
273 // TCK Pin Configuration Register
274 #define MAC7100_PIM_CONFIG_TCK (MAC7100_PIM_BASE+0x03CA)
275 // TA Pin Configuration Register
276 #define MAC7100_PIM_CONFIG_TA (MAC7100_PIM_BASE+0x03CC)
278 // Bit definitions and macros for PIM_PA_CONFIGn
279 // Pin Interrupt Flag Register
280 #define MAC7100_PIM_PIFR (0x0001)
281 // Pin Interrupt Enable Register
282 #define MAC7100_PIM_PIER (0x0002)
283 // Pull-up/down Enable Register
284 #define MAC7100_PIM_PULL(x) (((x)&0x0003)<<2)
285 // Reduced Drive Strength Register
286 #define MAC7100_PIM_RDR (0x0010)
287 // Open Drain Enable Register
288 #define MAC7100_PIM_ODER (0x0020)
289 // Data Direction Register
290 #define MAC7100_PIM_DDR (0x0040)
291 #define MAC7100_PIM_MODE (0x0080)
292 #define MAC7100_PIM_MODE_PERIPHERAL MAC7100_PIM_MODE
294 // Bit definitions and macros for PIM_GLBLINT
296 #define MAC7100_PIM_INT_PENDING(x) (((x)&0x01FF)<<0)
298 // Bit definitions and macros for PIM_PIMCONFIG
299 // Clock Enable for the EIM module
300 #define MAC7100_PIM_PORTHSEL (0x0001)
302 #define MAC7100_PIM_EIMCLKEN (0x0002)
304 #define MAC7100_PIM_PORT32IR(port32ir) (MAC7100_PIM_BASE+0x03E0+port32ir)
306 #define MAC7100_PIM_PORT32IR_AB (0x00)
307 #define MAC7100_PIM_PORT32IR_CD (0x04)
308 #define MAC7100_PIM_PORT32IR_EF (0x08)
309 #define MAC7100_PIM_PORT32IR_GH (0x0C)
310 #define MAC7100_PIM_PORT32IR_BC (0x10)
311 #define MAC7100_PIM_PORT32IR_DE (0x14)
312 #define MAC7100_PIM_PORT32IR_FG (0x18)
313 #define MAC7100_PIM_PORT32IR_HI (0x1C)
316 // ********************************************************************
320 // ********************************************************************
322 // Register read/write macros
323 #define MAC7100_CRG_BASE 0xFC088000 // SYNR - Synthesizer Register
324 #define MAC7100_CRG_SYNR 0xFC088000 // SYNR - Synthesizer Register
325 #define MAC7100_CRG_REFDV 0xFC088001 // REFDV - Reference Divider Register
326 #define MAC7100_CRG_CTFLG 0xFC088002 // CTFLG - Test Flags Register (reserved)
327 #define MAC7100_CRG_CRGFLG 0xFC088003 // CRGFLG - Flags Register
328 #define MAC7100_CRG_CRGINT 0xFC088004 // CRGINT - Interrupt Enable Register
329 #define MAC7100_CRG_CLKSEL 0xFC088005 // CLKSEL - Clock Select Register
330 #define MAC7100_CRG_PLLCTL 0xFC088006 // PLLCTL - PLL Control Register
331 #define MAC7100_CRG_SDMCTL 0xFC088007 // SDMCTL - STOP/DOZE Control Register
332 #define MAC7100_CRG_BDMCTL 0xFC088008 // BDMCTL - BDM Control Register
333 #define MAC7100_CRG_FORBYP 0xFC088009 // FORBYP - Force and Bypass Test
334 #define MAC7100_CRG_CTCTL 0xFC08800A // CTCTL - Test Control Register (resvd)
336 // Bit definitions and macros for CRG_SYNR
337 #define MAC7100_CRG_SYN(x) (((x)&0x3F)<<0) // Synthesizer Count value
339 // Bit definitions and macros for CRG_REFDV
340 #define MAC7100_CRG_REFD(x) (((x)&0x0F)<<0) //Reference divider
342 // Bit definitions and macros for CRG_CRGFLG
343 #define MAC7100_CRG_SCM (0x01) //Self Clock Mode Status
344 #define MAC7100_CRG_SCMIF (0x02) //Self Clock Mode Interrupt Flag
345 #define MAC7100_CRG_TRACK (0x04) //Track Status
346 #define MAC7100_CRG_LOCK (0x08) //Lock Status
347 #define MAC7100_CRG_LOCKIF (0x10) //PLL Lock Interrupt Flag
348 #define MAC7100_CRG_LVRF (0x20) //Low Voltage Reset Flag
349 #define MAC7100_CRG_PORF (0x40) //Power on Reset Flag
350 #define MAC7100_CRG_STPEF (0x80) //Stop Entry Flag
352 // Bit definitions and macros for CRG_CRGINT
353 #define MAC7100_CRG_SCMIE (0x02) //Self Clock Mode Interrupt Enable
354 #define MAC7100_CRG_LOCKIE (0x10) //Lock Interrupt Enable
356 // Bit definitions and macros for CRG_CLKSEL
357 #define MAC7100_CRG_SWTDOZE (0x01) //SWT stops in Doze Mode
358 #define MAC7100_CRG_RTIDOZE (0x02) /* RTI stops in Doze Mode */
359 #define MAC7100_CRG_PLLDOZE (0x08) /* PLL stops in Doze Mode */
360 #define MAC7100_CRG_DOZE_ROA (0x10) /* Reduced Osc Amp in Doze Mode */
361 #define MAC7100_CRG_PSTP (0x40) /* Pseudo Stop */
362 #define MAC7100_CRG_PLLSEL (0x80) /* PLL Select */
364 // Bit definitions and macros for CRG_PLLCTL
365 #define MAC7100_CRG_SCME (0x01) //Self Clock Mode Enable
366 #define MAC7100_CRG_PWE (0x02) //SWT Enable during Pseudo Stop
367 #define MAC7100_CRG_PRE (0x04) //RTI Enable during Pseudo Stop
368 #define MAC7100_CRG_FSTWKP (0x08) //Fast Wake-up from Full Stop Bit
369 #define MAC7100_CRG_ACQ (0x10) //Acquisition
370 #define MAC7100_CRG_AUTO (0x20) //Automatic Bandwidth Control
371 #define MAC7100_CRG_PLLON (0x40) //Phase Lock Loop On
372 #define MAC7100_CRG_CME (0x80) //Clock Monitor Enable
374 // Bit definitions and macros for CRG_SDMCTL
375 #define MAC7100_CRG_STOP (0x01) //STOP mode
376 #define MAC7100_CRG_DOZE (0x02) //DOZE mode
378 // Bit definitions and macros for CRG_BDMCTL
379 #define MAC7100_CRG_RSBCK (0x40) //SWT & RTI stop in Active BDM mode
382 // *********************************************************************
386 // *********************************************************************
388 // Register read/write macros
389 #define MAC7100_MCM_PCT 0xFC040000 //
390 #define MAC7100_MCM_REV 0xFC040002 //
391 #define MAC7100_MCM_AMC 0xFC040004 //
392 #define MAC7100_MCM_ASC 0xFC040006 //
393 #define MAC7100_MCM_IMC 0xFC040008 //
394 // MRSR - Miscellaneous Reset Status Register
395 #define MAC7100_MCM_MRSR 0xFC04000F
396 // MWCR - Miscellaneous Wakeup Control Register
397 #define MAC7100_MCM_MWCR 0xFC040013
398 // MSWTCR - Miscellaneous Software Watchdog Timer Control Register
399 #define MAC7100_MCM_MSWTCR 0xFC040016
400 // MSWTSR - Miscellaneous Software Watchdog Timer Service Register
401 #define MAC7100_MCM_MSWTSR 0xFC04001B
402 // MSWTIR - Miscellaneous Software Watchdog Timer Interrupt Register
403 #define MAC7100_MCM_MSWTIR 0xFC04001F
404 // AAMR - AXBS Address Map Register
405 #define MAC7100_MCM_AAMR 0xFC040020
406 // CFADR - Core Fault Address Register
407 #define MAC7100_MCM_CFADR 0xFC040070
408 // CFLOC - Core Fault Location Register
409 #define MAC7100_MCM_CFLOC 0xFC040076
410 // CFATR - Core Fault Attributes Register
411 #define MAC7100_MCM_CFATR 0xFC040077
412 // CFDTR - Core Fault Data Register
413 #define MAC7100_MCM_CFDTR 0xFC04007C
415 // Bit definitions and macros for MCM_AMC
417 // AXBS Master Configuration
418 #define MAC7100_MCM_AXMC(x) (((x)&0x00FF)<<0)
420 // Bit definitions and macros for MCM_ASC
421 // AXBS Slave Configuration
422 #define MAC7100_MCM_AXSC(x) (((x)&0x00FF)<<0)
423 #define MAC7100_MCM_DP64 (0x8000) // 64-bit Datapath
425 // Bit definitions and macros for MCM_MRSR
426 #define MAC7100_MCM_SWTR (0x20) // Watchdog Timer Reset
427 #define MAC7100_MCM_DIR (0x40) // Device Input Reset
428 #define MAC7100_MCM_POR (0x80) // Power-On Reset
430 // Bit definitions and macros for MCM_MWCR
431 #define MAC7100_MCM_PRILVL(x) (((x)&0x0F)<<0) // Interrupt Priority Level
432 #define MAC7100_MCM_ENBWCR (0x80) // Enable WCR
434 // Bit definitions and macros for MCM_MSWTCR
435 #define MAC7100_MCM_SWT(x) (((x)&0x001F)<<0) // Watchdog Time-Out Period
436 #define MAC7100_MCM_SWRI(x) (((x)&0x0003)<<5) // Watchdog Reset/Interrupt
437 #define MAC7100_MCM_SWE (0x0080) // Watchdog Enable
438 #define MAC7100_MCM_SWRWH (0x0100) // Watchdog Run While Halted
439 #define MAC7100_MCM_SWCIN16 (0x0200) // Force SWT CarryIn16
440 #define MAC7100_MCM_RO (0x8000) // Read-Only
442 // Bit definitions and macros for MCM_MSWTIR
443 #define MAC7100_MCM_SWTIC (0x01) // Watchdog Interrupt Flag
445 // Bit definitions and macros for MCM_AAMR
448 // Address 0 Slave Number
449 #define MAC7100_MCM_ASLAVE(adr_reg,sl_n) (((sl_n)&0x00000007)<<(adr_reg*4)
450 // Enable Address Region 0
451 #define MAC7100_MCM_EA(adr_reg) (0x00000008<<(adr_reg*4))
453 // Bit definitions and macros for MCM_CFLOC
454 #define MAC7100_MCM_LOCALERR (0x80) // Bus Error Indicator
456 // Bit definitions and macros for MCM_CFATR
457 // Protection fault type
458 #define MAC7100_MCM_PROTECTION(x) (((x)&0x0F)<<0)
459 // 8-16-32-64-bit core access
460 #define MAC7100_MCM_SIZE(x) (((x)&0x07)<<4)
461 // Core read/write access
462 #define MAC7100_MCM_WRITE (0x80)
464 //=============================================================================
465 // FIQ interrupt vector which is shared by all HAL variants.
467 #define CYGNUM_HAL_INTERRUPT_FIQ 0
468 #endif // CYGONCE_HAL_VAR_IO_H
469 //-----------------------------------------------------------------------------