1 /*=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //===========================================================================*/
42 #include <pkgconf/hal.h>
44 #include <cyg/infra/cyg_type.h> // base types
45 #include <cyg/infra/cyg_trac.h> // tracing macros
46 #include <cyg/infra/cyg_ass.h> // assertion macros
48 #include <cyg/hal/hal_arch.h> // basic machine info
49 #include <cyg/hal/hal_intr.h> // interrupt macros
50 #include <cyg/hal/hal_io.h> // IO macros
51 #include <cyg/hal/hal_diag.h>
52 #include <cyg/hal/hal_if.h> // Calling-if API
53 #include <cyg/hal/drv_api.h> // driver API
54 #include <cyg/hal/hal_misc.h> // Helper functions
55 #include <cyg/hal/hal_soc.h> // Hardware definitions
56 #include <cyg/hal/fsl_board.h> // Platform specifics
58 static void cyg_hal_plf_duart_init(void);
59 extern void cyg_hal_plf_serial_init(void);
60 extern unsigned int system_rev;
62 void cyg_hal_plf_comms_init(void)
64 static int initialized = 0;
71 /* Setup GPIO and enable transceiver for UARTs */
72 #if CYGHWR_HAL_ARM_SOC_UART1 != 0
73 *REG32_PTR(MX21_GPIOE_BASE+KHwGpioGIUS) &= ~0x00003000;
74 BitSetEIO(EIO_UART1_EN);
76 #if CYGHWR_HAL_ARM_SOC_UART2 != 0
77 *REG32_PTR(MX21_GPIOE_BASE+KHwGpioGIUS) &= ~0x000000C0;
78 BitSetEIO(EIO_UART2_EN);
80 #if CYGHWR_HAL_ARM_SOC_UART3 != 0
81 *REG32_PTR(MX21_GPIOE_BASE+KHwGpioGIUS) &= ~0x00000300;
82 BitSetEIO(EIO_UART3_EN);
84 #if CYGHWR_HAL_ARM_SOC_UART4 != 0
85 if (system_rev == MX21_SILICONID_Rev2 || system_rev == MX21_SILICONID_Rev31) {
86 *REG32_PTR(MX21_GPIOB_BASE+KHwGpioGPR) = 0x10000000;
87 *REG32_PTR(MX21_GPIOB_BASE+KHwGpioGIUS) = 0xEFFFFFF0;
88 } else if (system_rev == MX21_SILICONID_OLD) {
89 *REG32_PTR(MX21_GPIOB_BASE+KHwGpioGPR) |= 0x30000000;
90 *REG32_PTR(MX21_GPIOB_BASE+KHwGpioGIUS) &= ~0x30000000;
93 BitSetEIO(EIO_UART4_EN);
96 cyg_hal_plf_duart_init();
97 cyg_hal_plf_serial_init();
100 //=============================================================================
101 // ST16552 DUART driver
102 //=============================================================================
104 //-----------------------------------------------------------------------------
105 // There are two serial ports.
106 #define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x10) // port A
107 #define CYG_DEV_SERIAL_BASE_B (BOARD_CS_UART_BASE + 0x00) // port B
109 //-----------------------------------------------------------------------------
110 // Default baud rate is 38400
111 // Based on 3.6864 MHz xtal
112 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
113 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
114 #define CYG_DEV_SERIAL_BAUD_LSB 0x18
116 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
117 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
118 #define CYG_DEV_SERIAL_BAUD_LSB 0x0C
120 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
121 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
122 #define CYG_DEV_SERIAL_BAUD_LSB 0x06
124 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
125 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
126 #define CYG_DEV_SERIAL_BAUD_LSB 0x04
128 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
129 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
130 #define CYG_DEV_SERIAL_BAUD_LSB 0x02
133 #ifndef CYG_DEV_SERIAL_BAUD_MSB
134 #error Missing/incorrect serial baud rate defined - CDL error?
137 //-----------------------------------------------------------------------------
138 // Define the serial registers. The board is equipped with a 16552
142 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
143 #define HAL_READ_UINT_UART HAL_READ_UINT16
144 typedef cyg_uint16 uart_width;
146 typedef cyg_uint8 uart_width;
147 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
148 #define HAL_READ_UINT_UART HAL_READ_UINT8
151 #define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
152 #define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
153 #define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
154 #define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
155 #define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
156 #define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
157 #define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
158 #define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
159 #define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
160 #define CYG_DEV_SERIAL_MCR 0x04
161 #define CYG_DEV_SERIAL_MCR_A 0x04
162 #define CYG_DEV_SERIAL_MCR_B 0x04
163 #define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
164 #define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
165 #define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
167 // The interrupt enable register bits.
168 #define SIO_IER_ERDAI 0x01 // enable received data available irq
169 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
170 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
171 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
173 // The interrupt identification register bits.
174 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
175 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
179 // The line status register bits.
180 #define SIO_LSR_DR 0x01 // data ready
181 #define SIO_LSR_OE 0x02 // overrun error
182 #define SIO_LSR_PE 0x04 // parity error
183 #define SIO_LSR_FE 0x08 // framing error
184 #define SIO_LSR_BI 0x10 // break interrupt
185 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
186 #define SIO_LSR_TEMT 0x40 // transmitter register empty
187 #define SIO_LSR_ERR 0x80 // any error condition
189 // The modem status register bits.
190 #define SIO_MSR_DCTS 0x01 // delta clear to send
191 #define SIO_MSR_DDSR 0x02 // delta data set ready
192 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
193 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
194 #define SIO_MSR_CTS 0x10 // clear to send
195 #define SIO_MSR_DSR 0x20 // data set ready
196 #define SIO_MSR_RI 0x40 // ring indicator
197 #define SIO_MSR_DCD 0x80 // data carrier detect
199 // The line control register bits.
200 #define SIO_LCR_WLS0 0x01 // word length select bit 0
201 #define SIO_LCR_WLS1 0x02 // word length select bit 1
202 #define SIO_LCR_STB 0x04 // number of stop bits
203 #define SIO_LCR_PEN 0x08 // parity enable
204 #define SIO_LCR_EPS 0x10 // even parity select
205 #define SIO_LCR_SP 0x20 // stick parity
206 #define SIO_LCR_SB 0x40 // set break
207 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
209 // The FIFO control register
210 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
211 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
212 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
214 //-----------------------------------------------------------------------------
218 cyg_int32 msec_timeout;
222 static channel_data_t channels[] = {
223 #if CYGHWR_HAL_ARM_DUART_UARTA != 0
224 {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
226 #if CYGHWR_HAL_ARM_DUART_UARTB != 0
227 {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
231 //-----------------------------------------------------------------------------
233 static void init_duart_channel(channel_data_t* __ch_data)
235 uart_width* base = __ch_data->base;
239 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
240 SIO_LCR_WLS0 | SIO_LCR_WLS1);
242 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
244 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
245 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
246 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
247 lcr &= ~SIO_LCR_DLAB;
248 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
249 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
252 void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
254 uart_width* base = ((channel_data_t*)__ch_data)->base;
257 CYGARC_HAL_SAVE_GP();
260 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
261 } while ((lsr & SIO_LSR_THRE) == 0);
263 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
265 // Hang around until the character has been safely sent.
267 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
268 } while ((lsr & SIO_LSR_THRE) == 0);
270 CYGARC_HAL_RESTORE_GP();
273 static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
275 uart_width* base = ((channel_data_t*)__ch_data)->base;
276 uart_width lsr, ch16;
278 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
279 if ((lsr & SIO_LSR_DR) == 0)
282 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
284 *ch = (cyg_uint8) (ch16 & 0x00FF);
289 cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
293 CYGARC_HAL_SAVE_GP();
295 while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
297 CYGARC_HAL_RESTORE_GP();
301 static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
304 CYGARC_HAL_SAVE_GP();
307 cyg_hal_plf_duart_putc(__ch_data, *__buf++);
309 CYGARC_HAL_RESTORE_GP();
312 static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
315 CYGARC_HAL_SAVE_GP();
318 *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
320 CYGARC_HAL_RESTORE_GP();
323 cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
326 channel_data_t* chan = (channel_data_t*)__ch_data;
329 CYGARC_HAL_SAVE_GP();
331 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
333 res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
334 if (res || 0 == delay_count--)
337 CYGACC_CALL_IF_DELAY_US(100);
340 CYGARC_HAL_RESTORE_GP();
344 static int cyg_hal_plf_duart_control(void *__ch_data,
345 __comm_control_cmd_t __func, ...)
347 static int irq_state = 0;
348 channel_data_t* chan = (channel_data_t*)__ch_data;
352 CYGARC_HAL_SAVE_GP();
355 case __COMMCTL_IRQ_ENABLE:
356 HAL_INTERRUPT_UNMASK(chan->isr_vector);
357 HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
358 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
359 ier |= SIO_IER_ERDAI;
360 HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
363 case __COMMCTL_IRQ_DISABLE:
366 HAL_INTERRUPT_MASK(chan->isr_vector);
367 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
368 ier &= ~SIO_IER_ERDAI;
369 HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
371 case __COMMCTL_DBG_ISR_VECTOR:
372 ret = chan->isr_vector;
374 case __COMMCTL_SET_TIMEOUT:
378 va_start(ap, __func);
380 ret = chan->msec_timeout;
381 chan->msec_timeout = va_arg(ap, cyg_uint32);
389 CYGARC_HAL_RESTORE_GP();
393 static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
394 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
396 channel_data_t* chan = (channel_data_t*)__ch_data;
399 CYGARC_HAL_SAVE_GP();
401 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
402 _iir &= SIO_IIR_ID_MASK;
405 if ( ISR_Rx == _iir ) {
408 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
409 if (lsr & SIO_LSR_DR) {
411 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
413 c8 = (cyg_uint8) (c & 0x00FF);
415 if (cyg_hal_is_break( &c8 , 1 ))
419 // Acknowledge the interrupt
420 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
421 res = CYG_ISR_HANDLED;
424 CYGARC_HAL_RESTORE_GP();
428 static void cyg_hal_plf_duart_init(void)
430 hal_virtual_comm_table_t* comm;
431 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
435 #define NUMOF(x) (sizeof(x)/sizeof(x[0]))
436 for (i = 0; i < NUMOF(channels); i++) {
437 HAL_INTERRUPT_MASK(channels[i].isr_vector);
438 init_duart_channel(&channels[i]);
439 CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
440 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
441 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
442 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
443 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
444 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
445 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
446 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
447 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
448 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
451 // Restore original console
452 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
455 //=============================================================================
456 // Compatibility with older stubs
457 //=============================================================================
459 //=============================================================================
460 // Compatibility with older stubs
461 //=============================================================================
463 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
465 #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
467 #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
468 #define __BASE CMA101_DUARTA
469 #define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
470 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
471 #define __BASE CMA101_DUARTB
472 #define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
477 #ifdef CYGSEM_HAL_ROM_MONITOR
478 #define CYG_HAL_STARTUP_ROM
479 #define CYG_HAL_STARTUP_ROMRAM
480 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
483 #if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
484 #define HAL_DIAG_USES_HARDWARE
485 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
486 #define HAL_DIAG_USES_HARDWARE
487 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
488 #define HAL_DIAG_USES_HARDWARE
491 static channel_data_t channel = {
492 (uart_width*) _BASE, 0, 0
495 #ifdef HAL_DIAG_USES_HARDWARE
497 void hal_diag_init(void)
500 char *msg = "\n\rARM eCos\n\r";
505 init_duart_channel(&channel);
507 while (*msg) hal_diag_write_char(*msg++);
511 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
512 #define DIAG_BUFSIZE 32
514 #define DIAG_BUFSIZE 2048
516 static char diag_buffer[DIAG_BUFSIZE];
517 static int diag_bp = 0;
520 void hal_diag_write_char(char c)
526 cyg_hal_plf_duart_putc(&channel, c)
529 diag_buffer[diag_bp++] = c;
530 if (diag_bp == DIAG_BUFSIZE) {
537 void hal_diag_read_char(char *c)
539 *c = cyg_hal_plf_duart_getc(&channel);
542 #else // HAL_DIAG relies on GDB
544 // Initialize diag port - assume GDB channel is already set up
545 void hal_diag_init(void)
547 if (0) init_duart_channel(&channel); // avoid warning
550 // Actually send character down the wire
551 static void hal_diag_write_char_serial(char c)
553 cyg_hal_plf_duart_putc(&channel, c);
556 static bool hal_diag_read_serial(char *c)
558 long timeout = 1000000000; // A long time...
560 while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
561 if (0 == --timeout) return false;
566 void hal_diag_read_char(char *c)
568 while (!hal_diag_read_serial(c)) ;
571 void hal_diag_write_char(char c)
573 static char line[100];
576 // No need to send CRs
577 if (c == '\r') return;
581 if (c == '\n' || pos == sizeof(line)) {
582 CYG_INTERRUPT_STATE old;
584 // Disable interrupts. This prevents GDB trying to interrupt us
585 // while we are in the middle of sending a packet. The serial
586 // receive interrupt will be seen when we re-enable interrupts
589 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
590 CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
592 HAL_DISABLE_INTERRUPTS(old);
596 static char hex[] = "0123456789ABCDEF";
601 hal_diag_write_char_serial('$');
602 hal_diag_write_char_serial('O');
604 for (i = 0; i < pos; i++) {
606 char h = hex[(ch>>4)&0xF];
607 char l = hex[ch&0xF];
608 hal_diag_write_char_serial(h);
609 hal_diag_write_char_serial(l);
613 hal_diag_write_char_serial('#');
614 hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
615 hal_diag_write_char_serial(hex[csum&0xF]);
617 // Wait for the ACK character '+' from GDB here and handle
618 // receiving a ^C instead. This is the reason for this clause
620 if (!hal_diag_read_serial(&c1))
621 continue; // No response - try sending packet again
624 break; // a good acknowledge
626 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
627 cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
629 // Ctrl-C: breakpoint.
630 cyg_hal_gdb_interrupt (__builtin_return_address(0));
634 // otherwise, loop round again
639 // And re-enable interrupts
640 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
641 CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
643 HAL_RESTORE_INTERRUPTS(old);
652 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
654 /*---------------------------------------------------------------------------*/