packages/hal/arm/mx21/var/v2_0/include/hal_cache.h

   1 #ifndef CYGONCE_HAL_CACHE_H
   2 #define CYGONCE_HAL_CACHE_H
   3
   4 //=============================================================================
   5 //
   6 //      hal_cache.h
   7 //
   8 //      HAL cache control API
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
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  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44
  45 #include <cyg/infra/cyg_type.h>
  46 #include <cyg/hal/hal_soc.h>         // Variant specific hardware definitions
  47
  48 //-----------------------------------------------------------------------------
  49 // Cache dimensions
  50
  51 // Data cache
  52 #define HAL_DCACHE_SIZE                 0x4000    // 16KB Size of data cache in bytes
  53 #define HAL_DCACHE_LINE_SIZE            32    // Size of a data cache line
  54 #define HAL_DCACHE_WAYS                 64    // Associativity of the cache
  55
  56 // Instruction cache
  57 #define HAL_ICACHE_SIZE                 0x4000    // Size of cache in bytes
  58 #define HAL_ICACHE_LINE_SIZE            32    // Size of a cache line
  59 #define HAL_ICACHE_WAYS                 64    // Associativity of the cache
  60
  61 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  62 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  63
  64 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
  65 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x20
  66 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
  67 //-----------------------------------------------------------------------------
  68 // Global control of data cache
  69
  70 // Enable the data cache
  71 #define HAL_DCACHE_ENABLE()                                             \
  72 CYG_MACRO_START                                                         \
  73     asm volatile (                                                      \
  74         "mrc  p15,0,r1,c1,c0,0;"                                        \
  75         "orr  r1,r1,#0x0007;" /* enable DCache (also ensures    */      \
  76                               /* the MMU, alignment faults, and */      \
  77         "mcr  p15,0,r1,c1,c0,0"                                         \
  78         :                                                               \
  79         :                                                               \
  80         : "r1" /* Clobber list */                                       \
  81         );                                                              \
  82 CYG_MACRO_END
  83
  84 // Disable the data cache
  85 #define HAL_DCACHE_DISABLE()    \
  86 CYG_MACRO_START                                                         \
  87     asm volatile (                                                      \
  88         "mov    r1,#0;"                                                 \
  89         "mcr  p15,0,r1,c7,c6,0;" /* clear data cache */                  \
  90         "mrc  p15,0,r1,c1,c0,0;"                                        \
  91         "bic  r1,r1,#0x0004;" /* disable DCache  */                     \
  92                               /* but not MMU and alignment faults */    \
  93         "mcr  p15,0,r1,c1,c0,0"                                        \
  94         :                                                               \
  95         :                                                               \
  96         : "r1" /* Clobber list */                                       \
  97         );                                                              \
  98 CYG_MACRO_END
  99
 100 // Invalidate the entire cache
 101 #define HAL_DCACHE_INVALIDATE_ALL()                                     \
 102 CYG_MACRO_START  /* this macro can discard dirty cache lines. */        \
 103     asm volatile (                                                      \
 104         "mov    r0,#0;"                                                 \
 105         "mcr    p15,0,r0,c7,c6,0;" /* flush d-cache */                  \
 106         "mcr    p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */                 \
 107         :                                                               \
 108         :                                                               \
 109         : "r0","memory" /* clobber list */);                            \
 110 CYG_MACRO_END
 111
 112 // Synchronize the contents of the cache with memory.
 113 // using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
 114 #if 1
 115 #define HAL_DCACHE_SYNC()                                               \
 116 CYG_MACRO_START                                                         \
 117     asm volatile (                                                      \
 118         "nop; "                                                \
 119         "nop; "                                                \
 120         "nop; "                                                \
 121         "nop; "                                                \
 122         "nop; "                                                \
 123         "nop; "                                                \
 124         "1: "                                                \
 125         "mrc p15, 0, r15, c7, c14, 3;"                                                \
 126         "bne 1b;"                                                           \
 127         "mov    r0, #0x0;"                                                    \
 128         "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
 129         :                                                               \
 130         :                                                               \
 131         : "r0" /* Clobber list */                                       \
 132         );                                                              \
 133 CYG_MACRO_END
 134
 135 #else
 136 #define HAL_DCACHE_SYNC()                                               \
 137 CYG_MACRO_START                                                         \
 138     cyg_uint32 _tmp1, _tmp2;                                            \
 139     asm volatile (                                                      \
 140         "mov    %0, #0;"                                                \
 141         "1: "                                                           \
 142         "mov    %1, #0;"                                                \
 143         "2: "                                                           \
 144         "orr    r0,%0,%1;"                                              \
 145         "mcr    p15,0,r0,c7,c14,2;"  /* clean index in DCache */        \
 146         "add    %1,%1,%2;"                                              \
 147         "cmp    %1,%3;"                                                 \
 148         "bne    2b;"                                                    \
 149         "add    %0,%0,#0x04000000;"  /* get to next index */            \
 150         "cmp    %0,#0;"                                                 \
 151         "bne    1b;"                                                    \
 152         "mov    r0, #0x0;"                                                    \
 153         "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
 154         : "=r" (_tmp1), "=r" (_tmp2)                                    \
 155         : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP),            \
 156           "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT)            \
 157         : "r0" /* Clobber list */                                       \
 158         );                                                              \
 159 CYG_MACRO_END
 160 #endif
 161
 162 // Query the state of the data cache
 163 #define HAL_DCACHE_IS_ENABLED(_state_)                                   \
 164 CYG_MACRO_START                                                          \
 165     register int reg;                                                    \
 166     asm volatile (  \
 167         "nop; "                                                \
 168         "nop; "                                                \
 169         "nop; "                                                \
 170         "nop; "                                                \
 171         "nop; "                                                \
 172         "mrc  p15,0,%0,c1,c0,0;"                               \
 173                   : "=r"(reg)                                            \
 174                   :                                                      \
 175         );                                                               \
 176     (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */           \
 177 CYG_MACRO_END
 178
 179 // Purge contents of data cache
 180 //#define HAL_DCACHE_PURGE_ALL() -- not used
 181
 182 // Set the data cache refill burst size
 183 //#define HAL_DCACHE_BURST_SIZE(_size_)
 184
 185 // Set the data cache write mode
 186 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 187
 188 //#define HAL_DCACHE_WRITETHRU_MODE       0
 189 //#define HAL_DCACHE_WRITEBACK_MODE       1
 190
 191 // Load the contents of the given address range into the data cache
 192 // and then lock the cache so that it stays there.
 193 //#define HAL_DCACHE_LOCK(_base_, _size_)
 194
 195 // Undo a previous lock operation
 196 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
 197
 198 // Unlock entire cache
 199 //#define HAL_DCACHE_UNLOCK_ALL()
 200
 201 //-----------------------------------------------------------------------------
 202 // Data cache line control
 203
 204 // Allocate cache lines for the given address range without reading its
 205 // contents from memory.
 206 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 207
 208 // Write dirty cache lines to memory and invalidate the cache entries
 209 // for the given address range.
 210 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 211
 212 // Invalidate cache lines in the given range without writing to memory.
 213 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 214
 215 // Write dirty cache lines to memory for the given address range.
 216 //#define HAL_DCACHE_STORE( _base_ , _size_ )
 217
 218 // Preread the given range into the cache with the intention of reading
 219 // from it later.
 220 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 221
 222 // Preread the given range into the cache with the intention of writing
 223 // to it later.
 224 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 225
 226 // Allocate and zero the cache lines associated with the given range.
 227 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
 228
 229 //-----------------------------------------------------------------------------
 230 // Global control of Instruction cache
 231
 232 // Enable the instruction cache
 233 #define HAL_ICACHE_ENABLE()                                             \
 234 CYG_MACRO_START                                                         \
 235     asm volatile (                                                      \
 236         "mrc  p15,0,r1,c1,c0,0;"                                        \
 237         "orr  r1,r1,#0x1000;"                                           \
 238         "orr  r1,r1,#0x0003;" /* enable ICache (also ensures   */       \
 239                               /* that MMU and alignment faults */       \
 240                               /* are enabled)                  */       \
 241         "mcr  p15,0,r1,c1,c0,0"                                         \
 242         :                                                               \
 243         :                                                               \
 244         : "r1" /* Clobber list */                                       \
 245         );                                                              \
 246 CYG_MACRO_END
 247
 248 // Query the state of the instruction cache
 249 #define HAL_ICACHE_IS_ENABLED(_state_)                                   \
 250 CYG_MACRO_START                                                          \
 251     register cyg_uint32 reg;                                             \
 252     asm volatile ("mrc  p15,0,%0,c1,c0,0"                                \
 253                   : "=r"(reg)                                            \
 254                   :                                                      \
 255         );                                                               \
 256     (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */     \
 257 CYG_MACRO_END
 258
 259 // Disable the instruction cache
 260 #define HAL_ICACHE_DISABLE()                                            \
 261 CYG_MACRO_START                                                         \
 262     asm volatile (                                                      \
 263         "mrc    p15,0,r1,c1,c0,0;"                                      \
 264         "bic    r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
 265         "mcr    p15,0,r1,c1,c0,0;"                                      \
 266         "mov    r1,#0;"                                                 \
 267         "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
 268         "nop;" /* next few instructions may be via cache    */          \
 269         "nop;"                                                          \
 270         "nop;"                                                          \
 271         "nop;"                                                          \
 272         "nop;"                                                          \
 273         "nop"                                                           \
 274         :                                                               \
 275         :                                                               \
 276         : "r1" /* Clobber list */                                       \
 277         );                                                              \
 278 CYG_MACRO_END
 279
 280 // Invalidate the entire cache
 281 #define HAL_ICACHE_INVALIDATE_ALL()                                     \
 282 CYG_MACRO_START                                                         \
 283     /* this macro can discard dirty cache lines (N/A for ICache) */     \
 284     asm volatile (                                                      \
 285         "mov    r1,#0;"                                                 \
 286         "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
 287         "mcr    p15,0,r1,c8,c5,0;"  /* flush ITLB only */               \
 288         "nop;" /* next few instructions may be via cache    */          \
 289         "nop;"                                                          \
 290         "nop;"                                                          \
 291         "nop;"                                                          \
 292         "nop;"                                                          \
 293         "nop;"                                                          \
 294         :                                                               \
 295         :                                                               \
 296         : "r1" /* Clobber list */                                       \
 297         );                                                              \
 298 CYG_MACRO_END
 299
 300 // Synchronize the contents of the cache with memory.
 301 // (which includes flushing out pending writes)
 302 #define HAL_ICACHE_SYNC()                                       \
 303 CYG_MACRO_START                                                 \
 304     HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
 305     HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
 306 CYG_MACRO_END
 307
 308 #else
 309
 310
 311 // Set the instruction cache refill burst size
 312 //#define HAL_ICACHE_BURST_SIZE(_size_)
 313
 314 // Load the contents of the given address range into the instruction cache
 315 // and then lock the cache so that it stays there.
 316 //#define HAL_ICACHE_LOCK(_base_, _size_)
 317
 318 // Undo a previous lock operation
 319 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
 320
 321 // Unlock entire cache
 322 //#define HAL_ICACHE_UNLOCK_ALL()
 323
 324 //-----------------------------------------------------------------------------
 325 // Instruction cache line control
 326
 327 // Invalidate cache lines in the given range without writing to memory.
 328 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 329
 330 //-----------------------------------------------------------------------------
 331 #endif // ifndef CYGONCE_HAL_CACHE_H
 332 // End of hal_cache.h