packages/hal/arm/mx25/var/v2_0/include/hal_soc.h

   1 //==========================================================================
   2 //
   3 //              hal_soc.h
   4 //
   5 //              SoC chip definitions
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 // Copyright (C) 2002 Gary Thomas
  13 //
  14 // eCos is free software; you can redistribute it and/or modify it under
  15 // the terms of the GNU General Public License as published by the Free
  16 // Software Foundation; either version 2 or (at your option) any later version.
  17 //
  18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  21 // for more details.
  22 //
  23 // You should have received a copy of the GNU General Public License along
  24 // with eCos; if not, write to the Free Software Foundation, Inc.,
  25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  26 //
  27 // As a special exception, if other files instantiate templates or use macros
  28 // or inline functions from this file, or you compile this file and link it
  29 // with other works to produce a work based on this file, this file does not
  30 // by itself cause the resulting work to be covered by the GNU General Public
  31 // License. However the source code for this file must still be made available
  32 // in accordance with section (3) of the GNU General Public License.
  33 //
  34 // This exception does not invalidate any other reasons why a work based on
  35 // this file might be covered by the GNU General Public License.
  36 //
  37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  38 // at http://sources.redhat.com/ecos/ecos-license/
  39 // -------------------------------------------
  40 //####ECOSGPLCOPYRIGHTEND####
  41 //========================================================================*/
  42
  43 #ifndef __HAL_SOC_H__
  44 #define __HAL_SOC_H__
  45
  46 #ifdef __ASSEMBLER__
  47 #define UL(a)            (a)
  48
  49 #define REG8_VAL(a)                      (a)
  50 #define REG16_VAL(a)             (a)
  51 #define REG32_VAL(a)             (a)
  52
  53 #define REG8_PTR(a)                      (a)
  54 #define REG16_PTR(a)             (a)
  55 #define REG32_PTR(a)             (a)
  56
  57 #else /* __ASSEMBLER__ */
  58 #define UL(a)            (a##UL)
  59
  60 extern char HAL_PLATFORM_EXTRA[];
  61 #define REG8_VAL(a)                      ((unsigned char)(a))
  62 #define REG16_VAL(a)             ((unsigned short)(a))
  63 #define REG32_VAL(a)             ((unsigned int)(a))
  64
  65 #define REG8_PTR(a)                      ((volatile unsigned char *)(a))
  66 #define REG16_PTR(a)             ((volatile unsigned short *)(a))
  67 #define REG32_PTR(a)             ((volatile unsigned int *)(a))
  68 #define readb(a)                         (*(volatile unsigned char *)(a))
  69 #define readw(a)                         (*(volatile unsigned short *)(a))
  70 #define readl(a)                         (*(volatile unsigned int *)(a))
  71 #define writeb(v,a)                      (*(volatile unsigned char *)(a) = (v))
  72 #define writew(v,a)                      (*(volatile unsigned short *)(a) = (v))
  73 #define writel(v,a)                      (*(volatile unsigned int *)(a) = (v))
  74
  75 #endif /* __ASSEMBLER__ */
  76
  77 /*
  78  * Default Memory Layout Definitions
  79  */
  80
  81 /*
  82  * AIPS 1
  83  */
  84 #define AIPS1_BASE_ADDR                 UL(0x43F00000)
  85 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
  86 #define MAX_BASE_ADDR                   UL(0x43F04000)
  87 #define CLKCTL_BASE_ADDR                UL(0x43F08000)
  88 #define ETB_SLOT4_BASE_ADDR             UL(0x43F0C000)
  89 #define ETB_SLOT5_BASE_ADDR             UL(0x43F10000)
  90 #define ECT_CTIO_BASE_ADDR              UL(0x43F18000)
  91 #define I2C_BASE_ADDR                   UL(0x43F80000)
  92 #define I2C3_BASE_ADDR                  UL(0x43F84000)
  93 #define CAN1_BASE_ADDR                  UL(0x43F88000)
  94 #define CAN2_BASE_ADDR                  UL(0x43F8C000)
  95 #define UART1_BASE_ADDR                 UL(0x43F90000)
  96 #define UART2_BASE_ADDR                 UL(0x43F94000)
  97 #define I2C2_BASE_ADDR                  UL(0x43F98000)
  98 #define OWIRE_BASE_ADDR                 UL(0x43F9C000)
  99 #define CSPI1_BASE_ADDR                 UL(0x43FA4000)
 100 #define KPP_BASE_ADDR                   UL(0x43FA8000)
 101 #define IOMUXC_BASE_ADDR                UL(0x43FAC000)
 102 #define AUDMUX_BASE_ADDR                UL(0x43FB0000)
 103 #define ECT_IP1_BASE_ADDR               UL(0x43FB8000)
 104 #define ECT_IP2_BASE_ADDR               UL(0x43FBC000)
 105
 106 /*
 107  * SPBA
 108  */
 109 #define SPBA_BASE_ADDR                  UL(0x50000000)
 110 #define CSPI3_BASE_ADDR                 UL(0x50040000)
 111 #define UART4_BASE_ADDR                 UL(0x50008000)
 112 #define UART3_BASE_ADDR                 UL(0x5000C000)
 113 #define CSPI2_BASE_ADDR                 UL(0x50010000)
 114 #define SSI2_BASE_ADDR                  UL(0x50014000)
 115 #define ESAI_BASE_ADDR                  UL(0x50018000)
 116 #define ATA_DMA_BASE_ADDR               UL(0x50020000)
 117 #define SIM1_BASE_ADDR                  UL(0x50024000)
 118 #define SIM2_BASE_ADDR                  UL(0x50028000)
 119 #define UART5_BASE_ADDR                 UL(0x5002C000)
 120 #define TSC_BASE_ADDR                   UL(0x50030000)
 121 #define SSI1_BASE_ADDR                  UL(0x50034000)
 122 #define FEC_BASE_ADDR                   UL(0x50038000)
 123 #define SOC_FEC_BASE                    FEC_BASE_ADDR
 124 #define SPBA_CTRL_BASE_ADDR             UL(0x5003C000)
 125
 126 /*
 127  * AIPS 2
 128  */
 129 #define AIPS2_BASE_ADDR                 UL(0x53F00000)
 130 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
 131 #define CCM_BASE_ADDR                   UL(0x53F80000)
 132 #define GPT4_BASE_ADDR                  UL(0x53F84000)
 133 #define GPT3_BASE_ADDR                  UL(0x53F88000)
 134 #define GPT2_BASE_ADDR                  UL(0x53F8C000)
 135 #define GPT1_BASE_ADDR                  UL(0x53F90000)
 136 #define EPIT1_BASE_ADDR                 UL(0x53F94000)
 137 #define EPIT2_BASE_ADDR                 UL(0x53F98000)
 138 #define GPIO4_BASE_ADDR                 UL(0x53F9C000)
 139 #define PWM2_BASE_ADDR                  UL(0x53FA0000)
 140 #define GPIO3_BASE_ADDR                 UL(0x53FA4000)
 141 #define PWM3_BASE_ADDR                  UL(0x53FA8000)
 142 #define SCC_BASE_ADDR                   UL(0x53FAC000)
 143 #define SCM_BASE_ADDR                   UL(0x53FAE000)
 144 #define SMN_BASE_ADDR                   UL(0x53FAF000)
 145 #define RNGD_BASE_ADDR                  UL(0x53FB0000)
 146 #define MMC_SDHC1_BASE_ADDR             UL(0x53FB4000)
 147 #define MMC_SDHC2_BASE_ADDR             UL(0x53FB8000)
 148 #define ESDHC1_REG_BASE                 MMC_SDHC1_BASE_ADDR
 149 #define LCDC_BASE_ADDR                  UL(0x53FBC000)
 150 #define SLCDC_BASE_ADDR                 UL(0x53FC0000)
 151 #define PWM4_BASE_ADDR                  UL(0x53FC8000)
 152 #define GPIO1_BASE_ADDR                 UL(0x53FCC000)
 153 #define GPIO2_BASE_ADDR                 UL(0x53FD0000)
 154 #define SDMA_BASE_ADDR                  UL(0x53FD4000)
 155 #define WDOG_BASE_ADDR                  UL(0x53FDC000)
 156 #define PWM1_BASE_ADDR                  UL(0x53FE0000)
 157 #define RTIC_BASE_ADDR                  UL(0x53FEC000)
 158 #define IIM_BASE_ADDR                   UL(0x53FF0000)
 159 #define USB_BASE_ADDR                   UL(0x53FF4000)
 160 #define CSI_BASE_ADDR                   UL(0x53FF8000)
 161 #define DRYICE_BASE_ADDR                UL(0x53FFC000)
 162
 163 /*
 164  * ROMPATCH and AVIC
 165  */
 166 #define ROMPATCH_BASE_ADDR              UL(0x60000000)
 167 #define ASIC_BASE_ADDR                  UL(0x68000000)
 168
 169 #define RAM_BASE_ADDR                   UL(0x78000000)
 170
 171 /*
 172  * NAND, SDRAM, WEIM, M3IF, EMI controllers
 173  */
 174 #define EXT_MEM_CTRL_BASE               UL(0xB8000000)
 175 #define ESDCTL_BASE_ADDR                UL(0xB8001000)
 176 #define WEIM_BASE_ADDR                  UL(0xB8002000)
 177 #define WEIM_CTRL_CS0                   WEIM_BASE_ADDR
 178 #define WEIM_CTRL_CS1                   (WEIM_BASE_ADDR + 0x10)
 179 #define WEIM_CTRL_CS2                   (WEIM_BASE_ADDR + 0x20)
 180 #define WEIM_CTRL_CS3                   (WEIM_BASE_ADDR + 0x30)
 181 #define WEIM_CTRL_CS4                   (WEIM_BASE_ADDR + 0x40)
 182 #define WEIM_CTRL_CS5                   (WEIM_BASE_ADDR + 0x50)
 183 #define M3IF_BASE                               UL(0xB8003000)
 184 #define EMI_BASE                                UL(0xB8004000)
 185
 186 #define NFC_BASE                                UL(0xBB000000)
 187 /*
 188  * Memory regions and CS
 189  */
 190 #define CSD0_BASE_ADDR                  UL(0x80000000)
 191 #define CSD1_BASE_ADDR                  UL(0x90000000)
 192 #define CS0_BASE_ADDR                   UL(0xA0000000)
 193 #define CS1_BASE_ADDR                   UL(0xA8000000)
 194 #define CS2_BASE_ADDR                   UL(0xB0000000)
 195 #define CS3_BASE_ADDR                   UL(0xB2000000)
 196 #define CS4_BASE_ADDR                   UL(0xB4000000)
 197 #define CS5_BASE_ADDR                   UL(0xB6000000)
 198
 199 /*
 200  * IRQ Controller Register Definitions.
 201  */
 202 #define ASIC_NIMASK                             REG32_PTR(ASIC_BASE_ADDR + 0x04)
 203 #define ASIC_INTTYPEH                   REG32_PTR(ASIC_BASE_ADDR + 0x18)
 204 #define ASIC_INTTYPEL                   REG32_PTR(ASIC_BASE_ADDR + 0x1C)
 205
 206 /* CCM */
 207 #define CLKCTL_MPCTL                    0x00
 208 #define CLKCTL_UPCTL                    0x04
 209 #define CLKCTL_CCTL                             0x08
 210 #define CLKCTL_CGR0                             0x0C
 211 #define CLKCTL_CGR1                             0x10
 212 #define CLKCTL_CGR2                             0x14
 213 #define CLKCTL_PCDR0                    0x18
 214 #define CLKCTL_PCDR1                    0x1C
 215 #define CLKCTL_PCDR2                    0x20
 216 #define CLKCTL_PCDR3                    0x24
 217 #define CLKCTL_RCSR                             0x28
 218 #define CLKCTL_CRDR                             0x2C
 219 #define CLKCTL_DCVR0                    0x30
 220 #define CLKCTL_DCVR1                    0x34
 221 #define CLKCTL_DCVR2                    0x38
 222 #define CLKCTL_DCVR3                    0x3C
 223 #define CLKCTL_LTR0                             0x40
 224 #define CLKCTL_LTR1                             0x44
 225 #define CLKCTL_LTR2                             0x48
 226 #define CLKCTL_LTR3                             0x4C
 227 #define CLKCTL_LTBR0                    0x50
 228 #define CLKCTL_LTBR1                    0x54
 229 #define CLKCTL_PCMR0                    0x58
 230 #define CLKCTL_PCMR1                    0x5C
 231 #define CLKCTL_PCMR2                    0x60
 232 #define CLKCTL_MCR                              0x64
 233 #define CLKCTL_LPIMR0                   0x68
 234 #define CLKCTL_LPIMR1                   0x6C
 235
 236 #define CRM_CCTL_ARM_SRC                (1 << 14)
 237 #define CRM_CCTL_ARM_OFFSET             30
 238 #define CRM_CCTL_AHB_OFFSET             28
 239
 240 #define SOC_MAC_ADDR_BASE               (IIM_BASE_ADDR + 0x868)
 241
 242 #define FREQ_24MHZ                              24000000
 243 #define PLL_REF_CLK                             FREQ_24MHZ
 244
 245 /*
 246  * FIXME-DALE - Constants verified up to this point.
 247  *                              Offsets and derived constants below should be confirmed.
 248  */
 249
 250 #define CLKMODE_AUTO                    0
 251 #define CLKMODE_CONSUMER                1
 252
 253 /* WEIM - CS0 */
 254 #define CSCRU                                   0x00
 255 #define CSCRL                                   0x04
 256 #define CSCRA                                   0x08
 257
 258 #define CHIP_REV_1_0                    0x0              /* PASS 1.0 */
 259 #define CHIP_REV_1_1                    0x1              /* PASS 1.1 */
 260 #define CHIP_REV_2_0                    0x2              /* PASS 2.0 */
 261 #define CHIP_LATEST                             CHIP_REV_1_1
 262
 263 #define IIM_STAT_OFF                    0x00
 264 #define IIM_STAT_BUSY                   (1 << 7)
 265 #define IIM_STAT_PRGD                   (1 << 1)
 266 #define IIM_STAT_SNSD                   (1 << 0)
 267 #define IIM_STATM_OFF                   0x04
 268 #define IIM_ERR_OFF                             0x08
 269 #define IIM_ERR_PRGE                    (1 << 7)
 270 #define IIM_ERR_WPE                             (1 << 6)
 271 #define IIM_ERR_OPE                             (1 << 5)
 272 #define IIM_ERR_RPE                             (1 << 4)
 273 #define IIM_ERR_WLRE                    (1 << 3)
 274 #define IIM_ERR_SNSE                    (1 << 2)
 275 #define IIM_ERR_PARITYE                 (1 << 1)
 276 #define IIM_EMASK_OFF                   0x0C
 277 #define IIM_FCTL_OFF                    0x10
 278 #define IIM_UA_OFF                              0x14
 279 #define IIM_LA_OFF                              0x18
 280 #define IIM_SDAT_OFF                    0x1C
 281 #define IIM_PREV_OFF                    0x20
 282 #define IIM_SREV_OFF                    0x24
 283 #define IIM_PREG_P_OFF                  0x28
 284 #define IIM_SCS0_OFF                    0x2C
 285 #define IIM_SCS1_OFF                    0x30
 286 #define IIM_SCS2_OFF                    0x34
 287 #define IIM_SCS3_OFF                    0x38
 288
 289 #define EPIT_BASE_ADDR                  EPIT1_BASE_ADDR
 290 #define EPITCR                                  0x00
 291 #define EPITSR                                  0x04
 292 #define EPITLR                                  0x08
 293 #define EPITCMPR                                0x0C
 294 #define EPITCNR                                 0x10
 295
 296 #define GPT_BASE_ADDR                   GPT1_BASE_ADDR
 297 #define GPTCR                                   0x00
 298 #define GPTPR                                   0x04
 299 #define GPTSR                                   0x08
 300 #define GPTIR                                   0x0C
 301 #define GPTOCR1                                 0x10
 302 #define GPTOCR2                                 0x14
 303 #define GPTOCR3                                 0x18
 304 #define GPTICR1                                 0x1C
 305 #define GPTICR2                                 0x20
 306 #define GPTCNT                                  0x24
 307
 308 /* ESDCTL */
 309 #define ESDCTL_ESDCTL0                  0x00
 310 #define ESDCTL_ESDCFG0                  0x04
 311 #define ESDCTL_ESDCTL1                  0x08
 312 #define ESDCTL_ESDCFG1                  0x0C
 313 #define ESDCTL_ESDMISC                  0x10
 314
 315 /* DRYICE */
 316 #define DRYICE_DTCMR                    0x00
 317 #define DRYICE_DTCLR                    0x04
 318 #define DRYICE_DCAMR                    0x08
 319 #define DRYICE_DCALR                    0x0C
 320 #define DRYICE_DCR                              0x10
 321 #define DRYICE_DSR                              0x14
 322 #define DRYICE_DIER                             0x18
 323 #define DRYICE_DMCR                             0x1C
 324 #define DRYICE_DKSR                             0x20
 325 #define DRYICE_DKCR                             0x24
 326 #define DRYICE_DTCR                             0x28
 327 #define DRYICE_DACR                             0x2C
 328 #define DRYICE_DGPR                             0x3C
 329 #define DRYICE_DPKR0                    0x40
 330 #define DRYICE_DPKR1                    0x44
 331 #define DRYICE_DPKR2                    0x48
 332 #define DRYICE_DPKR3                    0x4C
 333 #define DRYICE_DPKR4                    0x50
 334 #define DRYICE_DPKR5                    0x54
 335 #define DRYICE_DPKR6                    0x58
 336 #define DRYICE_DPKR7                    0x5C
 337 #define DRYICE_DRKR0                    0x60
 338 #define DRYICE_DRKR1                    0x64
 339 #define DRYICE_DRKR2                    0x68
 340 #define DRYICE_DRKR3                    0x6C
 341 #define DRYICE_DRKR4                    0x70
 342 #define DRYICE_DRKR5                    0x74
 343 #define DRYICE_DRKR6                    0x78
 344 #define DRYICE_DRKR7                    0x7C
 345
 346 /* GPIO */
 347 #define GPIO_DR                                 0x00
 348 #define GPIO_GDIR                               0x04
 349 #define GPIO_PSR0                               0x08
 350 #define GPIO_ICR1                               0x0C
 351 #define GPIO_ICR2                               0x10
 352 #define GPIO_IMR                                0x14
 353 #define GPIO_ISR                                0x18
 354 #define GPIO_EDGE_SEL                   0x1C
 355
 356
 357 #if (PLL_REF_CLK != 24000000)
 358 #error Wrong PLL reference clock! The following macros will not work.
 359 #endif
 360
 361 /* Assuming 24MHz input clock */
 362 /*                                                        PD                     MFD                      MFI              MFN */
 363 #define MPCTL_PARAM_399         (((1-1) << 26) + ((16-1) << 16) + (8 << 10) + (5 << 0))
 364 #define MPCTL_PARAM_532         ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11 << 10) + (1 << 0))
 365 #define MPCTL_PARAM_665         (((1-1) << 26) + ((48-1) << 16) + (13 << 10) + (41 << 0))
 366
 367 /* UPCTL                                          PD                     MFD                      MFI              MFN */
 368 #define UPCTL_PARAM_300         (((1-1) << 26) + ((4-1) << 16) + (6     << 10) + (1 << 0))
 369
 370 #define NFC_V1_1
 371
 372 #define NAND_REG_BASE                                   (NFC_BASE + 0x1E00)
 373 #define NFC_BUFSIZE_REG_OFF                             0x00
 374 #define RAM_BUFFER_ADDRESS_REG_OFF              0x04
 375 #define NAND_FLASH_ADD_REG_OFF                  0x06
 376 #define NAND_FLASH_CMD_REG_OFF                  0x08
 377 #define NFC_CONFIGURATION_REG_OFF               0x0A
 378 #define ECC_STATUS_RESULT_REG_OFF               0x0C
 379 #define ECC_RSLT_MAIN_AREA_REG_OFF              0x0E
 380 #define ECC_RSLT_SPARE_AREA_REG_OFF             0x10
 381 #define NF_WR_PROT_REG_OFF                              0x12
 382 #define NAND_FLASH_WR_PR_ST_REG_OFF             0x18
 383 #define NAND_FLASH_CONFIG1_REG_OFF              0x1A
 384 #define NAND_FLASH_CONFIG2_REG_OFF              0x1C
 385 #define UNLOCK_START_BLK_ADD_REG_OFF    0x20
 386 #define UNLOCK_END_BLK_ADD_REG_OFF              0x22
 387 #define RAM_BUFFER_ADDRESS_RBA_3                0x3
 388 #define NFC_BUFSIZE_1KB                                 0x0
 389 #define NFC_BUFSIZE_2KB                                 0x1
 390 #define NFC_CONFIGURATION_UNLOCKED              0x2
 391 #define ECC_STATUS_RESULT_NO_ERR                0x0
 392 #define ECC_STATUS_RESULT_1BIT_ERR              0x1
 393 #define ECC_STATUS_RESULT_2BIT_ERR              0x2
 394 #define NF_WR_PROT_UNLOCK                               0x4
 395 #define NAND_FLASH_CONFIG1_FORCE_CE             (1 << 7)
 396 #define NAND_FLASH_CONFIG1_RST                  (1 << 6)
 397 #define NAND_FLASH_CONFIG1_BIG                  (1 << 5)
 398 #define NAND_FLASH_CONFIG1_INT_MSK              (1 << 4)
 399 #define NAND_FLASH_CONFIG1_ECC_EN               (1 << 3)
 400 #define NAND_FLASH_CONFIG1_SP_EN                (1 << 2)
 401 #define NAND_FLASH_CONFIG2_INT_DONE             (1 << 15)
 402 #define NAND_FLASH_CONFIG2_FDO_PAGE             (0 << 3)
 403 #define NAND_FLASH_CONFIG2_FDO_ID               (2 << 3)
 404 #define NAND_FLASH_CONFIG2_FDO_STATUS   (4 << 3)
 405 #define NAND_FLASH_CONFIG2_FDI_EN               (1 << 2)
 406 #define NAND_FLASH_CONFIG2_FADD_EN              (1 << 1)
 407 #define NAND_FLASH_CONFIG2_FCMD_EN              (1 << 0)
 408 #define FDO_PAGE_SPARE_VAL                              0x8
 409 #define NAND_BUF_NUM                                    8
 410
 411 #define MXC_NAND_BASE_DUMMY                             0x00000000
 412 #define MXC_MMC_BASE_DUMMY                              0x00000000
 413 #define NOR_FLASH_BOOT                                  0
 414 #define NAND_FLASH_BOOT                                 0x10000000
 415 #define SDRAM_NON_FLASH_BOOT                    0x20000000
 416 #define MMC_FLASH_BOOT                                  0x40000000
 417 #define MXCBOOT_FLAG_REG                                (CSI_BASE_ADDR + 0x28)  // use CSIDMASA-FB1
 418 #define MXCFIS_NOTHING                                  0x00000000
 419 #define MXCFIS_NAND                                             0x10000000
 420 #define MXCFIS_NOR                                              0x20000000
 421 #define MXCFIS_MMC                                              0x40000000
 422 #define MXCFIS_FLAG_REG                                 (CSI_BASE_ADDR + 0x2C)  // use CSIDMASA-FB2
 423
 424 #define IS_BOOTING_FROM_NAND()                  (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
 425 #define IS_BOOTING_FROM_NOR()                   (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
 426 #define IS_BOOTING_FROM_SDRAM()                 (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
 427 #define IS_BOOTING_FROM_MMC()                   (readl(MXCBOOT_FLAG_REG) == MMC_FLASH_BOOT)
 428
 429 #ifndef MXCFLASH_SELECT_NAND
 430 #define IS_FIS_FROM_NAND()                              0
 431 #else
 432 #define IS_FIS_FROM_NAND()                              (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
 433 #endif
 434
 435 #ifndef MXCFLASH_SELECT_MMC
 436 #define IS_FIS_FROM_MMC()                               0
 437 #else
 438 #define IS_FIS_FROM_MMC()                               (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
 439 #endif
 440
 441 #ifndef MXCFLASH_SELECT_NOR
 442 #define IS_FIS_FROM_NOR()                               0
 443 #else
 444 #define IS_FIS_FROM_NOR()                               (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
 445 #endif
 446
 447 #define MXC_ASSERT_NOR_BOOT()                   writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
 448 #define MXC_ASSERT_NAND_BOOT()                  writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
 449 #define MXC_ASSERT_MMC_BOOT()                   writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
 450
 451 /*
 452  * This macro is used to get certain bit field from a number
 453  */
 454 #define MXC_GET_FIELD(val, len, sh)                      ((val >> sh) & ((1 << len) - 1))
 455
 456 /*
 457  * This macro is used to set certain bit field inside a number
 458  */
 459 #define MXC_SET_FIELD(val, len, sh, nval)        ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
 460
 461 #define UART_WIDTH_32             /* internal UART is 32bit access only */
 462
 463 #if !defined(__ASSEMBLER__)
 464 void cyg_hal_plf_serial_init(void);
 465 void cyg_hal_plf_serial_stop(void);
 466 void hal_delay_us(unsigned int usecs);
 467 #define HAL_DELAY_US(n)         hal_delay_us(n)
 468
 469 enum plls {
 470                 MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL,
 471                 USB_PLL = CCM_BASE_ADDR + CLKCTL_UPCTL,
 472 };
 473
 474 enum main_clocks {
 475                 CPU_CLK,
 476                 AHB_CLK,
 477                 IPG_CLK,
 478                 IPG_PER_CLK, // not there on MX25 but simulated for compatibility
 479 };
 480
 481 enum peri_clocks {
 482                 PER_UART_CLK,
 483                 SPI1_CLK = CSPI1_BASE_ADDR,
 484                 SPI2_CLK = CSPI2_BASE_ADDR,
 485 };
 486
 487 unsigned int pll_clock(enum plls pll);
 488
 489 unsigned int get_main_clock(enum main_clocks clk);
 490
 491 unsigned int get_peri_clock(enum peri_clocks clk);
 492
 493 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
 494
 495 #endif //#if !defined(__ASSEMBLER__)
 496
 497 #define HAL_MMU_OFF()                                                                                           \
 498 CYG_MACRO_START                                                                                                         \
 499         asm volatile (                                                                                                  \
 500                 "1: "                                                                                                           \
 501                 "mrc p15, 0, r15, c7, c14, 3;"   /*test clean and inval*/       \
 502                 "bne 1b;"                                                                                                       \
 503                 "mov r0, #0;"                                                                                           \
 504                 "mcr p15,0,r0,c7,c10,4;"   /*drain write buffer*/                       \
 505                 "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */                        \
 506                 "mrc p15,0,r0,c1,c0,0;" /* read c1 */                                           \
 507                 "bic r0,r0,#0x7;" /* disable DCache and MMU */                          \
 508                 "bic r0,r0,#0x1000;" /* disable ICache */                                       \
 509                 "mcr p15,0,r0,c1,c0,0;" /*      */                                                              \
 510                 "nop;" /* flush i+d-TLBs */                                                                     \
 511                 "nop;" /* flush i+d-TLBs */                                                                     \
 512                 "nop;" /* flush i+d-TLBs */                                                                     \
 513                 :                                                                                                                       \
 514                 :                                                                                                                       \
 515                 : "r0","memory" /* clobber list */);                                            \
 516 CYG_MACRO_END
 517
 518 #endif /* __HAL_SOC_H__ */