packages/hal/arm/mx25/var/v2_0/include/hal_soc.h

   1 //==========================================================================
   2 //
   3 //      hal_soc.h
   4 //
   5 //      SoC chip definitions
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 // Copyright (C) 2002 Gary Thomas
  13 //
  14 // eCos is free software; you can redistribute it and/or modify it under
  15 // the terms of the GNU General Public License as published by the Free
  16 // Software Foundation; either version 2 or (at your option) any later version.
  17 //
  18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  21 // for more details.
  22 //
  23 // You should have received a copy of the GNU General Public License along
  24 // with eCos; if not, write to the Free Software Foundation, Inc.,
  25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  26 //
  27 // As a special exception, if other files instantiate templates or use macros
  28 // or inline functions from this file, or you compile this file and link it
  29 // with other works to produce a work based on this file, this file does not
  30 // by itself cause the resulting work to be covered by the GNU General Public
  31 // License. However the source code for this file must still be made available
  32 // in accordance with section (3) of the GNU General Public License.
  33 //
  34 // This exception does not invalidate any other reasons why a work based on
  35 // this file might be covered by the GNU General Public License.
  36 //
  37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  38 // at http://sources.redhat.com/ecos/ecos-license/
  39 // -------------------------------------------
  40 //####ECOSGPLCOPYRIGHTEND####
  41 //========================================================================*/
  42
  43 #ifndef __HAL_SOC_H__
  44 #define __HAL_SOC_H__
  45
  46 #ifdef __ASSEMBLER__
  47
  48 #define REG8_VAL(a)          (a)
  49 #define REG16_VAL(a)         (a)
  50 #define REG32_VAL(a)         (a)
  51
  52 #define REG8_PTR(a)          (a)
  53 #define REG16_PTR(a)         (a)
  54 #define REG32_PTR(a)         (a)
  55
  56 #else /* __ASSEMBLER__ */
  57
  58 extern char HAL_PLATFORM_EXTRA[];
  59 #define REG8_VAL(a)          ((unsigned char)(a))
  60 #define REG16_VAL(a)         ((unsigned short)(a))
  61 #define REG32_VAL(a)         ((unsigned int)(a))
  62
  63 #define REG8_PTR(a)          ((volatile unsigned char *)(a))
  64 #define REG16_PTR(a)         ((volatile unsigned short *)(a))
  65 #define REG32_PTR(a)         ((volatile unsigned int *)(a))
  66 #define readb(a)             (*(volatile unsigned char *)(a))
  67 #define readw(a)             (*(volatile unsigned short *)(a))
  68 #define readl(a)             (*(volatile unsigned int *)(a))
  69 #define writeb(v,a)          (*(volatile unsigned char *)(a) = (v))
  70 #define writew(v,a)          (*(volatile unsigned short *)(a) = (v))
  71 #define writel(v,a)          (*(volatile unsigned int *)(a) = (v))
  72
  73 #endif /* __ASSEMBLER__ */
  74
  75 /*
  76  * Default Memory Layout Definitions
  77  */
  78
  79 /*
  80  * AIPS 1
  81  */
  82 #define AIPS1_BASE_ADDR         0x43F00000
  83 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
  84 #define MAX_BASE_ADDR           0x43F04000
  85 #define CLKCTL_BASE_ADDR        0x43F08000
  86 #define ETB_SLOT4_BASE_ADDR     0x43F0C000
  87 #define ETB_SLOT5_BASE_ADDR     0x43F1000l
  88 #define ECT_CTIO_BASE_ADDR      0x43F18000
  89 #define I2C_BASE_ADDR           0x43F80000
  90 #define I2C3_BASE_ADDR          0x43F84000
  91 #define CAN1_BASE_ADDR          0x43F88000
  92 #define CAN2_BASE_ADDR          0x43F8C000
  93 #define UART1_BASE_ADDR         0x43F90000
  94 #define UART2_BASE_ADDR         0x43F94000
  95 #define I2C2_BASE_ADDR          0x43F98000
  96 #define OWIRE_BASE_ADDR         0x43F9C000
  97 #define CSPI1_BASE_ADDR         0x43FA4000
  98 #define KPP_BASE_ADDR           0x43FA8000
  99 #define IOMUXC_BASE_ADDR        0x43FAC000
 100 #define AUDMUX_BASE_ADDR        0x43FB0000
 101 #define ECT_IP1_BASE_ADDR       0x43FB8000
 102 #define ECT_IP2_BASE_ADDR       0x43FBC000
 103
 104 /*
 105  * SPBA
 106  */
 107 #define SPBA_BASE_ADDR          0x50000000
 108 #define CSPI3_BASE_ADDR         0x50040000
 109 #define UART4_BASE_ADDR         0x50008000
 110 #define UART3_BASE_ADDR         0x5000C000
 111 #define CSPI2_BASE_ADDR         0x50010000
 112 #define SSI2_BASE_ADDR          0x50014000
 113 #define ESAI_BASE_ADDR          0x50018000
 114 #define ATA_DMA_BASE_ADDR       0x50020000
 115 #define SIM1_BASE_ADDR          0x50024000
 116 #define SIM2_BASE_ADDR          0x50028000
 117 #define UART5_BASE_ADDR         0x5002C000
 118 #define TSC_BASE_ADDR           0x50030000
 119 #define SSI1_BASE_ADDR          0x50034000
 120 #define FEC_BASE_ADDR           0x50038000
 121 #define SOC_FEC_BASE            FEC_BASE_ADDR
 122 #define SPBA_CTRL_BASE_ADDR     0x5003C000
 123
 124 /*
 125  * AIPS 2
 126  */
 127 #define AIPS2_BASE_ADDR         0x53F00000
 128 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
 129 #define CCM_BASE_ADDR           0x53F80000
 130 #define GPT4_BASE_ADDR          0x53F84000
 131 #define GPT3_BASE_ADDR          0x53F88000
 132 #define GPT2_BASE_ADDR          0x53F8C000
 133 #define GPT1_BASE_ADDR          0x53F90000
 134 #define EPIT1_BASE_ADDR         0x53F94000
 135 #define EPIT2_BASE_ADDR         0x53F98000
 136 #define GPIO4_BASE_ADDR         0x53F9C000
 137 #define PWM2_BASE_ADDR          0x53FA0000
 138 #define GPIO3_BASE_ADDR         0x53FA4000
 139 #define PWM3_BASE_ADDR          0x53FA8000
 140 #define SCC_BASE_ADDR           0x53FAC000
 141 #define SCM_BASE_ADDR           0x53FAE000
 142 #define SMN_BASE_ADDR           0x53FAF000
 143 #define RNGD_BASE_ADDR          0x53FB0000
 144 #define MMC_SDHC1_BASE_ADDR     0x53FB4000
 145 #define MMC_SDHC2_BASE_ADDR     0x53FB8000
 146 #define ESDHC1_REG_BASE         MMC_SDHC1_BASE_ADDR
 147 #define LCDC_BASE_ADDR          0x53FBC000
 148 #define SLCDC_BASE_ADDR         0x53FC0000
 149 #define PWM4_BASE_ADDR          0x53FC8000
 150 #define GPIO1_BASE_ADDR         0x53FCC000
 151 #define GPIO2_BASE_ADDR         0x53FD0000
 152 #define SDMA_BASE_ADDR          0x53FD4000
 153 #define WDOG_BASE_ADDR          0x53FDC000
 154 #define PWM1_BASE_ADDR          0x53FE0000
 155 #define RTIC_BASE_ADDR          0x53FEC000
 156 #define IIM_BASE_ADDR           0x53FF0000
 157 #define USB_BASE_ADDR           0x53FF4000
 158 #define CSI_BASE_ADDR           0x53FF8000
 159 #define DRYICE_BASE_ADDR        0x53FFC000
 160
 161 /*
 162  * ROMPATCH and AVIC
 163  */
 164 #define ROMPATCH_BASE_ADDR      0x60000000
 165 #define ASIC_BASE_ADDR          0x68000000
 166
 167 #define RAM_BASE_ADDR           0x78000000
 168
 169 /*
 170  * NAND, SDRAM, WEIM, M3IF, EMI controllers
 171  */
 172 #define EXT_MEM_CTRL_BASE       0xB8000000
 173 #define ESDCTL_BASE_ADDR        0xB8001000
 174 #define WEIM_BASE_ADDR          0xB8002000
 175 #define WEIM_CTRL_CS0           WEIM_BASE_ADDR
 176 #define WEIM_CTRL_CS1           (WEIM_BASE_ADDR + 0x10)
 177 #define WEIM_CTRL_CS2           (WEIM_BASE_ADDR + 0x20)
 178 #define WEIM_CTRL_CS3           (WEIM_BASE_ADDR + 0x30)
 179 #define WEIM_CTRL_CS4           (WEIM_BASE_ADDR + 0x40)
 180 #define WEIM_CTRL_CS5           (WEIM_BASE_ADDR + 0x50)
 181 #define M3IF_BASE               0xB8003000
 182 #define EMI_BASE                0xB8004000
 183
 184 #define NFC_BASE                0xBB000000
 185 /*
 186  * Memory regions and CS
 187  */
 188 #define CSD0_BASE_ADDR          0x80000000
 189 #define CSD1_BASE_ADDR          0x90000000
 190 #define CS0_BASE_ADDR           0xA0000000
 191 #define CS1_BASE_ADDR           0xA8000000
 192 #define CS2_BASE_ADDR           0xB0000000
 193 #define CS3_BASE_ADDR           0xB2000000
 194 #define CS4_BASE_ADDR           0xB4000000
 195 #define CS5_BASE_ADDR           0xB6000000
 196
 197 /*
 198  * IRQ Controller Register Definitions.
 199  */
 200 #define ASIC_NIMASK                     REG32_PTR(ASIC_BASE_ADDR + (0x04))
 201 #define ASIC_INTTYPEH                   REG32_PTR(ASIC_BASE_ADDR + (0x18))
 202 #define ASIC_INTTYPEL                   REG32_PTR(ASIC_BASE_ADDR + (0x1C))
 203
 204 /* CCM */
 205 #define CLKCTL_MPCTL                    0x00
 206 #define CLKCTL_UPCTL                    0x04
 207 #define CLKCTL_CCTL                     0x08
 208 #define CLKCTL_CGR0                     0x0C
 209 #define CLKCTL_CGR1                     0x10
 210 #define CLKCTL_CGR2                     0x14
 211 #define CLKCTL_PCDR0                    0x18
 212 #define CLKCTL_PCDR1                    0x1C
 213 #define CLKCTL_PCDR2                    0x20
 214 #define CLKCTL_PCDR3                    0x24
 215 #define CLKCTL_RCSR                     0x28
 216 #define CLKCTL_CRDR                     0x2C
 217 #define CLKCTL_DCVR0                    0x30
 218 #define CLKCTL_DCVR1                    0x34
 219 #define CLKCTL_DCVR2                    0x38
 220 #define CLKCTL_DCVR3                    0x3C
 221 #define CLKCTL_LTR0                     0x40
 222 #define CLKCTL_LTR1                     0x44
 223 #define CLKCTL_LTR2                     0x48
 224 #define CLKCTL_LTR3                     0x4C
 225 #define CLKCTL_LTBR0                    0x50
 226 #define CLKCTL_LTBR1                    0x54
 227 #define CLKCTL_PCMR0                    0x58
 228 #define CLKCTL_PCMR1                    0x5C
 229 #define CLKCTL_PCMR2                    0x60
 230 #define CLKCTL_MCR                      0x64
 231 #define CLKCTL_LPIMR0                   0x68
 232 #define CLKCTL_LPIMR1                   0x6C
 233
 234 #define CRM_CCTL_ARM_SRC                (1 << 14)
 235 #define CRM_CCTL_AHB_OFFSET             28
 236
 237
 238 #define FREQ_24MHZ                      24000000
 239 #define PLL_REF_CLK                     FREQ_24MHZ
 240
 241 /*
 242  * FIXME-DALE - Constants verified up to this point.
 243  *              Offsets and derived constants below should be confirmed.
 244  */
 245
 246 #define CLKMODE_AUTO            0
 247 #define CLKMODE_CONSUMER        1
 248
 249 /* WEIM - CS0 */
 250 #define CSCRU                           0x00
 251 #define CSCRL                           0x04
 252 #define CSCRA                           0x08
 253
 254 #define CHIP_REV_1_0            0x0      /* PASS 1.0 */
 255 #define CHIP_REV_1_1            0x1      /* PASS 1.1 */
 256 #define CHIP_REV_2_0            0x2      /* PASS 2.0 */
 257 #define CHIP_LATEST             CHIP_REV_1_1
 258
 259 #define IIM_STAT_OFF            0x00
 260 #define IIM_STAT_BUSY           (1 << 7)
 261 #define IIM_STAT_PRGD           (1 << 1)
 262 #define IIM_STAT_SNSD           (1 << 0)
 263 #define IIM_STATM_OFF           0x04
 264 #define IIM_ERR_OFF             0x08
 265 #define IIM_ERR_PRGE            (1 << 7)
 266 #define IIM_ERR_WPE             (1 << 6)
 267 #define IIM_ERR_OPE             (1 << 5)
 268 #define IIM_ERR_RPE             (1 << 4)
 269 #define IIM_ERR_WLRE            (1 << 3)
 270 #define IIM_ERR_SNSE            (1 << 2)
 271 #define IIM_ERR_PARITYE         (1 << 1)
 272 #define IIM_EMASK_OFF           0x0C
 273 #define IIM_FCTL_OFF            0x10
 274 #define IIM_UA_OFF              0x14
 275 #define IIM_LA_OFF              0x18
 276 #define IIM_SDAT_OFF            0x1C
 277 #define IIM_PREV_OFF            0x20
 278 #define IIM_SREV_OFF            0x24
 279 #define IIM_PREG_P_OFF          0x28
 280 #define IIM_SCS0_OFF            0x2C
 281 #define IIM_SCS1_OFF            0x30
 282 #define IIM_SCS2_OFF            0x34
 283 #define IIM_SCS3_OFF            0x38
 284
 285 #define EPIT_BASE_ADDR          EPIT1_BASE_ADDR
 286 #define EPITCR                  0x00
 287 #define EPITSR                  0x04
 288 #define EPITLR                  0x08
 289 #define EPITCMPR                0x0C
 290 #define EPITCNR                 0x10
 291
 292 #define GPT_BASE_ADDR           GPT1_BASE_ADDR
 293 #define GPTCR                   0x00
 294 #define GPTPR                   0x04
 295 #define GPTSR                   0x08
 296 #define GPTIR                   0x0C
 297 #define GPTOCR1                 0x10
 298 #define GPTOCR2                 0x14
 299 #define GPTOCR3                 0x18
 300 #define GPTICR1                 0x1C
 301 #define GPTICR2                 0x20
 302 #define GPTCNT                  0x24
 303
 304 /* ESDCTL */
 305 #define ESDCTL_ESDCTL0                  0x00
 306 #define ESDCTL_ESDCFG0                  0x04
 307 #define ESDCTL_ESDCTL1                  0x08
 308 #define ESDCTL_ESDCFG1                  0x0C
 309 #define ESDCTL_ESDMISC                  0x10
 310
 311 /* DRYICE */
 312 #define DRYICE_DTCMR            0x00
 313 #define DRYICE_DTCLR            0x04
 314 #define DRYICE_DCAMR            0x08
 315 #define DRYICE_DCALR            0x0C
 316 #define DRYICE_DCR              0x10
 317 #define DRYICE_DSR              0x14
 318 #define DRYICE_DIER             0x18
 319 #define DRYICE_DMCR             0x1C
 320 #define DRYICE_DKSR             0x20
 321 #define DRYICE_DKCR             0x24
 322 #define DRYICE_DTCR             0x28
 323 #define DRYICE_DACR             0x2C
 324 #define DRYICE_DGPR             0x3C
 325 #define DRYICE_DPKR0            0x40
 326 #define DRYICE_DPKR1            0x44
 327 #define DRYICE_DPKR2            0x48
 328 #define DRYICE_DPKR3            0x4C
 329 #define DRYICE_DPKR4            0x50
 330 #define DRYICE_DPKR5            0x54
 331 #define DRYICE_DPKR6            0x58
 332 #define DRYICE_DPKR7            0x5C
 333 #define DRYICE_DRKR0            0x60
 334 #define DRYICE_DRKR1            0x64
 335 #define DRYICE_DRKR2            0x68
 336 #define DRYICE_DRKR3            0x6C
 337 #define DRYICE_DRKR4            0x70
 338 #define DRYICE_DRKR5            0x74
 339 #define DRYICE_DRKR6            0x78
 340 #define DRYICE_DRKR7            0x7C
 341
 342 /* GPIO */
 343 #define GPIO_DR                 0x00
 344 #define GPIO_GDIR               0x04
 345 #define GPIO_PSR0               0x08
 346 #define GPIO_ICR1               0x0C
 347 #define GPIO_ICR2               0x10
 348 #define GPIO_IMR                0x14
 349 #define GPIO_ISR                0x18
 350 #define GPIO_EDGE_SEL           0x1C
 351
 352
 353 #if (PLL_REF_CLK != 24000000)
 354 #error Wrong PLL reference clock! The following macros will not work.
 355 #endif
 356
 357 /* Assuming 24MHz input clock */
 358 /*                            PD             MFD              MFI          MFN */
 359 #define MPCTL_PARAM_399     (((1-1) << 26) + ((16-1) << 16) + (8  << 10) + (5 << 0))
 360 #define MPCTL_PARAM_532     ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11  << 10) + (1 << 0))
 361 #define MPCTL_PARAM_665     (((1-1) << 26) + ((48-1) << 16) + (13  << 10) + (41 << 0))
 362
 363 /* UPCTL                      PD             MFD              MFI          MFN */
 364 #define UPCTL_PARAM_300     (((1-1) << 26) + ((4-1) << 16) + (6  << 10) + (1  << 0))
 365
 366 #define NFC_V1_1
 367
 368 #define NAND_REG_BASE                   (NFC_BASE + 0x1E00)
 369 #define NFC_BUFSIZE_REG_OFF             (0 + 0x00)
 370 #define RAM_BUFFER_ADDRESS_REG_OFF      (0 + 0x04)
 371 #define NAND_FLASH_ADD_REG_OFF          (0 + 0x06)
 372 #define NAND_FLASH_CMD_REG_OFF          (0 + 0x08)
 373 #define NFC_CONFIGURATION_REG_OFF       (0 + 0x0A)
 374 #define ECC_STATUS_RESULT_REG_OFF       (0 + 0x0C)
 375 #define ECC_RSLT_MAIN_AREA_REG_OFF      (0 + 0x0E)
 376 #define ECC_RSLT_SPARE_AREA_REG_OFF     (0 + 0x10)
 377 #define NF_WR_PROT_REG_OFF              (0 + 0x12)
 378 #define NAND_FLASH_WR_PR_ST_REG_OFF     (0 + 0x18)
 379 #define NAND_FLASH_CONFIG1_REG_OFF      (0 + 0x1A)
 380 #define NAND_FLASH_CONFIG2_REG_OFF      (0 + 0x1C)
 381 #define UNLOCK_START_BLK_ADD_REG_OFF    (0 + 0x20)
 382 #define UNLOCK_END_BLK_ADD_REG_OFF      (0 + 0x22)
 383 #define RAM_BUFFER_ADDRESS_RBA_3        0x3
 384 #define NFC_BUFSIZE_1KB                 0x0
 385 #define NFC_BUFSIZE_2KB                 0x1
 386 #define NFC_CONFIGURATION_UNLOCKED      0x2
 387 #define ECC_STATUS_RESULT_NO_ERR        0x0
 388 #define ECC_STATUS_RESULT_1BIT_ERR      0x1
 389 #define ECC_STATUS_RESULT_2BIT_ERR      0x2
 390 #define NF_WR_PROT_UNLOCK               0x4
 391 #define NAND_FLASH_CONFIG1_FORCE_CE     (1 << 7)
 392 #define NAND_FLASH_CONFIG1_RST          (1 << 6)
 393 #define NAND_FLASH_CONFIG1_BIG          (1 << 5)
 394 #define NAND_FLASH_CONFIG1_INT_MSK      (1 << 4)
 395 #define NAND_FLASH_CONFIG1_ECC_EN       (1 << 3)
 396 #define NAND_FLASH_CONFIG1_SP_EN        (1 << 2)
 397 #define NAND_FLASH_CONFIG2_INT_DONE     (1 << 15)
 398 #define NAND_FLASH_CONFIG2_FDO_PAGE     (0 << 3)
 399 #define NAND_FLASH_CONFIG2_FDO_ID       (2 << 3)
 400 #define NAND_FLASH_CONFIG2_FDO_STATUS   (4 << 3)
 401 #define NAND_FLASH_CONFIG2_FDI_EN       (1 << 2)
 402 #define NAND_FLASH_CONFIG2_FADD_EN      (1 << 1)
 403 #define NAND_FLASH_CONFIG2_FCMD_EN      (1 << 0)
 404 #define FDO_PAGE_SPARE_VAL              0x8
 405 #define NAND_BUF_NUM    8
 406
 407 #define MXC_NAND_BASE_DUMMY             0x00000000
 408 #define MXC_MMC_BASE_DUMMY              0x00000000
 409 #define NOR_FLASH_BOOT                  0
 410 #define NAND_FLASH_BOOT                 0x10000000
 411 #define SDRAM_NON_FLASH_BOOT            0x20000000
 412 #define MMC_FLASH_BOOT                  0x40000000
 413 #define MXCBOOT_FLAG_REG                (CSI_BASE_ADDR + 0x28)  // use CSIDMASA-FB1
 414 #define MXCFIS_NOTHING                  0x00000000
 415 #define MXCFIS_NAND                     0x10000000
 416 #define MXCFIS_NOR                      0x20000000
 417 #define MXCFIS_MMC                      0x40000000
 418 #define MXCFIS_FLAG_REG                 (CSI_BASE_ADDR + 0x2C)  // use CSIDMASA-FB2
 419
 420 #define IS_BOOTING_FROM_NAND()          (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
 421 #define IS_BOOTING_FROM_NOR()           (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
 422 #define IS_BOOTING_FROM_SDRAM()         (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
 423 #define IS_BOOTING_FROM_MMC()           (readl(MXCBOOT_FLAG_REG) == MMC_FLASH_BOOT)
 424
 425 #ifndef MXCFLASH_SELECT_NAND
 426 #define IS_FIS_FROM_NAND()              0
 427 #else
 428 #define IS_FIS_FROM_NAND()              (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
 429 #endif
 430
 431 #ifndef MXCFLASH_SELECT_MMC
 432 #define IS_FIS_FROM_MMC()               0
 433 #else
 434 #define IS_FIS_FROM_MMC()               (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
 435 #endif
 436
 437 #ifndef MXCFLASH_SELECT_NOR
 438 #define IS_FIS_FROM_NOR()               0
 439 #else
 440 #define IS_FIS_FROM_NOR()               (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
 441 #endif
 442
 443 #define MXC_ASSERT_NOR_BOOT()           writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
 444 #define MXC_ASSERT_NAND_BOOT()          writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
 445 #define MXC_ASSERT_MMC_BOOT()           writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
 446
 447 /*
 448  * This macro is used to get certain bit field from a number
 449  */
 450 #define MXC_GET_FIELD(val, len, sh)          ((val >> sh) & ((1 << len) - 1))
 451
 452 /*
 453  * This macro is used to set certain bit field inside a number
 454  */
 455 #define MXC_SET_FIELD(val, len, sh, nval)    ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
 456
 457 #define UART_WIDTH_32         /* internal UART is 32bit access only */
 458
 459 #if !defined(__ASSEMBLER__)
 460 void cyg_hal_plf_serial_init(void);
 461 void cyg_hal_plf_serial_stop(void);
 462 void hal_delay_us(unsigned int usecs);
 463 #define HAL_DELAY_US(n)     hal_delay_us(n)
 464
 465 enum plls {
 466         MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL,
 467         USB_PLL = CCM_BASE_ADDR + CLKCTL_UPCTL,
 468 };
 469
 470 enum main_clocks {
 471         CPU_CLK,
 472         AHB_CLK,
 473         IPG_CLK,
 474         IPG_PER_CLK, // not there on MX25 but simulated for compatibility
 475 };
 476
 477 enum peri_clocks {
 478         PER_UART_CLK,
 479         SPI1_CLK = CSPI1_BASE_ADDR,
 480         SPI2_CLK = CSPI2_BASE_ADDR,
 481 };
 482
 483 unsigned int pll_clock(enum plls pll);
 484
 485 unsigned int get_main_clock(enum main_clocks clk);
 486
 487 unsigned int get_peri_clock(enum peri_clocks clk);
 488
 489 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
 490
 491 #endif //#if !defined(__ASSEMBLER__)
 492
 493 #define HAL_MMU_OFF()                                               \
 494 CYG_MACRO_START                                                     \
 495     asm volatile (                                                  \
 496         "1: "                                                       \
 497         "mrc p15, 0, r15, c7, c14, 3;"   /*test clean and inval*/   \
 498         "bne 1b;"                                                   \
 499         "mov r0, #0;"                                               \
 500         "mcr p15,0,r0,c7,c10,4;"   /*drain write buffer*/           \
 501         "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */            \
 502         "mrc p15,0,r0,c1,c0,0;" /* read c1 */                       \
 503         "bic r0,r0,#0x7;" /* disable DCache and MMU */              \
 504         "bic r0,r0,#0x1000;" /* disable ICache */                   \
 505         "mcr p15,0,r0,c1,c0,0;" /*  */                              \
 506         "nop;" /* flush i+d-TLBs */                                 \
 507         "nop;" /* flush i+d-TLBs */                                 \
 508         "nop;" /* flush i+d-TLBs */                                 \
 509         :                                                           \
 510         :                                                           \
 511         : "r0","memory" /* clobber list */);                        \
 512 CYG_MACRO_END
 513
 514 #endif /* __HAL_SOC_H__ */