packages/hal/arm/mx25/var/v2_0/src/soc_diag.c

   1 /*=============================================================================
   2 //
   3 //  hal_diag.c
   4 //
   5 //  HAL diagnostic output code
   6 //
   7 //=============================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //===========================================================================*/
  41
  42 #include <pkgconf/hal.h>
  43 #include <pkgconf/system.h>
  44 #include CYGBLD_HAL_PLATFORM_H
  45
  46 #include <cyg/infra/cyg_type.h>                 // base types
  47 #include <cyg/infra/cyg_trac.h>                 // tracing macros
  48 #include <cyg/infra/cyg_ass.h>                  // assertion macros
  49
  50 #include <cyg/hal/hal_arch.h>                   // basic machine info
  51 #include <cyg/hal/hal_intr.h>                   // interrupt macros
  52 #include <cyg/hal/hal_io.h>                             // IO macros
  53 #include <cyg/hal/hal_if.h>                             // Calling interface definitions
  54 #include <cyg/hal/hal_diag.h>
  55 #include <cyg/hal/drv_api.h>                    // cyg_drv_interrupt_acknowledge
  56 #include <cyg/hal/hal_misc.h>                   // Helper functions
  57 #include <cyg/hal/hal_soc.h>                    // Hardware definitions
  58
  59 /*
  60  * UART Control Register 0 Bit Fields.
  61  */
  62 #define EUartUCR1_ADEN          (1 << 15)                       // Auto dectect interrupt
  63 #define EUartUCR1_ADBR          (1 << 14)                       // Auto detect baud rate
  64 #define EUartUCR1_TRDYEN        (1 << 13)                       // Transmitter ready interrupt enable
  65 #define EUartUCR1_IDEN          (1 << 12)                       // Idle condition interrupt
  66 #define EUartUCR1_RRDYEN        (1 << 9)                        // Recv ready interrupt enable
  67 #define EUartUCR1_RDMAEN        (1 << 8)                        // Recv ready DMA enable
  68 #define EUartUCR1_IREN          (1 << 7)                        // Infrared interface enable
  69 #define EUartUCR1_TXMPTYEN      (1 << 6)                        // Transimitter empty interrupt enable
  70 #define EUartUCR1_RTSDEN        (1 << 5)                        // RTS delta interrupt enable
  71 #define EUartUCR1_SNDBRK        (1 << 4)                        // Send break
  72 #define EUartUCR1_TDMAEN        (1 << 3)                        // Transmitter ready DMA enable
  73 #define EUartUCR1_DOZE          (1 << 1)                        // Doze
  74 #define EUartUCR1_UARTEN        (1 << 0)                        // UART enabled
  75 #define EUartUCR2_ESCI          (1 << 15)                       // Escape seq interrupt enable
  76 #define EUartUCR2_IRTS          (1 << 14)                       // Ignore RTS pin
  77 #define EUartUCR2_CTSC          (1 << 13)                       // CTS pin control
  78 #define EUartUCR2_CTS           (1 << 12)                       // Clear to send
  79 #define EUartUCR2_ESCEN         (1 << 11)                       // Escape enable
  80 #define EUartUCR2_PREN          (1 << 8)                        // Parity enable
  81 #define EUartUCR2_PROE          (1 << 7)                        // Parity odd/even
  82 #define EUartUCR2_STPB          (1 << 6)                        // Stop
  83 #define EUartUCR2_WS            (1 << 5)                        // Word size
  84 #define EUartUCR2_RTSEN         (1 << 4)                        // Request to send interrupt enable
  85 #define EUartUCR2_ATEN          (1 << 3)                        // Aging timer enable
  86 #define EUartUCR2_TXEN          (1 << 2)                        // Transmitter enabled
  87 #define EUartUCR2_RXEN          (1 << 1)                        // Receiver enabled
  88 #define EUartUCR2_SRST_         (1 << 0)                        // SW reset
  89 #define EUartUCR3_PARERREN      (1 << 12)                       // Parity enable
  90 #define EUartUCR3_FRAERREN      (1 << 11)                       // Frame error interrupt enable
  91 #define EUartUCR3_ADNIMP        (1 << 7)                        // Autobaud detection not improved
  92 #define EUartUCR3_RXDSEN        (1 << 6)                        // Receive status interrupt enable
  93 #define EUartUCR3_AIRINTEN      (1 << 5)                        // Async IR wake interrupt enable
  94 #define EUartUCR3_AWAKEN        (1 << 4)                        // Async wake interrupt enable
  95 #define EUartUCR3_RXDMUXSEL (1 << 2)                    // RXD muxed input selected
  96 #define EUartUCR3_INVT          (1 << 1)                        // Inverted Infrared transmission
  97 #define EUartUCR3_ACIEN         (1 << 0)                        // Autobaud counter interrupt enable
  98 #define EUartUCR4_CTSTL_32      (32 << 10)                      // CTS trigger level (32 chars)
  99 #define EUartUCR4_INVR          (1 << 9)                        // Inverted infrared reception
 100 #define EUartUCR4_ENIRI         (1 << 8)                        // Serial infrared interrupt enable
 101 #define EUartUCR4_WKEN          (1 << 7)                        // Wake interrupt enable
 102 #define EUartUCR4_IRSC          (1 << 5)                        // IR special case
 103 #define EUartUCR4_LPBYP         (1 << 4)                        // Low power bypass
 104 #define EUartUCR4_TCEN          (1 << 3)                        // Transmit complete interrupt enable
 105 #define EUartUCR4_BKEN          (1 << 2)                        // Break condition interrupt enable
 106 #define EUartUCR4_OREN          (1 << 1)                        // Receiver overrun interrupt enable
 107 #define EUartUCR4_DREN          (1 << 0)                        // Recv data ready interrupt enable
 108 #define EUartUFCR_RXTL_SHF      0                                       // Receiver trigger level shift
 109 #define EUartUFCR_RFDIV_1       (5 << 7)                        // Reference freq divider (div 1)
 110 #define EUartUFCR_RFDIV_2       (4 << 7)                        // Reference freq divider (div 2)
 111 #define EUartUFCR_RFDIV_3       (3 << 7)                        // Reference freq divider (div 3)
 112 #define EUartUFCR_RFDIV_4       (2 << 7)                        // Reference freq divider (div 4)
 113 #define EUartUFCR_RFDIV_5       (1 << 7)                        // Reference freq divider (div 5)
 114 #define EUartUFCR_RFDIV_6       (0 << 7)                        // Reference freq divider (div 6)
 115 #define EUartUFCR_RFDIV_7       (6 << 7)                        // Reference freq divider (div 7)
 116 #define EUartUFCR_TXTL_SHF      10                                      // Transmitter trigger level shift
 117 #define EUartUSR1_PARITYERR (1 << 15)                   // Parity error interrupt flag
 118 #define EUartUSR1_RTSS          (1 << 14)                       // RTS pin status
 119 #define EUartUSR1_TRDY          (1 << 13)                       // Transmitter ready interrupt/dma flag
 120 #define EUartUSR1_RTSD          (1 << 12)                       // RTS delta
 121 #define EUartUSR1_ESCF          (1 << 11)                       // Escape seq interrupt flag
 122 #define EUartUSR1_FRAMERR       (1 << 10)                       // Frame error interrupt flag
 123 #define EUartUSR1_RRDY          (1 << 9)                        // Receiver ready interrupt/dma flag
 124 #define EUartUSR1_AGTIM         (1 << 8)                        // Aging timeout interrupt status
 125 #define EUartUSR1_RXDS          (1 << 6)                        // Receiver idle interrupt flag
 126 #define EUartUSR1_AIRINT        (1 << 5)                        // Async IR wake interrupt flag
 127 #define EUartUSR1_AWAKE         (1 << 4)                        // Aysnc wake interrupt flag
 128 #define EUartUSR2_ADET          (1 << 15)                       // Auto baud rate detect complete
 129 #define EUartUSR2_TXFE          (1 << 14)                       // Transmit buffer FIFO empty
 130 #define EUartUSR2_IDLE          (1 << 12)                       // Idle condition
 131 #define EUartUSR2_ACST          (1 << 11)                       // Autobaud counter stopped
 132 #define EUartUSR2_IRINT         (1 << 8)                        // Serial infrared interrupt flag
 133 #define EUartUSR2_WAKE          (1 << 7)                        // Wake
 134 #define EUartUSR2_RTSF          (1 << 4)                        // RTS edge interrupt flag
 135 #define EUartUSR2_TXDC          (1 << 3)                        // Transmitter complete
 136 #define EUartUSR2_BRCD          (1 << 2)                        // Break condition
 137 #define EUartUSR2_ORE           (1 << 1)                        // Overrun error
 138 #define EUartUSR2_RDR           (1 << 0)                        // Recv data ready
 139 #define EUartUTS_FRCPERR        (1 << 13)                       // Force parity error
 140 #define EUartUTS_LOOP           (1 << 12)                       // Loop tx and rx
 141 #define EUartUTS_TXEMPTY        (1 << 6)                        // TxFIFO empty
 142 #define EUartUTS_RXEMPTY        (1 << 5)                        // RxFIFO empty
 143 #define EUartUTS_TXFULL         (1 << 4)                        // TxFIFO full
 144 #define EUartUTS_RXFULL         (1 << 3)                        // RxFIFO full
 145 #define EUartUTS_SOFTRST        (1 << 0)                        // Software reset
 146
 147 #define EUartUFCR_RFDIV                                                 EUartUFCR_RFDIV_1
 148
 149 #if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_1)
 150 #define MXC_UART_REFFREQ                                                (get_peri_clock(PER_UART_CLK) / 1)
 151 #endif
 152
 153 #if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2)
 154 #define MXC_UART_REFFREQ                                                (get_peri_clock(PER_UART_CLK) / 2)
 155 #endif
 156
 157 #if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4)
 158 #define MXC_UART_REFFREQ                                                (get_peri_clock(PER_UART_CLK) / 4)
 159 #endif
 160
 161 /* The Freescale 3Stack board has two external UART ports which are mapped first
 162  * for whatever strange reason.
 163  * Other manufacturers may not have these UARTS on their boards but would
 164  * as well like to have their serial ports start at '0'!
 165  */
 166 #ifdef CYGPKG_HAL_ARM_MX25_3STACK
 167 #define MXC_UART_CHAN_OFFSET    2
 168 #else
 169 #define MXC_UART_CHAN_OFFSET    0
 170 #endif
 171
 172 #if 0
 173 void
 174 cyg_hal_plf_comms_init(void)
 175 {
 176         static int initialized = 0;
 177
 178         if (initialized)
 179                 return;
 180
 181         initialized = 1;
 182
 183         cyg_hal_plf_serial_init();
 184 }
 185 #endif
 186
 187 //=============================================================================
 188 // MXC Serial Port (UARTx) for Debug
 189 //=============================================================================
 190 #ifdef UART_WIDTH_32
 191 struct mxc_serial {
 192         volatile cyg_uint32 urxd[16];
 193         volatile cyg_uint32 utxd[16];
 194         volatile cyg_uint32 ucr1;
 195         volatile cyg_uint32 ucr2;
 196         volatile cyg_uint32 ucr3;
 197         volatile cyg_uint32 ucr4;
 198         volatile cyg_uint32 ufcr;
 199         volatile cyg_uint32 usr1;
 200         volatile cyg_uint32 usr2;
 201         volatile cyg_uint32 uesc;
 202         volatile cyg_uint32 utim;
 203         volatile cyg_uint32 ubir;
 204         volatile cyg_uint32 ubmr;
 205         volatile cyg_uint32 ubrc;
 206         volatile cyg_uint32 onems;
 207         volatile cyg_uint32 uts;
 208 };
 209 #else
 210 struct mxc_serial {
 211         volatile cyg_uint16 urxd[1];
 212         volatile cyg_uint16 resv0[31];
 213
 214         volatile cyg_uint16 utxd[1];
 215         volatile cyg_uint16 resv1[31];
 216         volatile cyg_uint16 ucr1;
 217         volatile cyg_uint16 resv2;
 218         volatile cyg_uint16 ucr2;
 219         volatile cyg_uint16 resv3;
 220         volatile cyg_uint16 ucr3;
 221         volatile cyg_uint16 resv4;
 222         volatile cyg_uint16 ucr4;
 223         volatile cyg_uint16 resv5;
 224         volatile cyg_uint16 ufcr;
 225         volatile cyg_uint16 resv6;
 226         volatile cyg_uint16 usr1;
 227         volatile cyg_uint16 resv7;
 228         volatile cyg_uint16 usr2;
 229         volatile cyg_uint16 resv8;
 230         volatile cyg_uint16 uesc;
 231         volatile cyg_uint16 resv9;
 232         volatile cyg_uint16 utim;
 233         volatile cyg_uint16 resv10;
 234         volatile cyg_uint16 ubir;
 235         volatile cyg_uint16 resv11;
 236         volatile cyg_uint16 ubmr;
 237         volatile cyg_uint16 resv12;
 238         volatile cyg_uint16 ubrc;
 239         volatile cyg_uint16 resv13;
 240         volatile cyg_uint16 onems;
 241         volatile cyg_uint16 resv14;
 242         volatile cyg_uint16 uts;
 243         volatile cyg_uint16 resv15;
 244 };
 245 #endif
 246
 247 typedef struct {
 248         volatile struct mxc_serial *base;
 249         cyg_int32 msec_timeout;
 250         int isr_vector;
 251         int baud_rate;
 252 } channel_data_t;
 253
 254 static channel_data_t channels[] = {
 255 #if CYGHWR_HAL_ARM_SOC_UART1 != 0
 256         {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
 257           CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
 258 #endif
 259 #if CYGHWR_HAL_ARM_SOC_UART2 != 0
 260         {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
 261          CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
 262 #endif
 263 #if CYGHWR_HAL_ARM_SOC_UART3 != 0
 264         {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
 265          CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
 266 #endif
 267 };
 268
 269 /*---------------------------------------------------------------------------*/
 270
 271 static void init_serial_channel(channel_data_t *__ch_data)
 272 {
 273         volatile struct mxc_serial *base = __ch_data->base;
 274
 275         /* Wait for UART to finish transmitting */
 276         while (!(base->uts & EUartUTS_TXEMPTY));
 277
 278         /* Disable UART */
 279         base->ucr1 &= ~EUartUCR1_UARTEN;
 280
 281         /* Set to default POR state */
 282         base->ucr1 = 0x00000000;
 283         base->ucr2 = 0x00000000;
 284
 285         while (!(base->ucr2 & EUartUCR2_SRST_));
 286
 287         base->ucr3 = 0x00000704;
 288         base->ucr4 = 0x00008000;
 289         base->ufcr = 0x00000801;
 290         base->uesc = 0x0000002B;
 291         base->utim = 0x00000000;
 292         base->ubir = 0x00000000;
 293         base->ubmr = 0x00000000;
 294         base->onems = 0x00000000;
 295         base->uts  = 0x00000000;
 296
 297         /* Configure FIFOs */
 298         base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV |
 299                 (2 << EUartUFCR_TXTL_SHF);
 300
 301         /* Setup One MS timer */
 302         base->onems = MXC_UART_REFFREQ / 1000;
 303
 304         /* Set to 8N1 */
 305         base->ucr2 &= ~EUartUCR2_PREN;
 306         base->ucr2 |= EUartUCR2_WS;
 307         base->ucr2 &= ~EUartUCR2_STPB;
 308
 309         /* Ignore RTS */
 310         base->ucr2 |= EUartUCR2_IRTS;
 311
 312         /* Enable UART */
 313         base->ucr1 |= EUartUCR1_UARTEN;
 314
 315         /* Enable FIFOs */
 316         base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
 317
 318         /* Clear status flags */
 319         base->usr2 |= EUartUSR2_ADET  |
 320                                   EUartUSR2_IDLE  |
 321                                   EUartUSR2_IRINT |
 322                                   EUartUSR2_WAKE  |
 323                                   EUartUSR2_RTSF  |
 324                                   EUartUSR2_BRCD  |
 325                                   EUartUSR2_ORE   |
 326                                   EUartUSR2_RDR;
 327
 328         /* Clear status flags */
 329         base->usr1 |= EUartUSR1_PARITYERR |
 330                                   EUartUSR1_RTSD          |
 331                                   EUartUSR1_ESCF          |
 332                                   EUartUSR1_FRAMERR       |
 333                                   EUartUSR1_AIRINT        |
 334                                   EUartUSR1_AWAKE;
 335
 336         /* Set the numerator value minus one of the BRM ratio */
 337         base->ubir = (__ch_data->baud_rate / 100) - 1;
 338
 339         /* Set the denominator value minus one of the BRM ratio */
 340         base->ubmr = (MXC_UART_REFFREQ / 1600) - 1;
 341 }
 342
 343 static void stop_serial_channel(channel_data_t *__ch_data)
 344 {
 345         volatile struct mxc_serial *base = __ch_data->base;
 346
 347         /* Wait for UART to finish transmitting */
 348         while (!(base->uts & EUartUTS_TXEMPTY));
 349
 350         /* Disable UART */
 351         base->ucr1 &= ~EUartUCR1_UARTEN;
 352 }
 353
 354 //#define debug_uart_log_buf
 355 #ifdef debug_uart_log_buf
 356 #define DIAG_BUFSIZE 2048
 357 static char __log_buf[DIAG_BUFSIZE];
 358 static int diag_bp = 0;
 359 #endif
 360
 361 void cyg_hal_plf_serial_putc(void *__ch_data, char c)
 362 {
 363         channel_data_t *chan = __ch_data;
 364         volatile struct mxc_serial *base = chan->base;
 365 #ifdef debug_uart_log_buf
 366         __log_buf[diag_bp++] = c;
 367 #endif
 368
 369         CYGARC_HAL_SAVE_GP();
 370
 371         // Wait for Tx FIFO not full
 372         while (base->uts & EUartUTS_TXFULL)
 373                 ;
 374         base->utxd[0] = c;
 375
 376         CYGARC_HAL_RESTORE_GP();
 377 }
 378
 379 static cyg_bool cyg_hal_plf_serial_getc_nonblock(void *__ch_data,
 380                                                                                                  cyg_uint8 *ch)
 381 {
 382         channel_data_t *chan = __ch_data;
 383         volatile struct mxc_serial *base = chan->base;
 384
 385         // If receive fifo is empty, return false
 386         if (base->uts & EUartUTS_RXEMPTY)
 387                 return false;
 388
 389         *ch = (char)base->urxd[0];
 390
 391         return true;
 392 }
 393
 394 cyg_uint8 cyg_hal_plf_serial_getc(void *__ch_data)
 395 {
 396         cyg_uint8 ch;
 397         CYGARC_HAL_SAVE_GP();
 398
 399         while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 400
 401         CYGARC_HAL_RESTORE_GP();
 402         return ch;
 403 }
 404
 405 static void cyg_hal_plf_serial_write(void *__ch_data, const cyg_uint8 *__buf,
 406                                                                          cyg_uint32 __len)
 407 {
 408         CYGARC_HAL_SAVE_GP();
 409
 410         while (__len-- > 0)
 411                 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 412
 413         CYGARC_HAL_RESTORE_GP();
 414 }
 415
 416 static void cyg_hal_plf_serial_read(void *__ch_data, cyg_uint8 *__buf,
 417                                                                         cyg_uint32 __len)
 418 {
 419         CYGARC_HAL_SAVE_GP();
 420
 421         while (__len-- > 0)
 422                 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 423
 424         CYGARC_HAL_RESTORE_GP();
 425 }
 426
 427 cyg_bool cyg_hal_plf_serial_getc_timeout(void *__ch_data,
 428                                                                                  cyg_uint8 *ch)
 429 {
 430         int delay_count;
 431         channel_data_t *chan = __ch_data;
 432         cyg_bool res;
 433         CYGARC_HAL_SAVE_GP();
 434
 435         delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 436
 437         for (;;) {
 438                 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
 439                 if (res || 0 == delay_count--)
 440                         break;
 441
 442                 CYGACC_CALL_IF_DELAY_US(100);
 443         }
 444
 445         CYGARC_HAL_RESTORE_GP();
 446         return res;
 447 }
 448
 449 static int cyg_hal_plf_serial_control(void *__ch_data,
 450                                                                           __comm_control_cmd_t __func, ...)
 451 {
 452         static int irq_state = 0;
 453         channel_data_t *chan = __ch_data;
 454         int ret = -1;
 455         va_list ap;
 456
 457         CYGARC_HAL_SAVE_GP();
 458         va_start(ap, __func);
 459
 460         switch (__func) {
 461         case __COMMCTL_GETBAUD:
 462                 ret = chan->baud_rate;
 463                 break;
 464         case __COMMCTL_SETBAUD:
 465                 chan->baud_rate = va_arg(ap, cyg_int32);
 466                 // Should we verify this value here?
 467                 init_serial_channel(chan);
 468                 ret = 0;
 469                 break;
 470         case __COMMCTL_IRQ_ENABLE:
 471                 irq_state = 1;
 472
 473                 chan->base->ucr1 |= EUartUCR1_RRDYEN;
 474
 475                 HAL_INTERRUPT_UNMASK(chan->isr_vector);
 476                 break;
 477         case __COMMCTL_IRQ_DISABLE:
 478                 ret = irq_state;
 479                 irq_state = 0;
 480
 481                 chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
 482
 483                 HAL_INTERRUPT_MASK(chan->isr_vector);
 484                 break;
 485         case __COMMCTL_DBG_ISR_VECTOR:
 486                 ret = chan->isr_vector;
 487                 break;
 488         case __COMMCTL_SET_TIMEOUT:
 489                 ret = chan->msec_timeout;
 490                 chan->msec_timeout = va_arg(ap, cyg_uint32);
 491                 break;
 492         default:
 493                 break;
 494         }
 495         va_end(ap);
 496         CYGARC_HAL_RESTORE_GP();
 497         return ret;
 498 }
 499
 500 static int cyg_hal_plf_serial_isr(void *__ch_data, int *__ctrlc,
 501                                                                   CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
 502 {
 503         int res = 0;
 504         channel_data_t *chan = __ch_data;
 505         char c;
 506
 507         CYGARC_HAL_SAVE_GP();
 508
 509         cyg_drv_interrupt_acknowledge(chan->isr_vector);
 510
 511         *__ctrlc = 0;
 512         if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
 513                 c = (char)chan->base->urxd[0];
 514
 515                 if (cyg_hal_is_break(&c, 1))
 516                         *__ctrlc = 1;
 517
 518                 res = CYG_ISR_HANDLED;
 519         }
 520
 521         CYGARC_HAL_RESTORE_GP();
 522         return res;
 523 }
 524
 525 #define NUMOF(x) (sizeof(x) / sizeof(x[0]))
 526
 527 void cyg_hal_plf_serial_init(void)
 528 {
 529         hal_virtual_comm_table_t *comm;
 530         int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 531         int i;
 532         static int jjj = 0;
 533
 534         // Init channels
 535         for (i = 0;      i < NUMOF(channels);  i++) {
 536                 init_serial_channel(&channels[i]);
 537                 CYGACC_CALL_IF_SET_CONSOLE_COMM(i + MXC_UART_CHAN_OFFSET);
 538                 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
 539                 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
 540                 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
 541                 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
 542                 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
 543                 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
 544                 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
 545                 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
 546                 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 547                 if (jjj == 0) {
 548                         cyg_hal_plf_serial_putc(&channels[i], '+');
 549                         jjj++;
 550                 }
 551         }
 552
 553         // Restore original console
 554         CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
 555 }
 556
 557 void cyg_hal_plf_serial_stop(void)
 558 {
 559         int i;
 560
 561         // Init channels
 562         for (i = 0;      i < NUMOF(channels);  i++) {
 563                 stop_serial_channel(&channels[i]);
 564         }
 565 }
 566
 567 //=============================================================================
 568 // Compatibility with older stubs
 569 //=============================================================================
 570
 571 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 572
 573 #include <cyg/hal/hal_stub.h>                   // cyg_hal_gdb_interrupt
 574
 575 #define MXC_UART1_CHAN          (0 + MXC_UART_CHAN_OFFSET)
 576 #define MXC_UART2_CHAN          (1 + MXC_UART_CHAN_OFFSET)
 577 #define MXC_UART3_CHAN          (2 + MXC_UART_CHAN_OFFSET)
 578 #define MXC_UART4_CHAN          (3 + MXC_UART_CHAN_OFFSET)
 579 #define MXC_UART5_CHAN          (4 + MXC_UART_CHAN_OFFSET)
 580 #define MXC_UART6_CHAN          (5 + MXC_UART_CHAN_OFFSET)
 581
 582 #undef __BASE
 583
 584 #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART1_CHAN)
 585 #define __BASE ((void*)UART1_BASE_ADDR)
 586 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
 587 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART2_CHAN)
 588 #define __BASE ((void*)UART2_BASE_ADDR)
 589 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
 590 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART3_CHAN)
 591 #define __BASE ((void*)UART3_BASE_ADDR)
 592 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3
 593 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART4_CHAN)
 594 #define __BASE ((void*)UART4_BASE_ADDR)
 595 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART4
 596 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART5_CHAN)
 597 #define __BASE ((void*)UART5_BASE_ADDR)
 598 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART5
 599 #endif
 600
 601 #ifdef __BASE
 602
 603 #ifdef CYGSEM_HAL_ROM_MONITOR
 604 #define CYG_HAL_STARTUP_ROM
 605 #define CYG_HAL_STARTUP_ROMRAM
 606 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 607 #endif
 608
 609 #if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 610 #define HAL_DIAG_USES_HARDWARE
 611 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
 612 #define HAL_DIAG_USES_HARDWARE
 613 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
 614 #define HAL_DIAG_USES_HARDWARE
 615 #endif
 616
 617 static channel_data_t channel = {
 618         __BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
 619 };
 620
 621 #ifdef HAL_DIAG_USES_HARDWARE
 622
 623 void hal_diag_init(void)
 624 {
 625         static int init = 0;
 626         char *msg = "\n\rARM eCos\n\r";
 627
 628         if (init++) return;
 629
 630         init_serial_channel(&channel);
 631
 632         while (*msg) hal_diag_write_char(*msg++);
 633 }
 634
 635 #ifdef DEBUG_DIAG
 636 #ifndef CYG_HAL_STARTUP_ROM
 637 #define DIAG_BUFSIZE 2048
 638 static char diag_buffer[DIAG_BUFSIZE];
 639 static int diag_bp = 0;
 640 #endif
 641 #endif
 642
 643 void hal_diag_write_char(char c)
 644 {
 645 #ifdef DEBUG_DIAG
 646 #ifndef CYG_HAL_STARTUP_ROM
 647         diag_buffer[diag_bp++] = c;
 648         if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
 649 #endif
 650 #endif
 651         cyg_hal_plf_serial_putc(&channel, c);
 652 }
 653
 654 void hal_diag_read_char(char *c)
 655 {
 656         *c = cyg_hal_plf_serial_getc(&channel);
 657 }
 658
 659 #else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
 660
 661 void hal_diag_read_char(char *c)
 662 {
 663         *c = cyg_hal_plf_serial_getc(&channel);
 664 }
 665
 666 void hal_diag_write_char(char c)
 667 {
 668         static char line[100];
 669         static int pos = 0;
 670
 671         // FIXME: Some LED blinking might be nice right here.
 672
 673         // No need to send CRs
 674         if (c == '\r') return;
 675
 676         line[pos++] = c;
 677
 678         if (c == '\n' || pos == sizeof(line)) {
 679                 CYG_INTERRUPT_STATE old;
 680
 681                 // Disable interrupts. This prevents GDB trying to interrupt us
 682                 // while we are in the middle of sending a packet. The serial
 683                 // receive interrupt will be seen when we re-enable interrupts
 684                 // later.
 685 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 686                 CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
 687 #else
 688                 HAL_DISABLE_INTERRUPTS(old);
 689 #endif
 690                 while (1) {
 691                         static char hex[] = "0123456789ABCDEF";
 692                         cyg_uint8 csum = 0;
 693                         int i;
 694 #ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
 695                         char c1;
 696 #endif
 697                         cyg_hal_plf_serial_putc(&channel, '$');
 698                         cyg_hal_plf_serial_putc(&channel, 'O');
 699                         csum += 'O';
 700                         for (i = 0; i < pos; i++) {
 701                                 char ch = line[i];
 702                                 char h = hex[(ch >> 4) & 0xF];
 703                                 char l = hex[ch & 0xF];
 704                                 cyg_hal_plf_serial_putc(&channel, h);
 705                                 cyg_hal_plf_serial_putc(&channel, l);
 706                                 csum += h;
 707                                 csum += l;
 708                         }
 709                         cyg_hal_plf_serial_putc(&channel, '#');
 710                         cyg_hal_plf_serial_putc(&channel, hex[(csum >> 4) & 0xF]);
 711                         cyg_hal_plf_serial_putc(&channel, hex[csum & 0xF]);
 712
 713 #ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
 714
 715                         break; // regardless
 716
 717 #else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
 718
 719                         // Wait for the ACK character '+' from GDB here and handle
 720                         // receiving a ^C instead.  This is the reason for this clause
 721                         // being a loop.
 722                         c1 = cyg_hal_plf_serial_getc(&channel);
 723
 724                         if (c1 == '+')
 725                                 break;                          // a good acknowledge
 726
 727 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 728                         cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
 729                         if (c1 == '\003') {
 730                                 // Ctrl-C: breakpoint.
 731                                 cyg_hal_gdb_interrupt((target_register_t)__builtin_return_address(0));
 732                                 break;
 733                         }
 734 #endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 735
 736 #endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
 737                         // otherwise, loop round again
 738                 }
 739
 740                 pos = 0;
 741
 742                 // And re-enable interrupts
 743 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 744                 CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
 745 #else
 746                 HAL_RESTORE_INTERRUPTS(old);
 747 #endif
 748         }
 749 }
 750 #endif
 751
 752 #endif // __BASE
 753
 754 #endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 755
 756 /*---------------------------------------------------------------------------*/
 757 /* End of hal_diag.c */