1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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30 // or inline functions from this file, or you compile this file and link it
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/karo_tx27.h> // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
54 #define PLATFORM_SETUP1 _platform_setup1
55 #define CYGHWR_HAL_ARM_HAS_MMU
57 #ifdef CYG_HAL_STARTUP_ROMRAM
58 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
61 #define TX27_NAND_PAGE_SIZE 2048
62 #define TX27_NAND_BLKS_PER_PAGE 64
64 #define CYGHWR_HAL_ROM_VADDR 0x0
66 #ifndef CYGOPT_HAL_ARM_TX27_DEBUG
76 #define CYGHWR_LED_MACRO LED_BLINK #\x
77 #define LED_ON bl led_on
78 #define LED_OFF bl led_off
94 // switch user LED (PF13) on STK5
99 movne r9, #(1 << 13) // LED ON
100 moveq r9, #0 // LED OFF
101 str r9, [r10, #GPIO_DR]
120 // initialize GPIO PF13 for LED on STK5
123 ldr r9, [r10, #GPIO_GIUS]
124 orr r9, r9, #(1 << 13)
125 str r9, [r10, #GPIO_GIUS]
128 str r9, [r10, #GPIO_DDIR]
130 mov r9, #(3 << (2 * 13))
131 str r9, [r10, #GPIO_OCR1]
134 // This macro represents the initial startup code for the platform
135 // r11 is reserved to contain chip rev info in this file
136 .macro _platform_setup1
137 KARO_TX27_SETUP_START:
138 // invalidate I/D cache/TLB
140 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
141 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
142 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
149 // setup System Controls
150 ldr r0, SOC_SYSCTRL_BASE_W
152 str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
153 // select 2kpage NAND (NF_FMS), CSD0, CS3
154 mvn r1, #(FMCR_SDCS1_SEL | FMCR_NF_16BIT | FMCR_SLCDC_SEL)
155 str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
159 init_drive_strength_start:
172 // check if sdram has been setup
173 cmp pc, #SDRAM_BASE_ADDR
175 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
176 blo HWInitialise_skip_SDRAM_setup
184 HWInitialise_skip_SDRAM_setup:
186 add r2, r0, #0x800 // 2K window
188 blo Normal_Boot_Continue
190 bhi Normal_Boot_Continue
193 /* Copy image from flash to SDRAM first */
194 ldr r1, MXC_REDBOOT_RAM_START
202 ldr r1, MXC_REDBOOT_RAM_START
223 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
224 mov r1, #TX27_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
225 add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 1st RAM buf. Doesn't change
226 add r4, r0, #0xE00 //r4: NFC register base. Doesn't change
227 ldr r5, MXC_REDBOOT_RAM_START
228 add r6, r5, #REDBOOT_IMAGE_SIZE //r6: end of SDRAM address for copying. Doesn't change
229 add r5, r5, r1 //r5: starting SDRAM address for copying. Updated constantly
231 // enable ECC, disable interrupts
232 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
233 strh r3, [r4, #NAND_FLASH_CONFIG1_REG_OFF]
235 //unlock internal buffer
242 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
252 bl nfc_addr_input //2nd addr cycle
255 bl nfc_addr_input //3rd addr cycle
258 bl nfc_addr_input //4th addr cycle
267 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
270 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
273 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
276 // check for bad block
277 mov r3, r1, lsl #(32-17) // get rid of block number
278 cmp r3, #(TX27_NAND_PAGE_SIZE << (32-17)) // check if not first or second page in block
283 add r9, r0, #TX27_NAND_PAGE_SIZE //r3 -> spare area buf 0
288 // really sucks. Bad block!!!!
291 // even suckier since we already read the first page!
292 sub r5, r5, #TX27_NAND_PAGE_SIZE //rewind 1 page for the sdram pointer
293 sub r1, r1, #TX27_NAND_PAGE_SIZE //rewind 1 page for the flash pointer
295 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
299 add r1, r1, #(TX27_NAND_BLKS_PER_PAGE*TX27_NAND_PAGE_SIZE)
313 bge NAND_Copy_Main_done
315 add r1, r1, #TX27_NAND_PAGE_SIZE
320 Normal_Boot_Continue:
322 // Code and all data used up to here must fit within the first 2KiB of FLASH ROM!
323 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
324 /* Copy image from flash to SDRAM first */
327 ldr r1, MXC_REDBOOT_RAM_START
329 beq HWInitialise_skip_SDRAM_copy
331 add r2, r0, #REDBOOT_IMAGE_SIZE
341 #endif /* CYG_HAL_STARTUP_ROMRAM */
343 HWInitialise_skip_SDRAM_copy:
350 ldr r1, =(SOC_CRM_BASE)
351 ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
354 ldr r1, =(SOC_CRM_BASE)
355 str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
357 /* end of NAND clock divider setup */
359 // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
360 ldr r1, =(SOC_SYSCTRL_GPCR)
365 // Set up a stack [for calling C code]
366 ldr r1, =__startup_stack
367 ldr r2, =RAM_BANK0_BASE
377 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
378 orr r1, r1, #7 // enable MMU bit
379 mcr MMU_CP, 0, r1, MMU_Control, c0
383 mov pc,r2 /* Change address spaces */
386 .endm // _platform_setup1
388 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
389 #define PLATFORM_SETUP1
393 ldr r0, SOC_CRM_BASE_W
394 // disable MPLL/SPLL first
395 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
397 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
400 ldr r1, CRM_MPCTL0_VAL2_W
401 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
404 ldr r1, CRM_SPCTL0_VAL2_W
405 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
407 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
408 #ifdef PLL_REF_CLK_32768HZ
409 // Make sure to use CKIL
410 bic r1, r1, #(3 << 16)
412 orr r1, r1, #(3 << 16) // select 26MHz
414 orr r1, r1, #0x000C0000 // restart SPLL and MPLL
415 orr r1, r1, #0x00000003 // enable SPLL and MPLL
416 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
418 // add some delay here
424 ldr r2, SOC_CRM_CSCR2_W
425 str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
427 // Set divider of H264_CLK to zero, NFC to 3.
428 ldr r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
429 bic r2, r2, #0x0000FC00
430 str r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
432 /* Configure PCDR1 */
433 ldr r1, SOC_CRM_PCDR1_W
434 str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
436 // Configure PCCR0 and PCCR1
437 ldr r1, SOC_CRM_PCCR0_W
438 str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
440 ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
442 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
443 // make default CLKO to be FCLK
444 ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
445 and r1, r1, #0xFFFFFFE0
447 str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
451 ldr r1, SOC_CS0_CTL_BASE_W
452 ldr r2, CS0_CSCRU_VAL
453 str r2, [r1, #CSCRU_OFFSET]
454 ldr r2, CS0_CSCRL_VAL
455 str r2, [r1, #CSCRL_OFFSET]
456 ldr r2, CS0_CSCRA_VAL
457 str r2, [r1, #CSCRA_OFFSET]
460 /* CS0 sync mode setup */
463 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
465 ldr r0, =SOC_CS0_CTL_BASE
466 ldr r1, CS0_CSCRU_SYNC_VAL
467 str r1, [r0, #CSCRU_OFFSET]
468 ldr r1, CS0_CSCRL_SYNC_VAL
469 str r1, [r0, #CSCRL_OFFSET]
470 ldr r1, CS0_CSCRA_SYNC_VAL
471 str r1, [r0, #CSCRA_OFFSET]
472 .endm /* init_cs0_sync */
474 .macro init_cs4 /* ADS board expanded IOs */
475 ldr r1, SOC_CS4_CTL_BASE_W
476 ldr r2, CS4_CSCRU_VAL
477 str r2, [r1, #CSCRU_OFFSET]
478 ldr r2, CS4_CSCRL_VAL
479 str r2, [r1, #CSCRL_OFFSET]
480 ldr r2, CS4_CSCRA_VAL
481 str r2, [r1, #CSCRA_OFFSET]
485 // setup AIPI1 and AIPI2
486 mov r0, #SOC_AIPI1_BASE
487 ldr r1, AIPI1_PSR0_VAL
488 str r1, [r0] /* PSR0 */
489 ldr r2, AIPI1_PSR1_VAL
490 str r2, [r0, #4] /* PSR1 */
491 // set r0 = AIPI2 base
494 str r1, [r0] /* PSR0 */
496 str r2, [r0, #4] /* PSR1 */
500 ldr r0, SOC_MAX_BASE_W
501 add r1, r0, #MAX_SLAVE_PORT1_OFFSET
502 add r2, r0, #MAX_SLAVE_PORT2_OFFSET
503 add r0, r0, #MAX_SLAVE_PORT0_OFFSET
506 ldr r6, SOC_MAX_MPR_VAL /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
507 str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
508 str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
509 str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
510 str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
511 str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
512 str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
515 .macro init_drive_strength
516 ldr r0, SOC_SYSCTRL_BASE_W
518 str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
519 str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
520 str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
522 str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
524 str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
525 .endm // init_drive_strength
527 .macro setup_sdram_ddr
528 // SDRAM controller base address
529 ldr r0, SOC_ESDCTL_BASE_W
530 // base address of SDRAM for SET MODE commands written to SDRAM via address lines
531 mov r2, #SOC_CSD0_BASE
533 mov r1, #(1 << 1) // SDRAM controller reset
534 str r1, [r0, #ESDCTL_ESDMISC]
536 // wait until SDRAMRDY bit is set indicating SDRAM is usable
537 ldr r1, [r0, #ESDCTL_ESDMISC]
541 mov r1, #(1 << 3) @ delay line soft reset
542 str r1, [r0, #ESDCTL_ESDMISC]
544 // wait until SDRAMRDY bit is set indicating SDRAM is usable
545 ldr r1, [r0, #ESDCTL_ESDMISC]
549 mov r1, #(1 << 2) @ enable DDR pipeline
550 str r1, [r0, #ESDCTL_ESDMISC]
552 ldr r1, SDRAM_ESDCFG0_VAL
553 str r1, [r0, #ESDCTL_ESDCFG0]
555 ldr r1, SDRAM_PRE_ALL_CMD
556 str r1, [r0, #ESDCTL_ESDCTL0]
558 str r1, [r2, #(1 << 10)] @ contents of r1 irrelevant, data written via A0-A11
560 ldr r1, SDRAM_AUTO_REF_CMD
561 str r1, [r0, #ESDCTL_ESDCTL0]
562 @ initiate 2 auto refresh cycles
567 ldr r1, SDRAM_SET_MODE_REG_CMD
568 str r1, [r0, #ESDCTL_ESDCTL0]
570 @ address offset for extended mode register
571 add r3, r2, #(2 << 24)
572 @ select drive strength via extended mode register:
573 @ 0=full 1=half 2=quarter 3=3-quarter
574 ldrb r1, [r2, #(0 << 5)]
576 ldrb r1, [r2, #0x033] @ write to SDRAM MODE register (via A0-A12)
578 ldr r1, SDRAM_NORMAL_MODE
579 str r1, [r0, #ESDCTL_ESDCTL0]
582 mov r1, #((1 << 3) | (1 << 2) | (1 << 5))
583 str r1, [r0, #ESDCTL_ESDMISC]
584 .endm // setup_sdram_ddr
586 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
590 mov r9, #(1 << 13) // LED ON
591 str r9, [r10, #GPIO_DR]
597 mov r9, #0 // LED OFF
598 str r9, [r10, #GPIO_DR]
603 strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
604 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
605 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
610 strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
611 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
612 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
616 mov r3, #FDO_PAGE_SPARE_VAL
617 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
623 ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
624 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
626 strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
634 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
635 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
636 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
637 ldr r0, SDRAM_ADDR_MASK
638 ldr r1, MXC_REDBOOT_RAM_START
644 #define PLATFORM_VECTORS _platform_vectors
645 .macro _platform_vectors
649 .globl _KARO_STRUCT_SIZE
651 .word 0 // reserve space structure length
653 .globl _KARO_CECFG_START
656 .word 0 // reserve space for CE configuration
659 .globl _KARO_CECFG_END
664 .ascii "KARO TX27 " __DATE__ " " __TIME__
666 // All these constants need to be in the first 2KiB of FLASH
667 GPIOF_BASE: .word 0x10015500
668 SDRAM_ADDR_MASK: .word 0xffff0000
669 MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
670 SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
671 SOC_MAX_BASE_W: .word SOC_MAX_BASE
672 SOC_MAX_MPR_VAL: .word 0x00302145
673 SOC_CRM_BASE_W: .word SOC_CRM_BASE
674 CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
675 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
676 SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
677 SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
678 SOC_CRM_PCCR0_W: .word 0x3108480F
679 SOC_CS4_CTL_BASE_W: .word SOC_CS4_CTL_BASE
680 CS4_CSCRU_VAL: .word 0x0000DCF6
681 CS4_CSCRL_VAL: .word 0x444A4541
682 CS4_CSCRA_VAL: .word 0x44443302
683 NFC_BASE_W: .word NFC_BASE
684 SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
685 SDRAM_ESDCFG0_VAL: .word 0x00395729
686 SDRAM_PRE_ALL_CMD: .word 0x92120000
687 SDRAM_AUTO_REF_CMD: .word 0xA2120000
688 SDRAM_SET_MODE_REG_CMD: .word 0xB2120000
689 #if SDRAM_SIZE > SZ_64M
690 SDRAM_NORMAL_MODE: .word 0x82226485
692 SDRAM_NORMAL_MODE: .word 0x82126485
694 CS0_CSCRU_VAL: .word 0x0000CC03
695 CS0_CSCRL_VAL: .word 0xA0330D01
696 CS0_CSCRA_VAL: .word 0x00220800
697 CS0_CSCRU_SYNC_VAL: .word 0x23524E80
698 CS0_CSCRL_SYNC_VAL: .word 0x10000D03
699 CS0_CSCRA_SYNC_VAL: .word 0x00720900
700 CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
701 SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
702 DS_DSCR_VAL: .word 0x55555555
703 DS_DSCR7_VAL: .word 0x00005005
704 DS_DSCR8_VAL: .word 0x15555555
705 AIPI1_PSR0_VAL: .word 0x20040304
706 AIPI1_PSR1_VAL: .word 0xDFFBFCFB
708 /*----------------------------------------------------------------------*/
709 /* end of hal_platform_setup.h */
710 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */