1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include CYGBLD_HAL_PLF_DEFS_H // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
54 #define PLATFORM_SETUP1 _platform_setup1
55 #define CYGHWR_HAL_ARM_HAS_MMU
57 #ifdef CYG_HAL_STARTUP_ROMRAM
58 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
61 #define TX27_NAND_PAGE_SIZE 2048
62 #define TX27_NAND_BLKS_PER_PAGE 64
64 #define CYGHWR_HAL_ROM_VADDR 0x0
66 #define DEBUG_LED_BIT 13
67 #define DEBUG_LED_PORT GPIOF_BASE
69 #ifndef CYGOPT_HAL_ARM_TX27_DEBUG
79 #define CYGHWR_LED_MACRO LED_BLINK #\x
80 #define LED_ON bl led_on
81 #define LED_OFF bl led_off
96 // switch user LED (PF13) on STK5
97 ldr r10, DEBUG_LED_PORT
101 ldr r9, [r10, #GPIO_DR]
102 orrne r9, #(1 << DEBUG_LED_BIT) // LED ON
103 biceq r9, #(1 << DEBUG_LED_BIT) // LED OFF
104 str r9, [r10, #GPIO_DR]
123 // initialize GPIO PF13 for LED on STK5
124 ldr r10, DEBUG_LED_PORT
126 ldr r9, [r10, #GPIO_DR]
127 bic r9, #(1 << DEBUG_LED_BIT)
128 str r9, [r10, #GPIO_DR]
130 ldr r9, [r10, #GPIO_OCR1]
131 orr r9, #(3 << (2 * (DEBUG_LED_BIT % 16)))
132 str r9, [r10, #GPIO_OCR1]
134 ldr r9, [r10, #GPIO_GIUS]
135 orr r9, r9, #(1 << DEBUG_LED_BIT)
136 str r9, [r10, #GPIO_GIUS]
138 ldr r9, [r10, #GPIO_DDIR]
139 orr r9, #(1 << DEBUG_LED_BIT)
140 str r9, [r10, #GPIO_DDIR]
144 ldr r10, SOC_CRM_BASE_W
145 ldr r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
146 orr r9, r9, #(1 << 2) /* enable FPM */
147 str r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
149 ldr r9, [r10, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
150 orr r9, r9, #(1 << 24) /* enable WDT clock */
151 str r9, [r10, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
153 /* Wait for clocks to be enabled */
164 /* enable watchdog timeout */
167 /* wait for watchdog to trigger */
170 // This macro represents the initial startup code for the platform
171 // r11 is reserved to contain chip rev info in this file
172 .macro _platform_setup1
173 KARO_TX27_SETUP_START:
174 // invalidate I/D cache/TLB
176 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
177 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
178 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
183 /* configure GPIO PB22 (OSC26M enable) as output high */
186 ldr r9, [r10, #GPIO_OCR2]
187 orr r9, #(3 << (2 * (22 % 16)))
188 str r9, [r10, #GPIO_OCR2]
190 ldr r9, [r10, #GPIO_DR]
191 orr r9, r9, #(1 << 22)
192 str r9, [r10, #GPIO_DR]
194 ldr r9, [r10, #GPIO_GIUS]
195 orr r9, r9, #(1 << 22)
196 str r9, [r10, #GPIO_GIUS]
198 ldr r9, [r10, #GPIO_DDIR]
200 str r9, [r10, #GPIO_DDIR]
204 // setup System Controls
205 ldr r0, SOC_SYSCTRL_BASE_W
207 str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
208 // select 2kpage NAND (NF_FMS), CSD0, CS3
209 mvn r1, #(FMCR_SDCS1_SEL | FMCR_NF_16BIT | FMCR_SLCDC_SEL)
210 str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
214 init_drive_strength_start:
215 @ init_drive_strength
217 // check if sdram has been setup
218 cmp pc, #SDRAM_BASE_ADDR
220 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
221 blo HWInitialise_skip_SDRAM_setup
229 HWInitialise_skip_SDRAM_setup:
231 add r2, r0, #0x800 // 2K window
233 blo Normal_Boot_Continue
235 bhi Normal_Boot_Continue
238 /* Copy image from flash to SDRAM first */
239 ldr r1, MXC_REDBOOT_RAM_START
247 ldr r1, MXC_REDBOOT_RAM_START
260 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
270 /* Code and all data used up to here must fit within the first 2KiB of FLASH ROM! */
274 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
275 mov r1, #TX27_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
276 add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 1st RAM buf. Doesn't change
277 add r4, r0, #0xE00 //r4: NFC register base. Doesn't change
278 ldr r5, MXC_REDBOOT_RAM_START
279 add r6, r5, #REDBOOT_IMAGE_SIZE //r6: end of SDRAM address for copying. Doesn't change
280 add r5, r5, r1 //r5: starting SDRAM address for copying. Updated constantly
282 // enable ECC, disable interrupts
283 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
284 strh r3, [r4, #NAND_FLASH_CONFIG1_REG_OFF]
286 // unlock internal buffer
293 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
303 bl nfc_addr_input //2nd addr cycle
306 bl nfc_addr_input //3rd addr cycle
309 bl nfc_addr_input //4th addr cycle
318 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
321 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
324 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
327 // check for bad block
328 mov r3, r1, lsl #(32-17) // get rid of block number
329 cmp r3, #(TX27_NAND_PAGE_SIZE << (32-17)) // check if not first or second page in block
332 add r9, r0, #TX27_NAND_PAGE_SIZE //r3 -> spare area buf 0
337 // really sucks. Bad block!!!!
340 // even suckier since we already read the first page!
341 sub r5, r5, #TX27_NAND_PAGE_SIZE //rewind 1 page for the sdram pointer
342 sub r1, r1, #TX27_NAND_PAGE_SIZE //rewind 1 page for the flash pointer
344 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
348 add r1, r1, #(TX27_NAND_BLKS_PER_PAGE * TX27_NAND_PAGE_SIZE)
362 bge NAND_Copy_Main_done
364 add r1, r1, #TX27_NAND_PAGE_SIZE
369 Normal_Boot_Continue:
373 ldr r1, SOC_CRM_BASE_W
374 ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
377 str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
379 /* end of NAND clock divider setup */
381 // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
382 ldr r1, =SOC_SYSCTRL_GPCR
387 // Set up a stack [for calling C code]
388 ldr sp, =__startup_stack
397 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
398 orr r1, r1, #7 // enable MMU bit
399 mcr MMU_CP, 0, r1, MMU_Control, c0
403 mov pc, r2 /* Change address spaces */
406 .endm // _platform_setup1
408 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
409 #define PLATFORM_SETUP1
413 ldr r0, SOC_CRM_BASE_W
414 // disable PLL update first
415 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
416 /* clear ARM_SRC & ARM_DIV required as workaround for ENGcm12387 */
417 bic r1, r1, #((1 << 15) | (3 << 12))
418 orr r1, r1, #(1 << 31)
419 #ifdef PLL_REF_CLK_32768HZ
420 orr r1, r1, #(1 << 3) // disable 26MHz osc
422 bic r1, r1, #(1 << 3) // enable 26MHz osc
424 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
427 ldr r1, CRM_MPCTL0_VAL2_W
428 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
431 ldr r1, CRM_SPCTL0_VAL2_W
432 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
434 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
435 #ifdef PLL_REF_CLK_32768HZ
436 // Make sure to use CKIL
437 bic r1, r1, #(3 << 16)
439 orr r1, r1, #(3 << 16) // select 26MHz
441 orr r1, r1, #(0x3 << 18) // SPLL_RESTART | MPLL_RESTART
442 orr r1, r1, #(0x3 << 0) // SPLL_ENABLE | MPLL_ENABLE
443 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
445 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
446 tst r1, #(0x3 << 18) // wait for SPLL/MPLL restart to clear
449 ldr r1, SOC_CRM_CSCR2_W
450 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
452 // Set divider of H264_CLK to zero, NFC to 3.
453 ldr r1, SOC_CRM_PCDR0_W
454 str r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
456 /* Configure PCDR1 */
457 ldr r1, SOC_CRM_PCDR1_W
458 str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
460 // Configure PCCR0 and PCCR1
461 ldr r1, SOC_CRM_PCCR0_W
462 str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
464 ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
466 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
470 ldr r1, SOC_CS0_CTL_BASE_W
471 ldr r2, CS0_CSCRU_VAL
472 str r2, [r1, #CSCRU_OFFSET]
473 ldr r2, CS0_CSCRL_VAL
474 str r2, [r1, #CSCRL_OFFSET]
475 ldr r2, CS0_CSCRA_VAL
476 str r2, [r1, #CSCRA_OFFSET]
479 /* CS0 sync mode setup */
482 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
484 ldr r0, =SOC_CS0_CTL_BASE
485 ldr r1, CS0_CSCRU_SYNC_VAL
486 str r1, [r0, #CSCRU_OFFSET]
487 ldr r1, CS0_CSCRL_SYNC_VAL
488 str r1, [r0, #CSCRL_OFFSET]
489 ldr r1, CS0_CSCRA_SYNC_VAL
490 str r1, [r0, #CSCRA_OFFSET]
491 .endm /* init_cs0_sync */
493 .macro init_cs4 /* ADS board expanded IOs */
494 ldr r1, SOC_CS4_CTL_BASE_W
495 ldr r2, CS4_CSCRU_VAL
496 str r2, [r1, #CSCRU_OFFSET]
497 ldr r2, CS4_CSCRL_VAL
498 str r2, [r1, #CSCRL_OFFSET]
499 ldr r2, CS4_CSCRA_VAL
500 str r2, [r1, #CSCRA_OFFSET]
504 // setup AIPI1 and AIPI2
505 mov r0, #SOC_AIPI1_BASE
506 ldr r1, AIPI1_PSR0_VAL
507 str r1, [r0] /* PSR0 */
508 ldr r2, AIPI1_PSR1_VAL
509 str r2, [r0, #4] /* PSR1 */
510 // set r0 = AIPI2 base
513 str r1, [r0] /* PSR0 */
515 str r2, [r0, #4] /* PSR1 */
519 ldr r0, SOC_MAX_BASE_W
520 add r1, r0, #MAX_SLAVE_PORT1_OFFSET
521 add r2, r0, #MAX_SLAVE_PORT2_OFFSET
522 add r0, r0, #MAX_SLAVE_PORT0_OFFSET
525 ldr r6, SOC_MAX_MPR_VAL /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
526 str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
527 str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
528 str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
529 str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
530 str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
531 str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
534 .macro init_drive_strength
535 ldr r0, SOC_SYSCTRL_BASE_W
537 str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
538 str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
539 str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
541 str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
543 str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
544 .endm // init_drive_strength
546 .macro setup_sdram_ddr
547 // SDRAM controller base address
548 ldr r0, SOC_ESDCTL_BASE_W
549 // base address of SDRAM for SET MODE commands written to SDRAM via address lines
550 mov r2, #SOC_CSD0_BASE
552 mov r1, #(1 << 1) // SDRAM controller reset
553 str r1, [r0, #ESDCTL_ESDMISC]
555 // wait until SDRAMRDY bit is set indicating SDRAM is usable
556 ldr r1, [r0, #ESDCTL_ESDMISC]
560 mov r1, #(1 << 3) @ delay line soft reset
561 str r1, [r0, #ESDCTL_ESDMISC]
563 // wait until SDRAMRDY bit is set indicating SDRAM is usable
564 ldr r1, [r0, #ESDCTL_ESDMISC]
568 mov r1, #(1 << 2) @ enable DDR pipeline
569 str r1, [r0, #ESDCTL_ESDMISC]
571 ldr r1, SDRAM_ESDCFG0_VAL
572 str r1, [r0, #ESDCTL_ESDCFG0]
574 ldr r1, SDRAM_DLY_VAL
575 str r1, [r0, #ESDCTL_ESDCDLY1]
576 str r1, [r0, #ESDCTL_ESDCDLY2]
577 str r1, [r0, #ESDCTL_ESDCDLY3]
578 str r1, [r0, #ESDCTL_ESDCDLY4]
579 str r1, [r0, #ESDCTL_ESDCDLY5]
581 ldr r1, SDRAM_PRE_ALL_CMD
582 str r1, [r0, #ESDCTL_ESDCTL0]
584 str r1, [r2, #(1 << 10)] @ contents of r1 irrelevant, data written via A0-A11
586 ldr r1, SDRAM_AUTO_REF_CMD
587 str r1, [r0, #ESDCTL_ESDCTL0]
588 @ initiate 2 auto refresh cycles
593 ldr r1, SDRAM_SET_MODE_REG_CMD
594 str r1, [r0, #ESDCTL_ESDCTL0]
596 @ address offset for extended mode register
597 add r3, r2, #(2 << 24)
598 @ select drive strength via extended mode register:
599 @ 0=full 1=half 2=quarter 3=3-quarter
600 ldrb r1, [r3, #(0 << 5)]
602 ldrb r1, [r2, #0x033] @ write to SDRAM MODE register (via A0-A12)
604 ldr r1, SDRAM_NORMAL_MODE
605 str r1, [r0, #ESDCTL_ESDCTL0]
608 mov r1, #((1 << 3) | (1 << 2) | (1 << 5))
609 str r1, [r0, #ESDCTL_ESDMISC]
610 .endm // setup_sdram_ddr
612 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
616 mov r9, #(1 << 13) // LED ON
617 str r9, [r10, #GPIO_DR]
623 mov r9, #0 // LED OFF
624 str r9, [r10, #GPIO_DR]
629 strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
630 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
631 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
636 strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
637 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
638 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
642 mov r3, #FDO_PAGE_SPARE_VAL
643 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
649 ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
650 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
652 strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
660 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
661 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
662 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
663 ldr r0, SDRAM_ADDR_MASK
664 ldr r1, MXC_REDBOOT_RAM_START
670 #define PLATFORM_VECTORS _platform_vectors
671 .macro _platform_vectors
675 .globl _KARO_STRUCT_SIZE
677 .word 0 // reserve space structure length
679 .globl _KARO_CECFG_START
682 .word 0 // reserve space for CE configuration
685 .globl _KARO_CECFG_END
690 .ascii "KARO TX27 " __DATE__ " " __TIME__
693 /* SDRAM configuration */
694 #define RA_BITS 2 /* row addr bits - 11 */
695 #define CA_BITS (SDRAM_SIZE / SZ_64M) /* 0-2: col addr bits - 8 3: rsrvd */
696 #define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
697 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
698 #define PWDT 1 /* 0: disabled 1: precharge pwdn
699 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
700 #define FP 0 /* 0: not full page 1: full page */
701 #define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
702 #define PRCT 5 /* 0: disabled *: clks / 2 (0..63) */
703 #define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
704 (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
705 (BL << 7) | (PRCT << 0))
707 /* SDRAM timing definitions */
708 #define SDRAM_CLK 133
709 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
711 .macro CK_VAL, name, clks, offs
716 .set \name, \clks - \offs
723 .macro NS_VAL, name, ns, offs
727 CK_VAL \name, NS_TO_CK(\ns), \offs
731 #if SDRAM_SIZE <= SZ_64M
732 /* MT46H16M32LF-75 */
733 CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
734 CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
735 NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
736 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
737 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
738 NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
739 CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
740 NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
741 NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
742 /* tRC is actually max(tRC,tRFC,tXSR) */
743 NS_VAL tRC, 120, 1 /* 0: 20 *: clks - 1 (0..15) */
745 /* MT46H32M32LF-6 or -75 */
746 NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
747 CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
748 NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
749 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
750 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
751 NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
752 CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
753 NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
754 NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
755 NS_VAL tRC, 138, 1 /* 0: 20 *: clks - 1 (0..15) */
758 #define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
759 (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
760 (tRCD << 4) | (tRC << 0))
762 // All these constants need to be in the first 2KiB of FLASH
763 WDOG_BASE: .word WDOG_BASE_ADDR
764 GPIOB_BASE: .word 0x10015100
765 GPIOF_BASE: .word 0x10015500
766 SDRAM_ADDR_MASK: .word 0xffff0000
767 MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
768 SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
769 SOC_MAX_BASE_W: .word SOC_MAX_BASE
770 SOC_MAX_MPR_VAL: .word 0x00302145
771 SOC_CRM_BASE_W: .word SOC_CRM_BASE
772 CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
773 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
775 #define AHBDIV (MPLL_REF_CLK_kHz * 2 / 3 / 1000 / CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK)
777 #define CSCR_AHB_DIV(n) ((((n) & 3) - 1) << 8)
778 #define CSCR_ARM_DIV(n) ((((n) & 3) - 1) << 12)
779 #define CSCR_ARM_SRC(n) ((!!(n)) << 15)
780 #define CSCR_MCU_SEL(n) ((!!(n)) << 16)
781 #define CSCR_SP_SEL(n) ((!!(n)) << 17)
782 #define CSCR_USB_DIV(n) ((((n) & 7) - 1) << 28)
784 #define MPLL_CLK_DIV(khz) ((MPLL_REF_CLK_kHz * 2 / 3 + (khz) - 1) / (khz) - 1)
785 #define MPLL_CLK_DIV2(khz) ((MPLL_REF_CLK_kHz * 4 / 3 + (khz) - 1) / (khz) - 4)
786 #define SPLL_CLK_DIV(khz) ((SPLL_REF_CLK_kHz + (khz) - 1) / (khz) - 1)
787 #define SPLL_CLK_DIV2(khz) ((SPLL_REF_CLK_kHz * 2 + (khz) - 1) / (khz) - 4)
789 #define PCDR0_SSI2_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 26)
790 #define PCDR0_CLKO_DIV(n) ((((n) - 1) & 0x7) << 22)
791 #define PCDR0_SSI1_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 16)
792 #define PCDR0_H264_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 10)
793 #define PCDR0_NFC_DIV(n) ((MPLL_CLK_DIV(n) & 0xf) << 6)
794 #define PCDR0_MSHC_DIV(pll, n) ((pll##_CLK_DIV(n) & 0x3f) << 0)
795 #define PCDR0_CLKO_EN (1 << 25)
797 #define PCDR1_PER1_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 0)
798 #define PCDR1_PER2_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 8)
799 #define PCDR1_PER3_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 16)
800 #define PCDR1_PER4_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 24)
802 #ifndef PLL_REF_CLK_32768HZ
803 #define MPLL_SRC (1 << 16)
804 #define SPLL_SRC (1 << 17)
805 #define FPM_ENABLE (1 << 2)
807 #define MPLL_SRC (0 << 16)
808 #define SPLL_SRC (0 << 17)
809 #define FPM_ENABLE (1 << 2)
812 SOC_CRM_CSCR2_W: .word 0x03f00003 | \
813 FPM_ENABLE | MPLL_SRC | SPLL_SRC | \
814 CSCR_AHB_DIV(AHBDIV) | \
817 CSCR_ARM_SRC(MPLL_REF_CLK_kHz / 1000 == CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK)
818 SOC_CRM_PCDR0_W: .word PCDR0_SSI2_DIV(MPLL, 66500) | \
819 PCDR0_CLKO_DIV(8) | PCDR0_CLKO_EN | \
820 PCDR0_SSI1_DIV(MPLL, 66500) | \
821 PCDR0_H264_DIV(MPLL, 133000) | \
822 PCDR0_NFC_DIV(16625) | \
823 PCDR0_MSHC_DIV(MPLL, 66500)
824 SOC_CRM_PCDR1_W: .word PCDR1_PER1_DIV(13300) | \
825 PCDR1_PER2_DIV(26600) | \
826 PCDR1_PER3_DIV(66500) | \
827 PCDR1_PER4_DIV(26600)
828 SOC_CRM_PCCR0_W: .word 0x3108480F
829 SOC_CS4_CTL_BASE_W: .word SOC_CS4_CTL_BASE
830 CS4_CSCRU_VAL: .word 0x0000DCF6
831 CS4_CSCRL_VAL: .word 0x444A4541
832 CS4_CSCRA_VAL: .word 0x44443302
833 NFC_BASE_W: .word NFC_BASE
834 SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
835 SDRAM_ESDCFG0_VAL: .word ESDCFGVAL
836 SDRAM_DLY_VAL: .word 0x002c0000
837 SDRAM_PRE_ALL_CMD: .word 0x92120000
838 SDRAM_AUTO_REF_CMD: .word 0xA2120000
839 SDRAM_SET_MODE_REG_CMD: .word 0xB2120000
840 SDRAM_NORMAL_MODE: .word ESDCTLVAL
841 CS0_CSCRU_VAL: .word 0x0000CC03
842 CS0_CSCRL_VAL: .word 0xA0330D01
843 CS0_CSCRA_VAL: .word 0x00220800
844 CS0_CSCRU_SYNC_VAL: .word 0x23524E80
845 CS0_CSCRL_SYNC_VAL: .word 0x10000D03
846 CS0_CSCRA_SYNC_VAL: .word 0x00720900
847 CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
848 SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
849 DS_DSCR_VAL: .word 0x55555555
850 DS_DSCR7_VAL: .word 0x00005005
851 DS_DSCR8_VAL: .word 0x15555555
852 AIPI1_PSR0_VAL: .word 0x20040304
853 AIPI1_PSR1_VAL: .word 0xDFFBFCFB
855 /*----------------------------------------------------------------------*/
856 /* end of hal_platform_setup.h */
857 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */