1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/karo_tx27.h> // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
54 #define PLATFORM_SETUP1 _platform_setup1
55 #define CYGHWR_HAL_ARM_HAS_MMU
57 #ifdef CYG_HAL_STARTUP_ROMRAM
58 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
61 #define TX27_NAND_PAGE_SIZE 2048
62 #define TX27_NAND_BLKS_PER_PAGE 64
64 #define CYGHWR_HAL_ROM_VADDR 0x0
78 #define CYGHWR_LED_MACRO LED_BLINK \x
79 #define LED_ON bl led_on
80 #define LED_OFF bl led_off
96 // switch user LED (PF13) on STK5
101 movne r9, #(1 << 13) // LED ON
102 moveq r9, #0 // LED OFF
103 str r9, [r10, #GPIO_DR]
122 // initialize GPIO PF13 for LED on STK5
125 ldr r9, [r10, #GPIO_GIUS]
126 orr r9, r9, #(1 << 13)
127 str r9, [r10, #GPIO_GIUS]
130 str r9, [r10, #GPIO_DDIR]
132 mov r9, #(3 << (2 * 13))
133 str r9, [r10, #GPIO_OCR1]
136 // This macro represents the initial startup code for the platform
137 // r11 is reserved to contain chip rev info in this file
138 .macro _platform_setup1
139 b KARO_TX27_SETUP_START
144 mov r9, #(1 << 13) // LED ON
145 str r9, [r10, #GPIO_DR]
151 mov r9, #0 // LED OFF
152 str r9, [r10, #GPIO_DR]
157 strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
158 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
159 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
164 strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
165 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
166 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
170 mov r3, #FDO_PAGE_SPARE_VAL
171 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
177 ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
178 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
180 strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
184 KARO_TX27_SETUP_START:
185 // invalidate I/D cache/TLB
187 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
188 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
189 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
194 mov r0, #SDRAM_NON_FLASH_BOOT
195 ldr r1, AVIC_VECTOR0_ADDR_W
196 str r0, [r1] // for checking boot source from nand or sdram
198 // setup System Controls
199 ldr r0, SOC_SYSCTRL_BASE_W
201 str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
202 // select 2kpage NAND (NF_FMS), CSD0, CS3
203 mvn r1, #(FMCR_SDCS1_SEL | FMCR_NF_16BIT | FMCR_SLCDC_SEL)
204 str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
208 init_drive_strength_start:
221 // check if sdram has been setup
222 cmp pc, #SDRAM_BASE_ADDR
224 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
225 blo HWInitialise_skip_SDRAM_setup
232 HWInitialise_skip_SDRAM_setup:
234 add r2, r0, #0x800 // 2K window
236 blo Normal_Boot_Continue
238 bhi Normal_Boot_Continue
241 /* Copy image from flash to SDRAM first */
242 ldr r1, MXC_REDBOOT_ROM_START
250 ldr r1, MXC_REDBOOT_ROM_START
271 mov r0, #NAND_FLASH_BOOT
272 ldr r1, AVIC_VECTOR0_ADDR_W
275 ldr r1, AVIC_VECTOR1_ADDR_W
279 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
280 mov r1, #TX27_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
281 add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 3st RAM buf. Doesn't change
282 add r4, r0, #0xE00 //r4: NFC register base. Doesn't change
283 ldr r5, MXC_REDBOOT_ROM_START
284 add r6, r5, #REDBOOT_IMAGE_SIZE //r6: end of SDRAM address for copying. Doesn't change
285 add r5, r5, r1 //r5: starting SDRAM address for copying. Updated constantly
287 // enable ECC, disable interrupts
288 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
289 strh r3, [r4, #NAND_FLASH_CONFIG1_REG_OFF]
291 //unlock internal buffer
298 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
308 bl nfc_addr_input //2nd addr cycle
311 bl nfc_addr_input //3rd addr cycle
314 bl nfc_addr_input //4th addr cycle
323 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
326 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
329 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
332 // check for bad block
333 mov r3, r1, lsl #(32-17) // get rid of block number
334 cmp r3, #(TX27_NAND_PAGE_SIZE << (32-17)) // check if not first or second page in block
339 add r9, r0, #TX27_NAND_PAGE_SIZE //r3 -> spare area buf 0
344 // really sucks. Bad block!!!!
347 // even suckier since we already read the first page!
348 sub r5, r5, #TX27_NAND_PAGE_SIZE //rewind 1 page for the sdram pointer
349 sub r1, r1, #TX27_NAND_PAGE_SIZE //rewind 1 page for the flash pointer
355 add r1, r1, #(TX27_NAND_BLKS_PER_PAGE*TX27_NAND_PAGE_SIZE)
369 bge NAND_Copy_Main_done
371 add r1, r1, #TX27_NAND_PAGE_SIZE
376 Normal_Boot_Continue:
378 // Code and all data used up to here must fit within the first 2KiB of FLASH ROM!
382 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
383 /* Copy image from flash to SDRAM first */
386 ldr r1, MXC_REDBOOT_ROM_START
388 beq HWInitialise_skip_SDRAM_copy
390 add r2, r0, #REDBOOT_IMAGE_SIZE
398 #endif /* CYG_HAL_STARTUP_ROMRAM */
400 HWInitialise_skip_SDRAM_copy:
407 ldr r1, =(SOC_CRM_BASE)
408 ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
411 ldr r1, =(SOC_CRM_BASE)
412 str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
414 /* end of NAND clock divider setup */
416 // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
417 ldr r1, =(SOC_SYSCTRL_GPCR)
422 // Set up a stack [for calling C code]
423 ldr r1, =__startup_stack
424 ldr r2, =RAM_BANK0_BASE
434 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
435 orr r1, r1, #7 // enable MMU bit
436 mcr MMU_CP, 0, r1, MMU_Control, c0
440 mov pc,r2 /* Change address spaces */
443 .endm // _platform_setup1
445 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
446 #define PLATFORM_SETUP1
450 ldr r0, SOC_CRM_BASE_W
451 // disable MPLL/SPLL first
452 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
454 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
457 ldr r1, CRM_MPCTL0_VAL2_W
458 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
461 ldr r1, CRM_SPCTL0_VAL2_W
462 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
464 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
465 #ifdef PLL_REF_CLK_32768HZ
466 // Make sure to use CKIL
467 bic r1, r1, #(3 << 16)
469 orr r1, r1, #(3 << 16) // select 26MHz
471 orr r1, r1, #0x000C0000 // restart SPLL and MPLL
472 orr r1, r1, #0x00000003 // enable SPLL and MPLL
473 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
475 // add some delay here
481 ldr r2, SOC_CRM_CSCR2_W
482 str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
484 // Set divider of H264_CLK to zero, NFC to 3.
485 ldr r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
486 bic r2, r2, #0x0000FC00
487 str r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
490 /* Configure PCDR1 */
491 ldr r1, SOC_CRM_PCDR1_W
492 str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
494 // Configure PCCR0 and PCCR1
495 ldr r1, SOC_CRM_PCCR0_W
496 str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
498 ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
500 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
501 // make default CLKO to be FCLK
502 ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
503 and r1, r1, #0xFFFFFFE0
505 str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
509 ldr r1, SOC_CS0_CTL_BASE_W
510 ldr r2, CS0_CSCRU_VAL
511 str r2, [r1, #CSCRU_OFFSET]
512 ldr r2, CS0_CSCRL_VAL
513 str r2, [r1, #CSCRL_OFFSET]
514 ldr r2, CS0_CSCRA_VAL
515 str r2, [r1, #CSCRA_OFFSET]
518 /* CS0 sync mode setup */
521 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
523 ldr r0, =SOC_CS0_CTL_BASE
524 ldr r1, CS0_CSCRU_SYNC_VAL
525 str r1, [r0, #CSCRU_OFFSET]
526 ldr r1, CS0_CSCRL_SYNC_VAL
527 str r1, [r0, #CSCRL_OFFSET]
528 ldr r1, CS0_CSCRA_SYNC_VAL
529 str r1, [r0, #CSCRA_OFFSET]
530 .endm /* init_cs0_sync */
532 .macro init_cs4 /* ADS board expanded IOs */
533 ldr r1, SOC_CS4_CTL_BASE_W
534 ldr r2, CS4_CSCRU_VAL
535 str r2, [r1, #CSCRU_OFFSET]
536 ldr r2, CS4_CSCRL_VAL
537 str r2, [r1, #CSCRL_OFFSET]
538 ldr r2, CS4_CSCRA_VAL
539 str r2, [r1, #CSCRA_OFFSET]
543 // setup AIPI1 and AIPI2
544 mov r0, #SOC_AIPI1_BASE
545 ldr r1, AIPI1_PSR0_VAL
546 str r1, [r0] /* PSR0 */
547 ldr r2, AIPI1_PSR1_VAL
548 str r2, [r0, #4] /* PSR1 */
549 // set r0 = AIPI2 base
552 str r1, [r0] /* PSR0 */
554 str r2, [r0, #4] /* PSR1 */
558 ldr r0, SOC_MAX_BASE_W
559 add r1, r0, #MAX_SLAVE_PORT1_OFFSET
560 add r2, r0, #MAX_SLAVE_PORT2_OFFSET
561 add r0, r0, #MAX_SLAVE_PORT0_OFFSET
564 ldr r6, SOC_MAX_MPR_VAL /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
565 str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
566 str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
567 str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
568 str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
569 str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
570 str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
573 .macro init_drive_strength
574 ldr r0, SOC_SYSCTRL_BASE_W
576 str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
577 str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
578 str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
580 str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
582 str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
583 .endm // init_drive_strength
585 .macro setup_sdram_ddr
586 // SDRAM controller base address
587 ldr r0, SOC_ESDCTL_BASE_W
588 // base address of SDRAM for SET MODE commands written to SDRAM via address lines
589 mov r2, #SOC_CSD0_BASE
591 mov r1, #(1 << 3) // delay line soft reset
592 str r1, [r0, #ESDCTL_ESDMISC]
594 // wait until SDRAMRDY bit is set indicating SDRAM is usable
595 ldr r1, [r0, #ESDCTL_ESDMISC]
599 mov r1, #(1 << 2) // enable DDR pipeline
600 str r1, [r0, #ESDCTL_ESDMISC]
602 ldr r1, SDRAM_ESDCFG0_VAL
603 str r1, [r0, #ESDCTL_ESDCFG0]
605 ldr r1, SDRAM_PRE_ALL_CMD
606 str r1, [r0, #ESDCTL_ESDCTL0]
608 str r1, [r2, #(1 << 10)] // contents of r1 irrelevant, data written via A0-A12
609 ldr r1, SDRAM_AUTO_REF_CMD
610 str r1, [r0, #ESDCTL_ESDCTL0]
612 // initiate 8 auto refresh cycles
615 str r1, [r2, #(1 << 10)] // contents of r1 irrelevant, data written via A0-A12
619 ldr r1, SDRAM_SET_MODE_REG_CMD
620 str r1, [r0, #ESDCTL_ESDCTL0]
622 strb r1, [r2, #0x0033] // actually a write to SDRAM MODE register
624 ldr r1, SDRAM_NORMAL_MODE
625 str r1, [r0, #ESDCTL_ESDCTL0]
628 mov r1, #((1 << 3) | (1 << 2))
629 str r1, [r0, #ESDCTL_ESDMISC]
630 .endm // setup_sdram_ddr
634 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
635 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
636 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
637 ldr r0, SDRAM_ADDR_MASK
638 ldr r1, MXC_REDBOOT_ROM_START
646 .ascii "KARO TX27 " __DATE__ " " __TIME__
648 // All these constants need to be in the first 2KiB of FLASH
649 GPIOF_BASE: .word 0x10015500
650 CONST_0xFFF: .word 0xfff
651 SDRAM_ADDR_MASK: .word 0xfff00000
652 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x00100000
653 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
654 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
655 SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
656 SOC_MAX_BASE_W: .word SOC_MAX_BASE
657 SOC_MAX_MPR_VAL: .word 0x00302145
658 SOC_CRM_BASE_W: .word SOC_CRM_BASE
659 CRM_MPCTL0_VAL_W: .word CRM_MPCTL0_VAL
660 CRM_SPCTL0_VAL_W: .word CRM_SPCTL0_VAL
661 CRM_MPCTL0_VAL_27MHZ_W: .word CRM_MPCTL0_VAL_27MHZ
662 CRM_SPCTL0_VAL_27MHZ_W: .word CRM_SPCTL0_VAL_27MHZ
663 SOC_CRM_CSCR_W: .word CRM_CSCR_VAL
664 CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
665 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
666 CRM_MPCTL0_VAL2_27MHZ_W: .word CRM_MPCTL0_VAL2_27MHZ
667 CRM_SPCTL0_VAL2_27MHZ_W: .word CRM_SPCTL0_VAL2_27MHZ
668 SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
669 SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
670 SOC_CRM_PCCR0_W: .word 0x3108480F
671 SOC_CS4_CTL_BASE_W: .word SOC_CS4_CTL_BASE
672 CS4_CSCRU_VAL: .word 0x0000DCF6
673 CS4_CSCRL_VAL: .word 0x444A4541
674 CS4_CSCRA_VAL: .word 0x44443302
675 NFC_BASE_W: .word NFC_BASE
676 SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
677 SDRAM_ESDCFG0_VAL: .word 0x00395728
678 SDRAM_PRE_ALL_CMD: .word 0x92200000
679 SDRAM_AUTO_REF_CMD: .word 0xA2200000
680 SDRAM_SET_MODE_REG_CMD: .word 0xB2200000
681 SDRAM_NORMAL_MODE: .word 0x82124485
682 CS0_CSCRU_VAL: .word 0x0000CC03
683 CS0_CSCRL_VAL: .word 0xA0330D01
684 CS0_CSCRA_VAL: .word 0x00220800
685 CS0_CSCRU_SYNC_VAL: .word 0x23524E80
686 CS0_CSCRL_SYNC_VAL: .word 0x10000D03
687 CS0_CSCRA_SYNC_VAL: .word 0x00720900
688 CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
689 SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
690 DS_DSCR_VAL: .word 0x55555555
691 DS_DSCR7_VAL: .word 0x00005005
692 DS_DSCR8_VAL: .word 0x15555555
693 AIPI1_PSR0_VAL: .word 0x20040304
694 AIPI1_PSR1_VAL: .word 0xDFFBFCFB
696 /*----------------------------------------------------------------------*/
697 /* end of hal_platform_setup.h */
698 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */