packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h

   1 #ifndef CYGONCE_HAL_VAR_INTS_H
   2 #define CYGONCE_HAL_VAR_INTS_H
   3 //==========================================================================
   4 //
   5 //      hal_var_ints.h
   6 //
   7 //      HAL Interrupt and clock support
   8 //
   9 //==========================================================================
  10 //####ECOSGPLCOPYRIGHTBEGIN####
  11 // -------------------------------------------
  12 // This file is part of eCos, the Embedded Configurable Operating System.
  13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  14 //
  15 // eCos is free software; you can redistribute it and/or modify it under
  16 // the terms of the GNU General Public License as published by the Free
  17 // Software Foundation; either version 2 or (at your option) any later version.
  18 //
  19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  22 // for more details.
  23 //
  24 // You should have received a copy of the GNU General Public License along
  25 // with eCos; if not, write to the Free Software Foundation, Inc.,
  26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  27 //
  28 // As a special exception, if other files instantiate templates or use macros
  29 // or inline functions from this file, or you compile this file and link it
  30 // with other works to produce a work based on this file, this file does not
  31 // by itself cause the resulting work to be covered by the GNU General Public
  32 // License. However the source code for this file must still be made available
  33 // in accordance with section (3) of the GNU General Public License.
  34 //
  35 // This exception does not invalidate any other reasons why a work based on
  36 // this file might be covered by the GNU General Public License.
  37 //
  38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  39 // at http://sources.redhat.com/ecos/ecos-license/
  40 // -------------------------------------------
  41 //####ECOSGPLCOPYRIGHTEND####
  42 //==========================================================================
  43
  44 #include <cyg/hal/hal_soc.h>            // registers
  45
  46 #define CYGNUM_HAL_INTERRUPT_GPIO0      0
  47 #define CYGNUM_HAL_INTERRUPT_GPIO1      1
  48 #define CYGNUM_HAL_INTERRUPT_GPIO2      2
  49 #define CYGNUM_HAL_INTERRUPT_GPIO3      3
  50 #define CYGNUM_HAL_INTERRUPT_GPIO4      4
  51 #define CYGNUM_HAL_INTERRUPT_GPIO5      5
  52 #define CYGNUM_HAL_INTERRUPT_GPIO6      6
  53 #define CYGNUM_HAL_INTERRUPT_GPIO7      7
  54 #define CYGNUM_HAL_INTERRUPT_GPIO8      8
  55 #define CYGNUM_HAL_INTERRUPT_GPIO9      9
  56 #define CYGNUM_HAL_INTERRUPT_GPIO10     10
  57 #define CYGNUM_HAL_INTERRUPT_GPIO       11       // Don't use directly!
  58 #define CYGNUM_HAL_INTERRUPT_LCD        12
  59 #define CYGNUM_HAL_INTERRUPT_UDC        13
  60 #define CYGNUM_HAL_INTERRUPT_UART1      15
  61 #define CYGNUM_HAL_INTERRUPT_UART2      16
  62 #define CYGNUM_HAL_INTERRUPT_UART3      17
  63 #define CYGNUM_HAL_INTERRUPT_UART4      17
  64 #define CYGNUM_HAL_INTERRUPT_MCP        18
  65 #define CYGNUM_HAL_INTERRUPT_SSP        19
  66 #define CYGNUM_HAL_INTERRUPT_TIMER0     26
  67 #define CYGNUM_HAL_INTERRUPT_TIMER1     27
  68 #define CYGNUM_HAL_INTERRUPT_TIMER2     28
  69 #define CYGNUM_HAL_INTERRUPT_TIMER3     29
  70 #define CYGNUM_HAL_INTERRUPT_HZ         30
  71 #define CYGNUM_HAL_INTERRUPT_ALARM      31
  72
  73 // GPIO bits 31..11 can generate interrupts as well, but they all
  74 // end up clumped into interrupt signal #11.  Using the symbols
  75 // below allow for detection of these separately.
  76
  77 #define CYGNUM_HAL_INTERRUPT_GPIO11 (32 + 11)
  78 #define CYGNUM_HAL_INTERRUPT_GPIO12 (32 + 12)
  79 #define CYGNUM_HAL_INTERRUPT_GPIO13 (32 + 13)
  80 #define CYGNUM_HAL_INTERRUPT_GPIO14 (32 + 14)
  81 #define CYGNUM_HAL_INTERRUPT_GPIO15 (32 + 15)
  82 #define CYGNUM_HAL_INTERRUPT_GPIO16 (32 + 16)
  83 #define CYGNUM_HAL_INTERRUPT_GPIO17 (32 + 17)
  84 #define CYGNUM_HAL_INTERRUPT_GPIO18 (32 + 18)
  85 #define CYGNUM_HAL_INTERRUPT_GPIO19 (32 + 19)
  86 #define CYGNUM_HAL_INTERRUPT_GPIO20 (32 + 20)
  87 #define CYGNUM_HAL_INTERRUPT_GPIO21 (32 + 21)
  88 #define CYGNUM_HAL_INTERRUPT_GPIO22 (32 + 22)
  89 #define CYGNUM_HAL_INTERRUPT_GPIO23 (32 + 23)
  90 #define CYGNUM_HAL_INTERRUPT_GPIO24 (32 + 24)
  91 #define CYGNUM_HAL_INTERRUPT_GPIO25 (32 + 25)
  92 #define CYGNUM_HAL_INTERRUPT_GPIO26 (32 + 26)
  93 #define CYGNUM_HAL_INTERRUPT_GPIO27 (32 + 27)
  94
  95 #define CYGNUM_HAL_ISR_MIN                              0
  96 #define CYGNUM_HAL_ISR_MAX                              (27 + 32)
  97
  98 #define CYGNUM_HAL_ISR_COUNT                    (CYGNUM_HAL_ISR_MAX + 1)
  99
 100 // The vector used by the Real time clock
 101 #define CYGNUM_HAL_INTERRUPT_RTC                CYGNUM_HAL_INTERRUPT_TIMER0
 102
 103 // The vector used by the Ethernet
 104 #define CYGNUM_HAL_INTERRUPT_ETH                CYGNUM_HAL_INTERRUPT_GPIO0
 105
 106 // method for reading clock interrupt latency
 107 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
 108 externC void hal_clock_latency(cyg_uint32 *);
 109 # define HAL_CLOCK_LATENCY( _pvalue_ )                                  \
 110         hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
 111 #endif
 112
 113 //----------------------------------------------------------------------------
 114 // Reset.
 115 #define HAL_PLATFORM_RESET()                                                                                    \
 116         CYG_MACRO_START                                                                                                         \
 117                                                                                                                                                 \
 118         /* Enable WDT clock */                                                                                          \
 119         writel(readl(SOC_CRM_PCCR1) | (1 << 24), SOC_CRM_PCCR1);                        \
 120         /* Enable FPM */                                                                                                        \
 121         writel(readl(SOC_CRM_CSCR) | (1 << 2), SOC_CRM_CSCR);                           \
 122         HAL_DELAY_US(1000);                                                                                                     \
 123         /* Assert Softreset */                                                                                          \
 124         writew(readw(SOC_WDOG_BASE) & ~(1 << 4), SOC_WDOG_BASE);                        \
 125         /* hang here forever if reset fails */                                                          \
 126         while (1) { }                                                                                                           \
 127         CYG_MACRO_END
 128
 129 // Fallback (never really used)
 130 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
 131
 132 #endif // CYGONCE_HAL_VAR_INTS_H