packages/hal/arm/mx31/3stack/v2_0/src/board_diag.c

   1 /*=============================================================================
   2 //
   3 //      board_diag.c
   4 //
   5 //      HAL diagnostic output code
   6 //
   7 //=============================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //===========================================================================*/
  41
  42 #include <pkgconf/hal.h>
  43
  44 #include <cyg/infra/cyg_type.h>         // base types
  45 #include <cyg/infra/cyg_trac.h>         // tracing macros
  46 #include <cyg/infra/cyg_ass.h>          // assertion macros
  47
  48 #include <cyg/hal/hal_arch.h>           // basic machine info
  49 #include <cyg/hal/hal_intr.h>           // interrupt macros
  50 #include <cyg/hal/hal_io.h>             // IO macros
  51 #include <cyg/hal/hal_diag.h>
  52 #include <cyg/hal/hal_if.h>             // Calling-if API
  53 #include <cyg/hal/drv_api.h>            // driver API
  54 #include <cyg/hal/hal_misc.h>           // Helper functions
  55 #include <cyg/hal/hal_soc.h>            // Hardware definitions
  56 #include <cyg/hal/fsl_board.h>          // Platform specifics
  57
  58 static void cyg_hal_plf_duart_init(void);
  59 extern void cyg_hal_plf_serial_init(void);
  60
  61 #define DUART_WORKAROUND_DELAY(a)    hal_delay_us(a);
  62
  63
  64 void cyg_hal_plf_comms_init(void)
  65 {
  66     static int initialized = 0;
  67
  68     if (initialized)
  69         return;
  70
  71     initialized = 1;
  72
  73     /* Setup GPIO and enable transceiver for UARTs */
  74     cyg_hal_plf_duart_init();
  75     cyg_hal_plf_serial_init();
  76 }
  77
  78 //=============================================================================
  79 // ST16552 DUART driver
  80 //=============================================================================
  81
  82 //-----------------------------------------------------------------------------
  83 // There are two serial ports.
  84 #define CYG_DEV_SERIAL_BASE_A    (BOARD_CS_UART_BASE + 0x0000) // port A
  85 #define CYG_DEV_SERIAL_BASE_B    (BOARD_CS_UART_BASE + 0x8000) // port B
  86
  87 //-----------------------------------------------------------------------------
  88 // Based on 14.7456 MHz xtal
  89 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
  90 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
  91 #define CYG_DEV_SERIAL_BAUD_LSB        0x60
  92 #endif
  93 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
  94 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
  95 #define CYG_DEV_SERIAL_BAUD_LSB        0x30
  96 #endif
  97 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
  98 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
  99 #define CYG_DEV_SERIAL_BAUD_LSB        0x18
 100 #endif
 101 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
 102 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 103 #define CYG_DEV_SERIAL_BAUD_LSB        0x10
 104 #endif
 105 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
 106 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 107 #define CYG_DEV_SERIAL_BAUD_LSB        0x08
 108 #endif
 109
 110 #ifndef CYG_DEV_SERIAL_BAUD_MSB
 111 #error Missing/incorrect serial baud rate defined - CDL error?
 112 #endif
 113
 114 //-----------------------------------------------------------------------------
 115 // Define the serial registers. The board is equipped with a 16552
 116 // serial chip.
 117
 118 #ifdef EXT_UART_x16
 119 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
 120 #define HAL_READ_UINT_UART HAL_READ_UINT16
 121 typedef cyg_uint16 uart_width;
 122 #else  //_x8
 123 typedef cyg_uint8 uart_width;
 124 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
 125 #define HAL_READ_UINT_UART HAL_READ_UINT8
 126 #endif
 127
 128 #define CYG_DEV_SERIAL_RHR   0x00 // receiver buffer register, read, dlab = 0
 129 #define CYG_DEV_SERIAL_THR   0x00 // transmitter holding register, write, dlab = 0
 130 #define CYG_DEV_SERIAL_DLL   0x00 // divisor latch (LS), read/write, dlab = 1
 131 #define CYG_DEV_SERIAL_IER   0x01 // interrupt enable register, read/write, dlab = 0
 132 #define CYG_DEV_SERIAL_DLM   0x01 // divisor latch (MS), read/write, dlab = 1
 133 #define CYG_DEV_SERIAL_IIR   0x02 // interrupt identification register, read, dlab = 0
 134 #define CYG_DEV_SERIAL_FCR   0x02 // fifo control register, write, dlab = 0
 135 #define CYG_DEV_SERIAL_AFR   0x02 // alternate function register, read/write, dlab = 1
 136 #define CYG_DEV_SERIAL_LCR   0x03 // line control register, read/write
 137 #define CYG_DEV_SERIAL_MCR   0x04
 138 #define CYG_DEV_SERIAL_MCR_A 0x04
 139 #define CYG_DEV_SERIAL_MCR_B 0x04
 140 #define CYG_DEV_SERIAL_LSR   0x05 // line status register, read
 141 #define CYG_DEV_SERIAL_MSR   0x06 // modem status register, read
 142 #define CYG_DEV_SERIAL_SCR   0x07 // scratch pad register
 143
 144 // The interrupt enable register bits.
 145 #define SIO_IER_ERDAI   0x01            // enable received data available irq
 146 #define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
 147 #define SIO_IER_ELSI    0x04            // enable receiver line status irq
 148 #define SIO_IER_EMSI    0x08            // enable modem status interrupt
 149
 150 // The interrupt identification register bits.
 151 #define SIO_IIR_IP      0x01            // 0 if interrupt pending
 152 #define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
 153 #define ISR_Tx          0x02
 154 #define ISR_Rx          0x04
 155
 156 // The line status register bits.
 157 #define SIO_LSR_DR      0x01            // data ready
 158 #define SIO_LSR_OE      0x02            // overrun error
 159 #define SIO_LSR_PE      0x04            // parity error
 160 #define SIO_LSR_FE      0x08            // framing error
 161 #define SIO_LSR_BI      0x10            // break interrupt
 162 #define SIO_LSR_THRE    0x20            // transmitter holding register empty
 163 #define SIO_LSR_TEMT    0x40            // transmitter register empty
 164 #define SIO_LSR_ERR     0x80            // any error condition
 165
 166 // The modem status register bits.
 167 #define SIO_MSR_DCTS    0x01            // delta clear to send
 168 #define SIO_MSR_DDSR    0x02            // delta data set ready
 169 #define SIO_MSR_TERI    0x04            // trailing edge ring indicator
 170 #define SIO_MSR_DDCD    0x08            // delta data carrier detect
 171 #define SIO_MSR_CTS     0x10            // clear to send
 172 #define SIO_MSR_DSR     0x20            // data set ready
 173 #define SIO_MSR_RI      0x40            // ring indicator
 174 #define SIO_MSR_DCD     0x80            // data carrier detect
 175
 176 // The line control register bits.
 177 #define SIO_LCR_WLS0   0x01             // word length select bit 0
 178 #define SIO_LCR_WLS1   0x02             // word length select bit 1
 179 #define SIO_LCR_STB    0x04             // number of stop bits
 180 #define SIO_LCR_PEN    0x08             // parity enable
 181 #define SIO_LCR_EPS    0x10             // even parity select
 182 #define SIO_LCR_SP     0x20             // stick parity
 183 #define SIO_LCR_SB     0x40             // set break
 184 #define SIO_LCR_DLAB   0x80             // divisor latch access bit
 185
 186 // The FIFO control register
 187 #define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
 188 #define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
 189 #define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
 190
 191 //-----------------------------------------------------------------------------
 192
 193 typedef struct {
 194     uart_width* base;
 195     cyg_int32 msec_timeout;
 196     int isr_vector;
 197 } channel_data_t;
 198
 199 static channel_data_t channels[] = {
 200 #if CYGHWR_HAL_ARM_DUART_UARTA != 0
 201     {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
 202 #endif
 203 #if CYGHWR_HAL_ARM_DUART_UARTB != 0
 204     {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
 205 #endif
 206 };
 207
 208 //-----------------------------------------------------------------------------
 209
 210 static void init_duart_channel(channel_data_t* __ch_data)
 211 {
 212     uart_width* base = __ch_data->base;
 213     uart_width lcr;
 214
 215     // 8-1-no parity.
 216     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
 217                         SIO_LCR_WLS0 | SIO_LCR_WLS1);
 218     DUART_WORKAROUND_DELAY(50);
 219     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 220     lcr |= SIO_LCR_DLAB;
 221     DUART_WORKAROUND_DELAY(50);
 222     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 223     DUART_WORKAROUND_DELAY(50);
 224     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
 225     DUART_WORKAROUND_DELAY(50);
 226     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
 227     lcr &= ~SIO_LCR_DLAB;
 228     DUART_WORKAROUND_DELAY(50);
 229     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 230     DUART_WORKAROUND_DELAY(50);
 231     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07);  // Enable & clear FIFO
 232 }
 233
 234 //#define x_debug_uart_log_buf
 235 #ifdef x_debug_uart_log_buf
 236 #define x_DIAG_BUFSIZE 2048
 237 static char __x_log_buf[x_DIAG_BUFSIZE];
 238 static int x_diag_bp = 0;
 239 #endif
 240
 241 void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
 242 {
 243     uart_width* base = ((channel_data_t*)__ch_data)->base;
 244     uart_width lsr;
 245
 246 #ifdef x_debug_uart_log_buf
 247     __x_log_buf[x_diag_bp++] = c;
 248 #endif
 249     CYGARC_HAL_SAVE_GP();
 250
 251     do {
 252         HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 253     } while ((lsr & SIO_LSR_THRE) == 0);
 254
 255     DUART_WORKAROUND_DELAY(50);
 256     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
 257
 258     // Hang around until the character has been safely sent.
 259     do {
 260         HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 261     } while ((lsr & SIO_LSR_THRE) == 0);
 262
 263     CYGARC_HAL_RESTORE_GP();
 264 }
 265
 266 static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
 267 {
 268     uart_width* base = ((channel_data_t*)__ch_data)->base;
 269     uart_width lsr, ch16;
 270
 271     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 272     if ((lsr & SIO_LSR_DR) == 0)
 273         return false;
 274
 275     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
 276
 277     *ch = (cyg_uint8) (ch16 & 0x00FF);
 278
 279     return true;
 280 }
 281
 282 cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
 283 {
 284     cyg_uint8 ch;
 285
 286     CYGARC_HAL_SAVE_GP();
 287
 288     while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
 289
 290     CYGARC_HAL_RESTORE_GP();
 291     return ch;
 292 }
 293
 294 static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
 295                                     cyg_uint32 __len)
 296 {
 297     CYGARC_HAL_SAVE_GP();
 298
 299     while (__len-- > 0)
 300         cyg_hal_plf_duart_putc(__ch_data, *__buf++);
 301
 302     CYGARC_HAL_RESTORE_GP();
 303 }
 304
 305 static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
 306                                    cyg_uint32 __len)
 307 {
 308     CYGARC_HAL_SAVE_GP();
 309
 310     while (__len-- > 0)
 311         *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
 312
 313     CYGARC_HAL_RESTORE_GP();
 314 }
 315
 316 cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
 317 {
 318     int delay_count;
 319     channel_data_t* chan = (channel_data_t*)__ch_data;
 320     cyg_bool res;
 321
 322     CYGARC_HAL_SAVE_GP();
 323
 324     delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 325     for (;;) {
 326         res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
 327         if (res || 0 == delay_count--)
 328             break;
 329
 330         CYGACC_CALL_IF_DELAY_US(100);
 331     }
 332
 333     CYGARC_HAL_RESTORE_GP();
 334     return res;
 335 }
 336
 337 static int cyg_hal_plf_duart_control(void *__ch_data,
 338                                      __comm_control_cmd_t __func, ...)
 339 {
 340     static int irq_state = 0;
 341     channel_data_t* chan = (channel_data_t*)__ch_data;
 342     uart_width ier;
 343     int ret = 0;
 344
 345     CYGARC_HAL_SAVE_GP();
 346
 347     switch (__func) {
 348     case __COMMCTL_IRQ_ENABLE:
 349         HAL_INTERRUPT_UNMASK(chan->isr_vector);
 350         HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
 351         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 352         ier |= SIO_IER_ERDAI;
 353         HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 354         irq_state = 1;
 355         break;
 356     case __COMMCTL_IRQ_DISABLE:
 357         ret = irq_state;
 358         irq_state = 0;
 359         HAL_INTERRUPT_MASK(chan->isr_vector);
 360         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 361         ier &= ~SIO_IER_ERDAI;
 362         HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 363         break;
 364     case __COMMCTL_DBG_ISR_VECTOR:
 365         ret = chan->isr_vector;
 366         break;
 367     case __COMMCTL_SET_TIMEOUT:
 368         {
 369             va_list ap;
 370
 371             va_start(ap, __func);
 372
 373             ret = chan->msec_timeout;
 374             chan->msec_timeout = va_arg(ap, cyg_uint32);
 375
 376             va_end(ap);
 377         }
 378         break;
 379     default:
 380         break;
 381     }
 382     CYGARC_HAL_RESTORE_GP();
 383     return ret;
 384 }
 385
 386 static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
 387                                  CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
 388 {
 389     channel_data_t* chan = (channel_data_t*)__ch_data;
 390     uart_width _iir;
 391     int res = 0;
 392     CYGARC_HAL_SAVE_GP();
 393
 394     HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
 395     _iir &= SIO_IIR_ID_MASK;
 396
 397     *__ctrlc = 0;
 398     if ( ISR_Rx == _iir ) {
 399         uart_width c, lsr;
 400         cyg_uint8 c8;
 401         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
 402         if (lsr & SIO_LSR_DR) {
 403
 404             HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
 405
 406             c8 = (cyg_uint8) (c & 0x00FF);
 407
 408             if (cyg_hal_is_break( &c8 , 1 ))
 409                 *__ctrlc = 1;
 410         }
 411
 412         // Acknowledge the interrupt
 413         HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
 414         res = CYG_ISR_HANDLED;
 415     }
 416
 417     CYGARC_HAL_RESTORE_GP();
 418     return res;
 419 }
 420
 421 static void cyg_hal_plf_duart_init(void)
 422 {
 423     hal_virtual_comm_table_t* comm;
 424     int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 425     int i;
 426
 427     // Init channels
 428 #define NUMOF(x) (sizeof(x)/sizeof(x[0]))
 429     for (i = 0;  i < NUMOF(channels);  i++) {
 430         HAL_INTERRUPT_MASK(channels[i].isr_vector);
 431         init_duart_channel(&channels[i]);
 432         CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
 433         comm = CYGACC_CALL_IF_CONSOLE_PROCS();
 434         CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
 435         CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
 436         CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
 437         CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
 438         CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
 439         CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
 440         CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
 441         CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
 442     }
 443
 444     // Restore original console
 445     CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
 446 }
 447
 448 //=============================================================================
 449 // Compatibility with older stubs
 450 //=============================================================================
 451
 452 //=============================================================================
 453 // Compatibility with older stubs
 454 //=============================================================================
 455
 456 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 457
 458 #include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
 459
 460 #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
 461 #define __BASE   CMA101_DUARTA
 462 #define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_A
 463 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
 464 #define __BASE   CMA101_DUARTB
 465 #define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_B
 466 #endif
 467
 468 #ifdef __BASE
 469
 470 #ifdef CYGSEM_HAL_ROM_MONITOR
 471 #define CYG_HAL_STARTUP_ROM
 472 #define CYG_HAL_STARTUP_ROMRAM
 473 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 474 #endif
 475
 476 #if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 477 #define HAL_DIAG_USES_HARDWARE
 478 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
 479 #define HAL_DIAG_USES_HARDWARE
 480 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
 481 #define HAL_DIAG_USES_HARDWARE
 482 #endif
 483
 484 static channel_data_t channel = {
 485     (uart_width*) _BASE, 0, 0
 486 };
 487
 488 #ifdef HAL_DIAG_USES_HARDWARE
 489
 490 void hal_diag_init(void)
 491 {
 492     static int init = 0;
 493     char *msg = "\n\rARM eCos\n\r";
 494     uart_width lcr;
 495
 496     if (init++) return;
 497
 498     init_duart_channel(&channel);
 499
 500     while (*msg) hal_diag_write_char(*msg++);
 501 }
 502
 503 #ifdef DEBUG_DIAG
 504 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 505 #define DIAG_BUFSIZE 32
 506 #else
 507 #define DIAG_BUFSIZE 2048
 508 #endif
 509 static char diag_buffer[DIAG_BUFSIZE];
 510 static int diag_bp = 0;
 511 #endif
 512
 513 void hal_diag_write_char(char c)
 514 {
 515     uart_width lsr;
 516
 517     hal_diag_init();
 518
 519     cyg_hal_plf_duart_putc(&channel, c)
 520
 521 #ifdef DEBUG_DIAG
 522     diag_buffer[diag_bp++] = c;
 523     if (diag_bp == DIAG_BUFSIZE) {
 524         while (1) ;
 525         diag_bp = 0;
 526     }
 527 #endif
 528 }
 529
 530 void hal_diag_read_char(char *c)
 531 {
 532     *c = cyg_hal_plf_duart_getc(&channel);
 533 }
 534
 535 #else // HAL_DIAG relies on GDB
 536
 537 // Initialize diag port - assume GDB channel is already set up
 538 void hal_diag_init(void)
 539 {
 540     if (0) init_duart_channel(&channel); // avoid warning
 541 }
 542
 543 // Actually send character down the wire
 544 static void hal_diag_write_char_serial(char c)
 545 {
 546     cyg_hal_plf_duart_putc(&channel, c);
 547 }
 548
 549 static bool hal_diag_read_serial(char *c)
 550 {
 551     long timeout = 1000000000;  // A long time...
 552
 553     while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
 554         if (0 == --timeout) return false;
 555
 556     return true;
 557 }
 558
 559 void hal_diag_read_char(char *c)
 560 {
 561     while (!hal_diag_read_serial(c)) ;
 562 }
 563
 564 void hal_diag_write_char(char c)
 565 {
 566     static char line[100];
 567     static int pos = 0;
 568
 569     // No need to send CRs
 570     if (c == '\r') return;
 571
 572     line[pos++] = c;
 573
 574     if (c == '\n' || pos == sizeof(line)) {
 575         CYG_INTERRUPT_STATE old;
 576
 577         // Disable interrupts. This prevents GDB trying to interrupt us
 578         // while we are in the middle of sending a packet. The serial
 579         // receive interrupt will be seen when we re-enable interrupts
 580         // later.
 581
 582 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 583         CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
 584 #else
 585         HAL_DISABLE_INTERRUPTS(old);
 586 #endif
 587
 588         while (1) {
 589             static char hex[] = "0123456789ABCDEF";
 590             cyg_uint8 csum = 0;
 591             int i;
 592             char c1;
 593
 594             hal_diag_write_char_serial('$');
 595             hal_diag_write_char_serial('O');
 596             csum += 'O';
 597             for (i = 0; i < pos; i++) {
 598                 char ch = line[i];
 599                 char h = hex[(ch>>4)&0xF];
 600                 char l = hex[ch&0xF];
 601                 hal_diag_write_char_serial(h);
 602                 hal_diag_write_char_serial(l);
 603                 csum += h;
 604                 csum += l;
 605             }
 606             hal_diag_write_char_serial('#');
 607             hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
 608             hal_diag_write_char_serial(hex[csum&0xF]);
 609
 610             // Wait for the ACK character '+' from GDB here and handle
 611             // receiving a ^C instead.  This is the reason for this clause
 612             // being a loop.
 613             if (!hal_diag_read_serial(&c1))
 614                 continue;   // No response - try sending packet again
 615
 616             if ( c1 == '+' )
 617                 break;          // a good acknowledge
 618
 619 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 620             cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
 621             if ( c1 == 3 ) {
 622                 // Ctrl-C: breakpoint.
 623                 cyg_hal_gdb_interrupt (__builtin_return_address(0));
 624                 break;
 625             }
 626 #endif
 627             // otherwise, loop round again
 628         }
 629
 630         pos = 0;
 631
 632         // And re-enable interrupts
 633 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 634         CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
 635 #else
 636         HAL_RESTORE_INTERRUPTS(old);
 637 #endif
 638
 639     }
 640 }
 641 #endif
 642
 643 #endif // __BASE
 644
 645 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 646
 647 /*---------------------------------------------------------------------------*/