1 //==========================================================================
5 // HAL misc board support code for the board
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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30 // License. However the source code for this file must still be made available
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
42 #include <pkgconf/hal.h>
43 #include <pkgconf/system.h>
45 #include CYGBLD_HAL_PLATFORM_H
47 #include <cyg/infra/cyg_type.h> // base types
48 #include <cyg/infra/cyg_trac.h> // tracing macros
49 #include <cyg/infra/cyg_ass.h> // assertion macros
51 #include <cyg/hal/hal_io.h> // IO macros
52 #include <cyg/hal/hal_arch.h> // Register state info
53 #include <cyg/hal/hal_diag.h>
54 #include <cyg/hal/hal_intr.h> // Interrupt names
55 #include <cyg/hal/hal_cache.h>
56 #include <cyg/hal/hal_soc.h> // Hardware definitions
57 #include <cyg/hal/fsl_board.h> // Platform specifics
59 #include <cyg/infra/diag.h> // diag_printf
61 // All the MM table layout is here:
62 #include <cyg/hal/hal_mm.h>
64 externC void* memset(void *, int, size_t);
66 void hal_mmu_init(void)
68 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
72 * Set the TTB register
74 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
77 * Set the Domain Access Control Register
79 i = ARM_ACCESS_DACR_DEFAULT;
80 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
83 * First clear all TT entries - ie Set them to Faulting
85 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
87 /* Actual Virtual Size Attributes Function */
88 /* Base Base MB cached? buffered? access permissions */
89 /* xxx00000 xxx00000 */
90 X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
91 X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
92 X_ARM_MMU_SECTION(0x43F, 0x43F, 0x3C1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
93 X_ARM_MMU_SECTION(0x800, 0x000, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
94 X_ARM_MMU_SECTION(0x800, 0x800, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
95 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
96 X_ARM_MMU_SECTION(0xB40, 0xB40, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
97 X_ARM_MMU_SECTION(0xB50, 0xB50, 0x8, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PSRAM */
98 X_ARM_MMU_SECTION(0xB60, 0xB60, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
99 X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EIM control*/
103 // Platform specific initialization
106 unsigned int g_clock_src;
107 extern int g_board_type;
109 void plf_hardware_init(void)
111 unsigned long val = readl(CCM_BASE_ADDR + CLKCTL_CCMR);
114 if ((val & 0x6) == 0x4) {
115 g_clock_src = FREQ_26MHZ;
116 } else if ((val & 0x6) == 0x2) {
117 g_clock_src = FREQ_32768HZ;
120 /* Reset interrupt status reg */
121 writew(0x1F, PBC_INT_REST);
122 writew(0x00, PBC_INT_REST);
123 writew(0xFFFF, PBC_INT_MASK);
125 writel(0x1210, IOMUXC_BASE_ADDR + 0x80);
127 writel(0x01220100, IOMUXC_BASE_ADDR + 0x148);
128 reg = readl(GPIO3_BASE_ADDR + 0x4);
130 writel(reg, GPIO3_BASE_ADDR + 0x4);
131 reg = readl(GPIO3_BASE_ADDR);
133 writel(reg, GPIO3_BASE_ADDR);
135 g_board_type = BOARD_TYPE_3STACK;
138 #include CYGHWR_MEMORY_LAYOUT_H
140 typedef void code_fun(void);
142 void board_program_new_stack(void *func)
144 register CYG_ADDRESS stack_ptr asm("sp");
145 register CYG_ADDRESS old_stack asm("r4");
146 register code_fun *new_func asm("r0");
147 old_stack = stack_ptr;
148 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
149 new_func = (code_fun*)func;
151 stack_ptr = old_stack;
154 static void display_clock_src(void)
157 if (g_clock_src == FREQ_27MHZ) {
158 diag_printf("Clock input is 27 MHz");
159 } else if (g_clock_src == FREQ_26MHZ) {
160 diag_printf("Clock input is 26 MHz");
161 } else if (g_clock_src == FREQ_32768HZ) {
162 diag_printf("Clock input is 32KHz");
164 diag_printf("Unknown clock input source. Something is wrong!");
167 RedBoot_init(display_clock_src, RedBoot_INIT_LAST);
169 // ------------------------------------------------------------------------