packages/hal/arm/mx31/ads/v2_0/src/board_diag.c

   1 /*=============================================================================
   2 //
   3 //      board_diag.c
   4 //
   5 //      HAL diagnostic output code
   6 //
   7 //=============================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //===========================================================================*/
  41
  42 #include <pkgconf/hal.h>
  43
  44 #include <cyg/infra/cyg_type.h>         // base types
  45 #include <cyg/infra/cyg_trac.h>         // tracing macros
  46 #include <cyg/infra/cyg_ass.h>          // assertion macros
  47
  48 #include <cyg/hal/hal_arch.h>           // basic machine info
  49 #include <cyg/hal/hal_intr.h>           // interrupt macros
  50 #include <cyg/hal/hal_io.h>             // IO macros
  51 #include <cyg/hal/hal_diag.h>
  52 #include <cyg/hal/hal_if.h>             // Calling-if API
  53 #include <cyg/hal/drv_api.h>            // driver API
  54 #include <cyg/hal/hal_misc.h>           // Helper functions
  55 #include <cyg/hal/hal_soc.h>            // Hardware definitions
  56 #include <cyg/hal/fsl_board.h>          // Platform specifics
  57
  58 static void cyg_hal_plf_duart_init(void);
  59 extern void cyg_hal_plf_serial_init(void);
  60
  61 #define DUART_WORKAROUND_DELAY(a)   \
  62 do {                                \
  63     if (BOARD_PBC_VERSION < 7)      \
  64         hal_delay_us(a);            \
  65 } while (0)
  66
  67 void cyg_hal_plf_comms_init(void)
  68 {
  69     static int initialized = 0;
  70
  71     if (initialized)
  72         return;
  73
  74     initialized = 1;
  75
  76     /* Setup GPIO and enable transceiver for UARTs */
  77     cyg_hal_plf_duart_init();
  78     cyg_hal_plf_serial_init();
  79 }
  80
  81 //=============================================================================
  82 // ST16552 DUART driver
  83 //=============================================================================
  84
  85 //-----------------------------------------------------------------------------
  86 // There are two serial ports.
  87 #define CYG_DEV_SERIAL_BASE_A    (BOARD_CS_UART_BASE + 0x0000) // port A
  88 #define CYG_DEV_SERIAL_BASE_B    (BOARD_CS_UART_BASE + 0x0010) // port B
  89
  90 //-----------------------------------------------------------------------------
  91 // Based on 14.7456 MHz xtal
  92 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
  93 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
  94 #define CYG_DEV_SERIAL_BAUD_LSB        0x60
  95 #endif
  96 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
  97 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
  98 #define CYG_DEV_SERIAL_BAUD_LSB        0x30
  99 #endif
 100 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
 101 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 102 #define CYG_DEV_SERIAL_BAUD_LSB        0x18
 103 #endif
 104 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
 105 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 106 #define CYG_DEV_SERIAL_BAUD_LSB        0x10
 107 #endif
 108 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
 109 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 110 #define CYG_DEV_SERIAL_BAUD_LSB        0x08
 111 #endif
 112
 113 #ifndef CYG_DEV_SERIAL_BAUD_MSB
 114 #error Missing/incorrect serial baud rate defined - CDL error?
 115 #endif
 116
 117 //-----------------------------------------------------------------------------
 118 // Define the serial registers. The board is equipped with a 16552
 119 // serial chip.
 120
 121 #ifdef EXT_UART_x16
 122 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
 123 #define HAL_READ_UINT_UART HAL_READ_UINT16
 124 typedef cyg_uint16 uart_width;
 125 #else  //_x8
 126 typedef cyg_uint8 uart_width;
 127 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
 128 #define HAL_READ_UINT_UART HAL_READ_UINT8
 129 #endif
 130
 131 #define CYG_DEV_SERIAL_RHR   0x00 // receiver buffer register, read, dlab = 0
 132 #define CYG_DEV_SERIAL_THR   0x00 // transmitter holding register, write, dlab = 0
 133 #define CYG_DEV_SERIAL_DLL   0x00 // divisor latch (LS), read/write, dlab = 1
 134 #define CYG_DEV_SERIAL_IER   0x01 // interrupt enable register, read/write, dlab = 0
 135 #define CYG_DEV_SERIAL_DLM   0x01 // divisor latch (MS), read/write, dlab = 1
 136 #define CYG_DEV_SERIAL_IIR   0x02 // interrupt identification register, read, dlab = 0
 137 #define CYG_DEV_SERIAL_FCR   0x02 // fifo control register, write, dlab = 0
 138 #define CYG_DEV_SERIAL_AFR   0x02 // alternate function register, read/write, dlab = 1
 139 #define CYG_DEV_SERIAL_LCR   0x03 // line control register, read/write
 140 #define CYG_DEV_SERIAL_MCR   0x04
 141 #define CYG_DEV_SERIAL_MCR_A 0x04
 142 #define CYG_DEV_SERIAL_MCR_B 0x04
 143 #define CYG_DEV_SERIAL_LSR   0x05 // line status register, read
 144 #define CYG_DEV_SERIAL_MSR   0x06 // modem status register, read
 145 #define CYG_DEV_SERIAL_SCR   0x07 // scratch pad register
 146
 147 // The interrupt enable register bits.
 148 #define SIO_IER_ERDAI   0x01            // enable received data available irq
 149 #define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
 150 #define SIO_IER_ELSI    0x04            // enable receiver line status irq
 151 #define SIO_IER_EMSI    0x08            // enable modem status interrupt
 152
 153 // The interrupt identification register bits.
 154 #define SIO_IIR_IP      0x01            // 0 if interrupt pending
 155 #define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
 156 #define ISR_Tx          0x02
 157 #define ISR_Rx          0x04
 158
 159 // The line status register bits.
 160 #define SIO_LSR_DR      0x01            // data ready
 161 #define SIO_LSR_OE      0x02            // overrun error
 162 #define SIO_LSR_PE      0x04            // parity error
 163 #define SIO_LSR_FE      0x08            // framing error
 164 #define SIO_LSR_BI      0x10            // break interrupt
 165 #define SIO_LSR_THRE    0x20            // transmitter holding register empty
 166 #define SIO_LSR_TEMT    0x40            // transmitter register empty
 167 #define SIO_LSR_ERR     0x80            // any error condition
 168
 169 // The modem status register bits.
 170 #define SIO_MSR_DCTS    0x01            // delta clear to send
 171 #define SIO_MSR_DDSR    0x02            // delta data set ready
 172 #define SIO_MSR_TERI    0x04            // trailing edge ring indicator
 173 #define SIO_MSR_DDCD    0x08            // delta data carrier detect
 174 #define SIO_MSR_CTS     0x10            // clear to send
 175 #define SIO_MSR_DSR     0x20            // data set ready
 176 #define SIO_MSR_RI      0x40            // ring indicator
 177 #define SIO_MSR_DCD     0x80            // data carrier detect
 178
 179 // The line control register bits.
 180 #define SIO_LCR_WLS0   0x01             // word length select bit 0
 181 #define SIO_LCR_WLS1   0x02             // word length select bit 1
 182 #define SIO_LCR_STB    0x04             // number of stop bits
 183 #define SIO_LCR_PEN    0x08             // parity enable
 184 #define SIO_LCR_EPS    0x10             // even parity select
 185 #define SIO_LCR_SP     0x20             // stick parity
 186 #define SIO_LCR_SB     0x40             // set break
 187 #define SIO_LCR_DLAB   0x80             // divisor latch access bit
 188
 189 // The FIFO control register
 190 #define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
 191 #define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
 192 #define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
 193
 194 //-----------------------------------------------------------------------------
 195
 196 typedef struct {
 197     uart_width* base;
 198     cyg_int32 msec_timeout;
 199     int isr_vector;
 200 } channel_data_t;
 201
 202 static channel_data_t channels[] = {
 203 #if CYGHWR_HAL_ARM_DUART_UARTA != 0
 204     {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
 205 #endif
 206 #if CYGHWR_HAL_ARM_DUART_UARTB != 0
 207     {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
 208 #endif
 209 };
 210
 211 //-----------------------------------------------------------------------------
 212
 213 static void init_duart_channel(channel_data_t* __ch_data)
 214 {
 215     uart_width* base = __ch_data->base;
 216     uart_width lcr;
 217
 218     // 8-1-no parity.
 219     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
 220                         SIO_LCR_WLS0 | SIO_LCR_WLS1);
 221     DUART_WORKAROUND_DELAY(50);
 222     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 223     lcr |= SIO_LCR_DLAB;
 224     DUART_WORKAROUND_DELAY(50);
 225     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 226     DUART_WORKAROUND_DELAY(50);
 227     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
 228     DUART_WORKAROUND_DELAY(50);
 229     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
 230     lcr &= ~SIO_LCR_DLAB;
 231     DUART_WORKAROUND_DELAY(50);
 232     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 233     DUART_WORKAROUND_DELAY(50);
 234     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07);  // Enable & clear FIFO
 235 }
 236
 237 //#define x_debug_uart_log_buf
 238 #ifdef x_debug_uart_log_buf
 239 #define x_DIAG_BUFSIZE 2048
 240 static char __x_log_buf[x_DIAG_BUFSIZE];
 241 static int x_diag_bp = 0;
 242 #endif
 243
 244 void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
 245 {
 246     uart_width* base = ((channel_data_t*)__ch_data)->base;
 247     uart_width lsr;
 248
 249 #ifdef x_debug_uart_log_buf
 250     __x_log_buf[x_diag_bp++] = c;
 251 #endif
 252     CYGARC_HAL_SAVE_GP();
 253
 254     do {
 255         HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 256     } while ((lsr & SIO_LSR_THRE) == 0);
 257
 258     DUART_WORKAROUND_DELAY(50);
 259     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
 260
 261     // Hang around until the character has been safely sent.
 262     do {
 263         HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 264     } while ((lsr & SIO_LSR_THRE) == 0);
 265
 266     CYGARC_HAL_RESTORE_GP();
 267 }
 268
 269 static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
 270 {
 271     uart_width* base = ((channel_data_t*)__ch_data)->base;
 272     uart_width lsr, ch16;
 273
 274     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 275     if ((lsr & SIO_LSR_DR) == 0)
 276         return false;
 277
 278     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
 279
 280     *ch = (cyg_uint8) (ch16 & 0x00FF);
 281
 282     return true;
 283 }
 284
 285 cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
 286 {
 287     cyg_uint8 ch;
 288
 289     CYGARC_HAL_SAVE_GP();
 290
 291     while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
 292
 293     CYGARC_HAL_RESTORE_GP();
 294     return ch;
 295 }
 296
 297 static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
 298                                     cyg_uint32 __len)
 299 {
 300     CYGARC_HAL_SAVE_GP();
 301
 302     while (__len-- > 0)
 303         cyg_hal_plf_duart_putc(__ch_data, *__buf++);
 304
 305     CYGARC_HAL_RESTORE_GP();
 306 }
 307
 308 static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
 309                                    cyg_uint32 __len)
 310 {
 311     CYGARC_HAL_SAVE_GP();
 312
 313     while (__len-- > 0)
 314         *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
 315
 316     CYGARC_HAL_RESTORE_GP();
 317 }
 318
 319 cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
 320 {
 321     int delay_count;
 322     channel_data_t* chan = (channel_data_t*)__ch_data;
 323     cyg_bool res;
 324
 325     CYGARC_HAL_SAVE_GP();
 326
 327     delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 328     for (;;) {
 329         res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
 330         if (res || 0 == delay_count--)
 331             break;
 332
 333         CYGACC_CALL_IF_DELAY_US(100);
 334     }
 335
 336     CYGARC_HAL_RESTORE_GP();
 337     return res;
 338 }
 339
 340 static int cyg_hal_plf_duart_control(void *__ch_data,
 341                                      __comm_control_cmd_t __func, ...)
 342 {
 343     static int irq_state = 0;
 344     channel_data_t* chan = (channel_data_t*)__ch_data;
 345     uart_width ier;
 346     int ret = 0;
 347
 348     CYGARC_HAL_SAVE_GP();
 349
 350     switch (__func) {
 351     case __COMMCTL_IRQ_ENABLE:
 352         HAL_INTERRUPT_UNMASK(chan->isr_vector);
 353         HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
 354         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 355         ier |= SIO_IER_ERDAI;
 356         HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 357         irq_state = 1;
 358         break;
 359     case __COMMCTL_IRQ_DISABLE:
 360         ret = irq_state;
 361         irq_state = 0;
 362         HAL_INTERRUPT_MASK(chan->isr_vector);
 363         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 364         ier &= ~SIO_IER_ERDAI;
 365         HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 366         break;
 367     case __COMMCTL_DBG_ISR_VECTOR:
 368         ret = chan->isr_vector;
 369         break;
 370     case __COMMCTL_SET_TIMEOUT:
 371         {
 372             va_list ap;
 373
 374             va_start(ap, __func);
 375
 376             ret = chan->msec_timeout;
 377             chan->msec_timeout = va_arg(ap, cyg_uint32);
 378
 379             va_end(ap);
 380         }
 381         break;
 382     default:
 383         break;
 384     }
 385     CYGARC_HAL_RESTORE_GP();
 386     return ret;
 387 }
 388
 389 static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
 390                                  CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
 391 {
 392     channel_data_t* chan = (channel_data_t*)__ch_data;
 393     uart_width _iir;
 394     int res = 0;
 395     CYGARC_HAL_SAVE_GP();
 396
 397     HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
 398     _iir &= SIO_IIR_ID_MASK;
 399
 400     *__ctrlc = 0;
 401     if ( ISR_Rx == _iir ) {
 402         uart_width c, lsr;
 403         cyg_uint8 c8;
 404         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
 405         if (lsr & SIO_LSR_DR) {
 406
 407             HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
 408
 409             c8 = (cyg_uint8) (c & 0x00FF);
 410
 411             if (cyg_hal_is_break( &c8 , 1 ))
 412                 *__ctrlc = 1;
 413         }
 414
 415         // Acknowledge the interrupt
 416         HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
 417         res = CYG_ISR_HANDLED;
 418     }
 419
 420     CYGARC_HAL_RESTORE_GP();
 421     return res;
 422 }
 423
 424 static void cyg_hal_plf_duart_init(void)
 425 {
 426     hal_virtual_comm_table_t* comm;
 427     int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 428     int i;
 429
 430     // Init channels
 431 #define NUMOF(x) (sizeof(x)/sizeof(x[0]))
 432     for (i = 0;  i < NUMOF(channels);  i++) {
 433         HAL_INTERRUPT_MASK(channels[i].isr_vector);
 434         init_duart_channel(&channels[i]);
 435         CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
 436         comm = CYGACC_CALL_IF_CONSOLE_PROCS();
 437         CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
 438         CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
 439         CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
 440         CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
 441         CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
 442         CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
 443         CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
 444         CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
 445     }
 446
 447     // Restore original console
 448     CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
 449 }
 450
 451 //=============================================================================
 452 // Compatibility with older stubs
 453 //=============================================================================
 454
 455 //=============================================================================
 456 // Compatibility with older stubs
 457 //=============================================================================
 458
 459 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 460
 461 #include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
 462
 463 #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
 464 #define __BASE   CMA101_DUARTA
 465 #define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_A
 466 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
 467 #define __BASE   CMA101_DUARTB
 468 #define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_B
 469 #endif
 470
 471 #ifdef __BASE
 472
 473 #ifdef CYGSEM_HAL_ROM_MONITOR
 474 #define CYG_HAL_STARTUP_ROM
 475 #define CYG_HAL_STARTUP_ROMRAM
 476 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 477 #endif
 478
 479 #if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 480 #define HAL_DIAG_USES_HARDWARE
 481 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
 482 #define HAL_DIAG_USES_HARDWARE
 483 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
 484 #define HAL_DIAG_USES_HARDWARE
 485 #endif
 486
 487 static channel_data_t channel = {
 488     (uart_width*) _BASE, 0, 0
 489 };
 490
 491 #ifdef HAL_DIAG_USES_HARDWARE
 492
 493 void hal_diag_init(void)
 494 {
 495     static int init = 0;
 496     char *msg = "\n\rARM eCos\n\r";
 497     uart_width lcr;
 498
 499     if (init++) return;
 500
 501     init_duart_channel(&channel);
 502
 503     while (*msg) hal_diag_write_char(*msg++);
 504 }
 505
 506 #ifdef DEBUG_DIAG
 507 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 508 #define DIAG_BUFSIZE 32
 509 #else
 510 #define DIAG_BUFSIZE 2048
 511 #endif
 512 static char diag_buffer[DIAG_BUFSIZE];
 513 static int diag_bp = 0;
 514 #endif
 515
 516 void hal_diag_write_char(char c)
 517 {
 518     uart_width lsr;
 519
 520     hal_diag_init();
 521
 522     cyg_hal_plf_duart_putc(&channel, c)
 523
 524 #ifdef DEBUG_DIAG
 525     diag_buffer[diag_bp++] = c;
 526     if (diag_bp == DIAG_BUFSIZE) {
 527         while (1) ;
 528         diag_bp = 0;
 529     }
 530 #endif
 531 }
 532
 533 void hal_diag_read_char(char *c)
 534 {
 535     *c = cyg_hal_plf_duart_getc(&channel);
 536 }
 537
 538 #else // HAL_DIAG relies on GDB
 539
 540 // Initialize diag port - assume GDB channel is already set up
 541 void hal_diag_init(void)
 542 {
 543     if (0) init_duart_channel(&channel); // avoid warning
 544 }
 545
 546 // Actually send character down the wire
 547 static void hal_diag_write_char_serial(char c)
 548 {
 549     cyg_hal_plf_duart_putc(&channel, c);
 550 }
 551
 552 static bool hal_diag_read_serial(char *c)
 553 {
 554     long timeout = 1000000000;  // A long time...
 555
 556     while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
 557         if (0 == --timeout) return false;
 558
 559     return true;
 560 }
 561
 562 void hal_diag_read_char(char *c)
 563 {
 564     while (!hal_diag_read_serial(c)) ;
 565 }
 566
 567 void hal_diag_write_char(char c)
 568 {
 569     static char line[100];
 570     static int pos = 0;
 571
 572     // No need to send CRs
 573     if (c == '\r') return;
 574
 575     line[pos++] = c;
 576
 577     if (c == '\n' || pos == sizeof(line)) {
 578         CYG_INTERRUPT_STATE old;
 579
 580         // Disable interrupts. This prevents GDB trying to interrupt us
 581         // while we are in the middle of sending a packet. The serial
 582         // receive interrupt will be seen when we re-enable interrupts
 583         // later.
 584
 585 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 586         CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
 587 #else
 588         HAL_DISABLE_INTERRUPTS(old);
 589 #endif
 590
 591         while (1) {
 592             static char hex[] = "0123456789ABCDEF";
 593             cyg_uint8 csum = 0;
 594             int i;
 595             char c1;
 596
 597             hal_diag_write_char_serial('$');
 598             hal_diag_write_char_serial('O');
 599             csum += 'O';
 600             for (i = 0; i < pos; i++) {
 601                 char ch = line[i];
 602                 char h = hex[(ch>>4)&0xF];
 603                 char l = hex[ch&0xF];
 604                 hal_diag_write_char_serial(h);
 605                 hal_diag_write_char_serial(l);
 606                 csum += h;
 607                 csum += l;
 608             }
 609             hal_diag_write_char_serial('#');
 610             hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
 611             hal_diag_write_char_serial(hex[csum&0xF]);
 612
 613             // Wait for the ACK character '+' from GDB here and handle
 614             // receiving a ^C instead.  This is the reason for this clause
 615             // being a loop.
 616             if (!hal_diag_read_serial(&c1))
 617                 continue;   // No response - try sending packet again
 618
 619             if ( c1 == '+' )
 620                 break;          // a good acknowledge
 621
 622 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 623             cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
 624             if ( c1 == 3 ) {
 625                 // Ctrl-C: breakpoint.
 626                 cyg_hal_gdb_interrupt (__builtin_return_address(0));
 627                 break;
 628             }
 629 #endif
 630             // otherwise, loop round again
 631         }
 632
 633         pos = 0;
 634
 635         // And re-enable interrupts
 636 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 637         CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
 638 #else
 639         HAL_RESTORE_INTERRUPTS(old);
 640 #endif
 641
 642     }
 643 }
 644 #endif
 645
 646 #endif // __BASE
 647
 648 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 649
 650 /*---------------------------------------------------------------------------*/