unified MX27, MX25, MX37 trees
[karo-tx-redboot.git] / packages / hal / arm / mx31 / var / v2_0 / include / hal_cache.h
1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
3
4 //=============================================================================
5 //
6 //      hal_cache.h
7 //
8 //      HAL cache control API
9 //
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 //
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
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23 // for more details.
24 //
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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28 //
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44
45 #include <cyg/infra/cyg_type.h>
46 #include <cyg/hal/hal_soc.h>         // Variant specific hardware definitions
47
48 //-----------------------------------------------------------------------------
49 // Cache dimensions
50
51 // Data cache
52 #define HAL_DCACHE_SIZE                 0x4000    // 16KB Size of data cache in bytes
53 #define HAL_DCACHE_LINE_SIZE            32    // Size of a data cache line
54 #define HAL_DCACHE_WAYS                 64    // Associativity of the cache
55
56 // Instruction cache
57 #define HAL_ICACHE_SIZE                 0x4000    // Size of cache in bytes
58 #define HAL_ICACHE_LINE_SIZE            32    // Size of a cache line
59 #define HAL_ICACHE_WAYS                 64    // Associativity of the cache
60
61 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE / (HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
62 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE / (HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
63
64 #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
65 #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x20
66 #define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
67 //-----------------------------------------------------------------------------
68 // Global control of data cache
69
70 // Enable the data cache
71 #define HAL_DCACHE_ENABLE_L1()                                          \
72 CYG_MACRO_START                                                         \
73     asm volatile (                                                      \
74         "mrc p15, 0, r1, c1, c0, 0;"                                    \
75         "orr r1, r1, #0x0007;" /* enable DCache (also ensures */        \
76                                /* the MMU, alignment faults, and */       \
77         "mcr p15, 0, r1, c1, c0, 0"                                     \
78         :                                                               \
79         :                                                               \
80         : "r1" /* Clobber list */                                       \
81         );                                                              \
82 CYG_MACRO_END
83
84 // Disable the data cache
85 #define HAL_DCACHE_DISABLE_L1()                                         \
86 CYG_MACRO_START                                                         \
87     asm volatile (                                                      \
88         "mov r1, #0;"                                                   \
89         "mcr p15, 0, r1, c7, c6, 0;" /* clear data cache */             \
90         "mrc p15, 0, r1, c1, c0, 0;"                                    \
91         "bic r1, r1, #0x0004;" /* disable DCache  */                    \
92                              /* but not MMU and alignment faults */     \
93         "mcr p15, 0, r1, c1, c0, 0"                                     \
94         :                                                               \
95         :                                                               \
96         : "r1" /* Clobber list */                                       \
97     );                                                                  \
98 CYG_MACRO_END
99
100 // Invalidate the entire cache
101 #define HAL_DCACHE_INVALIDATE_ALL_L1()                                  \
102 CYG_MACRO_START  /* this macro can discard dirty cache lines. */        \
103     asm volatile (                                                      \
104         "mov r0, #0;"                                                   \
105         "mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */                \
106         "mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */               \
107         :                                                               \
108         :                                                               \
109         : "r0","memory" /* clobber list */                              \
110     );                                                                  \
111 CYG_MACRO_END
112
113 // Synchronize the contents of the cache with memory.
114 // using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
115 #define HAL_DCACHE_SYNC_L1()                                           \
116 CYG_MACRO_START                                                        \
117     asm volatile (                                                     \
118         "nop; "                                                        \
119         "nop; "                                                        \
120         "nop; "                                                        \
121         "nop; "                                                        \
122         "nop; "                                                        \
123         "nop; "                                                        \
124         "mov r0, #0x0;"                                                \
125         "mcr p15, 0, r0, c7, c14, 0;" /* clean, invalidate Dcache*/    \
126         "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */     \
127         "mcr p15, 0, r0, c7, c10, 5;" /* data memory barrier */        \
128         :                                                              \
129         :                                                              \
130         : "r0" /* Clobber list */                                      \
131         );                                                             \
132 CYG_MACRO_END
133
134 // Query the state of the data cache
135 #define HAL_DCACHE_IS_ENABLED(_state_)                                  \
136 CYG_MACRO_START                                                         \
137     register int reg;                                                   \
138     asm volatile (                                                      \
139         "nop; "                                                         \
140         "nop; "                                                         \
141         "nop; "                                                         \
142         "nop; "                                                         \
143         "nop; "                                                         \
144         "mrc p15, 0, %0, c1, c0, 0;"                                    \
145                   : "=r"(reg)                                           \
146                   :                                                     \
147         );                                                              \
148     (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */          \
149 CYG_MACRO_END
150
151 //-----------------------------------------------------------------------------
152 // Global control of Instruction cache
153
154 // Enable the instruction cache
155 #define HAL_ICACHE_ENABLE_L1()                                          \
156 CYG_MACRO_START                                                         \
157     asm volatile (                                                      \
158         "mrc p15, 0, r1, c1, c0, 0;"                                    \
159         "orr r1, r1, #0x1000;"                                          \
160         "orr r1, r1, #0x0003;"  /* enable ICache (also ensures   */     \
161                                 /* that MMU and alignment faults */     \
162                                 /* are enabled)                  */     \
163         "mcr p15, 0, r1, c1, c0, 0"                                     \
164         :                                                               \
165         :                                                               \
166         : "r1" /* Clobber list */                                       \
167         );                                                              \
168 CYG_MACRO_END
169
170 // Query the state of the instruction cache
171 #define HAL_ICACHE_IS_ENABLED(_state_)                                  \
172 CYG_MACRO_START                                                         \
173     register cyg_uint32 reg;                                            \
174     asm volatile (                                                      \
175         "mrc p15, 0, %0, c1, c0, 0"                                     \
176         : "=r"(reg)                                                     \
177         :                                                               \
178         );                                                              \
179                                                                         \
180     (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */    \
181 CYG_MACRO_END
182
183 // Disable the instruction cache
184 #define HAL_ICACHE_DISABLE_L1()                                         \
185 CYG_MACRO_START                                                         \
186     asm volatile (                                                      \
187         "mrc p15, 0, r1, c1, c0, 0;"                                    \
188         "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */  \
189         "mcr p15, 0, r1, c1, c0, 0;"                                    \
190         "mov r1, #0;"                                                   \
191         "mcr p15, 0, r1, c7, c5, 0;"  /* flush ICache */                \
192         "mcr p15, 0, r1, c7, c5, 4;"  /* flush prefetch buffer */       \
193         "nop;" /* next few instructions may be via cache    */          \
194         "nop;"                                                          \
195         "nop;"                                                          \
196         "nop;"                                                          \
197         "nop;"                                                          \
198         "nop"                                                           \
199         :                                                               \
200         :                                                               \
201         : "r1" /* Clobber list */                                       \
202         );                                                              \
203 CYG_MACRO_END
204
205 // Invalidate the entire cache
206 #define HAL_ICACHE_INVALIDATE_ALL_L1()                                  \
207 CYG_MACRO_START                                                         \
208     /* this macro can discard dirty cache lines (N/A for ICache) */     \
209     asm volatile (                                                      \
210         "mov r1, #0;"                                                   \
211         "mcr p15, 0, r1, c7, c5, 0;"  /* flush ICache */                \
212         "mcr p15, 0, r1, c8, c5, 0;"  /* flush ITLB only */             \
213         "mcr p15, 0, r1, c7, c5, 4;"  /* flush prefetch buffer */       \
214         "nop;" /* next few instructions may be via cache    */          \
215         "nop;"                                                          \
216         "nop;"                                                          \
217         "nop;"                                                          \
218         "nop;"                                                          \
219         "nop;"                                                          \
220         :                                                               \
221         :                                                               \
222         : "r1" /* Clobber list */                                       \
223         );                                                              \
224 CYG_MACRO_END
225
226 // Synchronize the contents of the cache with memory.
227 // (which includes flushing out pending writes)
228 #define HAL_ICACHE_SYNC()                                       \
229 CYG_MACRO_START                                                 \
230     HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
231     HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
232 CYG_MACRO_END
233
234 // Query the state of the L2 cache
235 #define HAL_L2CACHE_IS_ENABLED(_state_)                         \
236     (_state_ = readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1)
237
238 #ifdef L2CC_ENABLED
239
240 #define HAL_ENABLE_L2()                             \
241 {                                                   \
242     writel(1, L2CC_BASE_ADDR + L2_CACHE_CTL_REG);   \
243 }
244
245 #define HAL_DISABLE_L2()                            \
246 {                                                   \
247     writel(0, L2CC_BASE_ADDR + L2_CACHE_CTL_REG);   \
248 }
249
250 #define HAL_SYNC_L2()                                                           \
251 {                                                                               \
252     if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) {                  \
253         writel(0, L2CC_BASE_ADDR + L2_CACHE_SYNC_REG);                          \
254         while ((readl(L2CC_BASE_ADDR + L2_CACHE_SYNC_REG) & 1) == 1);           \
255     }                                                                           \
256 }
257
258 #define HAL_INVALIDATE_L2()                                                     \
259 {                                                                               \
260     if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) {                  \
261         writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG);                    \
262         while ((readl(L2CC_BASE_ADDR + L2_CACHE_INV_WAY_REG) & 0xFF) != 0);    \
263         HAL_SYNC_L2();                                                          \
264     }                                                                           \
265 }
266                                                                                 \
267 #define HAL_CLEAN_INVALIDATE_L2()                                               \
268 {                                                                               \
269     if ((readl(L2CC_BASE_ADDR + L2_CACHE_CTL_REG) & 1) != 0) {                  \
270         writel(0xFF, L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG);              \
271         while ((readl(L2CC_BASE_ADDR + L2_CACHE_CLEAN_INV_WAY_REG) & 0xFF) != 0);\
272         HAL_SYNC_L2();                                                          \
273     }                                                                           \
274 }
275
276 #else //L2CC_ENABLED
277
278 #define HAL_ENABLE_L2()
279 #define HAL_DISABLE_L2()
280 #define HAL_INVALIDATE_L2()
281 #define HAL_CLEAN_INVALIDATE_L2()
282 #define HAL_SYNC_L2()
283 #endif //L2CC_ENABLED
284
285 /*********************** Exported macros *******************/
286
287 #define HAL_DCACHE_ENABLE() {           \
288         HAL_DCACHE_ENABLE_L1();         \
289         HAL_ENABLE_L2();                \
290 }
291
292 #define HAL_DCACHE_DISABLE() {          \
293         HAL_DCACHE_DISABLE_L1();        \
294         HAL_DISABLE_L2();               \
295 }
296
297 #define HAL_DCACHE_INVALIDATE_ALL() {   \
298         HAL_DCACHE_INVALIDATE_ALL_L1(); \
299         HAL_CLEAN_INVALIDATE_L2();      \
300 }
301
302 #define HAL_DCACHE_SYNC() {             \
303         HAL_DCACHE_SYNC_L1();           \
304         /* don't just call HAL_SYNC_L2() */ \
305         HAL_CLEAN_INVALIDATE_L2();      \
306 }
307
308 #define HAL_ICACHE_INVALIDATE_ALL() {   \
309         HAL_ICACHE_INVALIDATE_ALL_L1(); \
310         HAL_CLEAN_INVALIDATE_L2();      \
311 }
312
313 #define HAL_ICACHE_DISABLE() {          \
314         HAL_ICACHE_DISABLE_L1();        \
315 }                                       
316
317 #define HAL_ICACHE_ENABLE() {           \
318         HAL_ICACHE_ENABLE_L1();         \
319 }
320
321 #endif // ifndef CYGONCE_HAL_CACHE_H
322 // End of hal_cache.h