1 //==========================================================================
5 // HAL misc board support code for the board
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
42 #include <pkgconf/hal.h>
43 #include <pkgconf/system.h>
45 #include CYGBLD_HAL_PLATFORM_H
47 #include <cyg/infra/cyg_type.h> // base types
48 #include <cyg/infra/cyg_trac.h> // tracing macros
49 #include <cyg/infra/cyg_ass.h> // assertion macros
51 #include <cyg/hal/hal_io.h> // IO macros
52 #include <cyg/hal/hal_arch.h> // Register state info
53 #include <cyg/hal/hal_diag.h>
54 #include <cyg/hal/hal_intr.h> // Interrupt names
55 #include <cyg/hal/hal_cache.h>
56 #include <cyg/hal/hal_soc.h> // Hardware definitions
57 #include <cyg/hal/fsl_board.h> // Platform specifics
59 #include <cyg/infra/diag.h> // diag_printf
61 // All the MM table layout is here:
62 #include <cyg/hal/hal_mm.h>
64 externC void* memset(void *, int, size_t);
65 static void plf_setup_uart(void);
66 static void plf_setup_fec(void);
68 void hal_mmu_init(void)
70 unsigned long ttb_base = RAM_BANK1_BASE + 0x4000;
74 * Set the TTB register
76 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
79 * Set the Domain Access Control Register
81 i = ARM_ACCESS_DACR_DEFAULT;
82 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
85 * First clear all TT entries - ie Set them to Faulting
87 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
89 /* Actual Virtual Size Attributes Function */
90 /* Base Base MB cached? buffered? access permissions */
91 /* xxx00000 xxx00000 */
92 X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
93 X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
94 X_ARM_MMU_SECTION(0x400, 0x400, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
95 X_ARM_MMU_SECTION(0x900, 0x000, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
96 X_ARM_MMU_SECTION(0x900, 0x900, 0x80, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
97 X_ARM_MMU_SECTION(0x900, 0x980, 0x80, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
98 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x200, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
99 X_ARM_MMU_SECTION(0xB00, 0xB00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PSRAM */
100 X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0, ARM_UNCACHEABLE, ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW); /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
104 // Platform specific initialization
107 unsigned int g_clock_src;
109 void plf_hardware_init(void)
112 unsigned long val = readl(CCM_BASE_ADDR + CLKCTL_CCMR);
114 g_clock_src = FREQ_24MHZ;
116 /* Reset interrupt status reg */
118 writel(0x0000007, PBC_CTRL1_SET);
119 for(i=0; i<10000; i++);
120 writel(0x0000007, PBC_CTRL1_CLR);
127 writel(0, IOMUXC_BASE_ADDR + 0x188);
128 writel(0x1E0, IOMUXC_BASE_ADDR + 0x55C);
131 writel(0, IOMUXC_BASE_ADDR + 0x18C);
132 writel(0x40, IOMUXC_BASE_ADDR + 0x560);
135 writel(0, IOMUXC_BASE_ADDR + 0x190);
136 writel(0x1E0, IOMUXC_BASE_ADDR + 0x564);
139 writel(0, IOMUXC_BASE_ADDR + 0x194);
140 writel(0x40, IOMUXC_BASE_ADDR + 0x568);
143 //writel(0x13131300, IOMUXC_BASE_ADDR + 0x70);
144 //writel(0x00001313, IOMUXC_BASE_ADDR + 0x74);
145 //writel(0x00000040, IOMUXC_BASE_ADDR + 0x7C);
146 //writel(0x40400000, IOMUXC_BASE_ADDR + 0x78);
150 static void plf_setup_uart(void)
154 writel(0, IOMUXC_BASE_ADDR + 0x188);
155 writel(0x1E0, IOMUXC_BASE_ADDR + 0x55C);
158 writel(0, IOMUXC_BASE_ADDR + 0x18C);
159 writel(0x40, IOMUXC_BASE_ADDR + 0x560);
162 writel(0, IOMUXC_BASE_ADDR + 0x190);
163 writel(0x1E0, IOMUXC_BASE_ADDR + 0x564);
166 writel(0, IOMUXC_BASE_ADDR + 0x194);
167 writel(0x40, IOMUXC_BASE_ADDR + 0x568);
172 static void plf_setup_fec(void)
175 writel(0, IOMUXC_BASE_ADDR + 0x02E0);
176 writel(0x1C0, IOMUXC_BASE_ADDR + 0x0744);
179 writel(0, IOMUXC_BASE_ADDR + 0x02E4);
180 writel(0x1C0, IOMUXC_BASE_ADDR + 0x0748);
183 writel(0, IOMUXC_BASE_ADDR + 0x02E8);
184 writel(0x1C0, IOMUXC_BASE_ADDR + 0x074C);
187 writel(0, IOMUXC_BASE_ADDR + 0x02EC);
188 writel(0x1C0, IOMUXC_BASE_ADDR + 0x0750);
191 writel(0, IOMUXC_BASE_ADDR + 0x02F0);
192 writel(0x1C0, IOMUXC_BASE_ADDR + 0x0754);
195 writel(0, IOMUXC_BASE_ADDR + 0x02F4);
196 writel(0x40, IOMUXC_BASE_ADDR + 0x0758);
199 writel(0, IOMUXC_BASE_ADDR + 0x02F8);
200 writel(0x40, IOMUXC_BASE_ADDR + 0x075C);
203 writel(0, IOMUXC_BASE_ADDR + 0x02FC);
204 writel(0x40, IOMUXC_BASE_ADDR + 0x0760);
207 writel(0, IOMUXC_BASE_ADDR + 0x0300);
208 writel(0x1F0, IOMUXC_BASE_ADDR + 0x0764);
211 writel(0, IOMUXC_BASE_ADDR + 0x0304);
212 writel(0x40, IOMUXC_BASE_ADDR + 0x0768);
215 writel(0, IOMUXC_BASE_ADDR + 0x0308);
216 writel(0x1C0, IOMUXC_BASE_ADDR + 0x076C);
219 writel(0, IOMUXC_BASE_ADDR + 0x030C);
220 writel(0x1C0, IOMUXC_BASE_ADDR + 0x0770);
223 writel(0, IOMUXC_BASE_ADDR + 0x0310);
224 writel(0x1C0, IOMUXC_BASE_ADDR + 0x0774);
227 writel(0, IOMUXC_BASE_ADDR + 0x0314);
228 writel(0x40, IOMUXC_BASE_ADDR + 0x0778);
231 writel(0, IOMUXC_BASE_ADDR + 0x0318);
232 writel(0x1C0, IOMUXC_BASE_ADDR + 0x077C);
235 writel(0, IOMUXC_BASE_ADDR + 0x031C);
236 writel(0x40, IOMUXC_BASE_ADDR + 0x0780);
239 writel(0, IOMUXC_BASE_ADDR + 0x0320);
240 writel(0x1C0, IOMUXC_BASE_ADDR + 0x0784);
243 writel(0, IOMUXC_BASE_ADDR + 0x0324);
244 writel(0x40, IOMUXC_BASE_ADDR + 0x0788);
247 #include CYGHWR_MEMORY_LAYOUT_H
249 typedef void code_fun(void);
251 void board_program_new_stack(void *func)
253 register CYG_ADDRESS stack_ptr asm("sp");
254 register CYG_ADDRESS old_stack asm("r4");
255 register code_fun *new_func asm("r0");
256 old_stack = stack_ptr;
257 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
258 new_func = (code_fun*)func;
260 stack_ptr = old_stack;
263 static void display_clock_src(void)
266 diag_printf("Clock input is 24 MHz");
268 RedBoot_init(display_clock_src, RedBoot_INIT_LAST);
270 // ------------------------------------------------------------------------