71793c70009a0089f3c89e7abfd5179ee0510bfc
[karo-tx-redboot.git] / packages / hal / arm / mx37 / var / v2_0 / include / hal_mm.h
1 #ifndef CYGONCE_HAL_MM_H
2 #define CYGONCE_HAL_MM_H
3
4 //=============================================================================
5 //
6 //      hal_mm.h
7 //
8 //=============================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
10 // -------------------------------------------
11 // This file is part of eCos, the Embedded Configurable Operating System.
12 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 //
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
17 //
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21 // for more details.
22 //
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 //
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
33 //
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
36 //
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //=============================================================================
42 // -------------------------------------------------------------------------
43 // MMU initialization:
44 //
45 // These structures are laid down in memory to define the translation
46 // table.
47 //
48
49 /*
50  * Translation Table Base Bit Masks
51  */
52 #define ARM_TRANSLATION_TABLE_MASK                               0xFFFFC000
53
54 /*
55  * Domain Access Control Bit Masks
56  */
57 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
58 #define ARM_ACCESS_TYPE_CLIENT(domain_num)               (0x1 << (domain_num)*2)
59 #define ARM_ACCESS_TYPE_MANAGER(domain_num)              (0x3 << (domain_num)*2)
60
61 struct ARM_MMU_FIRST_LEVEL_FAULT {
62                 unsigned int id : 2;
63                 unsigned int sbz : 30;
64 };
65
66 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
67
68 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
69                 unsigned int id : 2;
70                 unsigned int imp : 2;
71                 unsigned int domain : 4;
72                 unsigned int sbz : 1;
73                 unsigned int base_address : 23;
74 };
75
76 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
77
78 struct ARM_MMU_FIRST_LEVEL_SECTION {
79                 unsigned int id : 2;
80                 unsigned int b : 1;
81                 unsigned int c : 1;
82                 unsigned int imp : 1;
83                 unsigned int domain : 4;
84                 unsigned int sbz0 : 1;
85                 unsigned int ap : 2;
86                 unsigned int sbz1 : 8;
87                 unsigned int base_address : 12;
88 };
89
90 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
91
92 struct ARM_MMU_FIRST_LEVEL_RESERVED {
93                 unsigned int id : 2;
94                 unsigned int sbz : 30;
95 };
96
97 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
98
99 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
100                 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
101
102 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
103
104 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,                      \
105                                                 cacheable, bufferable, perm)                                      \
106         CYG_MACRO_START                                                                                                           \
107                 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;                               \
108                                                                                                                                                   \
109                 desc.word = 0;                                                                                                    \
110                 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                                 \
111                 desc.section.domain = 0;                                                                                  \
112                 desc.section.c = (cacheable);                                                                     \
113                 desc.section.b = (bufferable);                                                                    \
114                 desc.section.ap = (perm);                                                                                 \
115                 desc.section.base_address = (actual_base);                                                \
116                 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
117                                                         = desc.word;                                                              \
118         CYG_MACRO_END
119
120 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access)                             \
121           {                                                                                                                        \
122                 int i; int j = abase; int k = vbase;                                                      \
123                 for (i = size; i > 0 ; i--,j++,k++) {                                                     \
124                 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access);      \
125           }                                                                                                                        \
126         }
127
128 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
129                 unsigned long word;
130                 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
131                 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
132                 struct ARM_MMU_FIRST_LEVEL_SECTION section;
133                 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
134 };
135
136 #define ARM_UNCACHEABLE                                                 0
137 #define ARM_CACHEABLE                                                   1
138 #define ARM_UNBUFFERABLE                                                0
139 #define ARM_BUFFERABLE                                                  1
140
141 #define ARM_ACCESS_PERM_NONE_NONE                               0
142 #define ARM_ACCESS_PERM_RO_NONE                                 0
143 #define ARM_ACCESS_PERM_RO_RO                                   0
144 #define ARM_ACCESS_PERM_RW_NONE                                 1
145 #define ARM_ACCESS_PERM_RW_RO                                   2
146 #define ARM_ACCESS_PERM_RW_RW                                   3
147
148 /*
149  * Initialization for the Domain Access Control Register
150  */
151 #define ARM_ACCESS_DACR_DEFAULT          (                      \
152                 ARM_ACCESS_TYPE_MANAGER(0)        |                     \
153                 ARM_ACCESS_TYPE_NO_ACCESS(1)  |                 \
154                 ARM_ACCESS_TYPE_NO_ACCESS(2)  |                 \
155                 ARM_ACCESS_TYPE_NO_ACCESS(3)  |                 \
156                 ARM_ACCESS_TYPE_NO_ACCESS(4)  |                 \
157                 ARM_ACCESS_TYPE_NO_ACCESS(5)  |                 \
158                 ARM_ACCESS_TYPE_NO_ACCESS(6)  |                 \
159                 ARM_ACCESS_TYPE_NO_ACCESS(7)  |                 \
160                 ARM_ACCESS_TYPE_NO_ACCESS(8)  |                 \
161                 ARM_ACCESS_TYPE_NO_ACCESS(9)  |                 \
162                 ARM_ACCESS_TYPE_NO_ACCESS(10) |                 \
163                 ARM_ACCESS_TYPE_NO_ACCESS(11) |                 \
164                 ARM_ACCESS_TYPE_NO_ACCESS(12) |                 \
165                 ARM_ACCESS_TYPE_NO_ACCESS(13) |                 \
166                 ARM_ACCESS_TYPE_NO_ACCESS(14) |                 \
167                 ARM_ACCESS_TYPE_NO_ACCESS(15) )
168
169 #if 0
170 /*
171  * translate the virtual address of ram space to physical address
172  * It is dependent on the implementation of hal_mmu_init
173  */
174 static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
175 {
176         if (virt < 0x08000000) {
177                 return virt | 0x40000000;
178         }
179         if ((virt & 0xF0000000) == 0x40000000) {
180                 return virt & ~0x08000000;
181         }
182         return virt;
183 }
184
185 /*
186  * remap the physical address of ram space to uncacheable virtual address space
187  * It is dependent on the implementation of hal_mmu_init
188  */
189 static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
190 {
191         /* 0x48000000~0x48FFFFFF is uncacheable meory space which is mapped to SDRAM*/
192         if ((phy & 0xF0000000) == 0x40000000) {
193                 phy |= 0x08000000;
194         }
195         return phy;
196 }
197 #endif
198
199 // ------------------------------------------------------------------------
200 #endif // ifndef CYGONCE_HAL_MM_H
201 // End of hal_mm.h
202
203
204
205
206