1 //==========================================================================
5 // MX51 Fast Logo Implementation
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
42 #include <cyg/io/ipu_common.h>
44 // DI counter definitions
45 #define DI_COUNTER_BASECLK 0
46 #define DI_COUNTER_IHSYNC 1
47 #define DI_COUNTER_OHSYNC 2
48 #define DI_COUNTER_OVSYNC 3
49 #define DI_COUNTER_ALINE 4
50 #define DI_COUNTER_ACLOCK 5
52 extern display_buffer_info_t display_buffer;
54 void fastlogo_dma(void)
56 ipu_channel_parameter_t ipu_channel_params;
57 ipu_idmac_channel_enable(DISPLAY_CHANNEL, 0);
59 ipu_idmac_params_init(&ipu_channel_params);
60 ipu_channel_params.channel = DISPLAY_CHANNEL;
61 ipu_channel_params.eba0 = (unsigned int)(display_buffer.startAddr) / 8;
62 ipu_channel_params.fw = display_buffer.width - 1; //frame width
63 ipu_channel_params.fh = display_buffer.height - 1; //frame height
64 ipu_channel_params.sl = (display_buffer.width * display_buffer.bpp) / 8 - 1;
65 ipu_channel_params.npb = 31; //16 pixels per burst
66 ipu_channel_params.pfs = 7; //1->4:2:2 non-interleaved, 7->rgb
68 switch(display_buffer.bpp) {
70 ipu_channel_params.bpp = 0;
73 ipu_channel_params.bpp = 1;
76 ipu_channel_params.bpp = 2;
79 ipu_channel_params.bpp = 3;
82 diag_printf("data bpp format not supported!\n");
85 switch(display_buffer.dataFormat) {
87 ipu_channel_params.wid0 = 5 - 1; //bits
88 ipu_channel_params.wid1 = 6 - 1; //bits;
89 ipu_channel_params.wid2 = 5 - 1; //bits;
90 ipu_channel_params.wid3 = 0; //bits;
91 ipu_channel_params.ofs0 = 0;
92 ipu_channel_params.ofs1 = 5;
93 ipu_channel_params.ofs2 = 11;
94 ipu_channel_params.ofs3 = 16;
98 ipu_channel_params.wid0 = 6 - 1; //bits
99 ipu_channel_params.wid1 = 6 - 1; //bits;
100 ipu_channel_params.wid2 = 6 - 1; //bits;
101 ipu_channel_params.wid3 = 0; //bits;
102 ipu_channel_params.ofs0 = 0;
103 ipu_channel_params.ofs1 = 6;
104 ipu_channel_params.ofs2 = 12;
105 ipu_channel_params.ofs3 = 18;
108 ipu_channel_params.wid0 = 8 - 1; //bits
109 ipu_channel_params.wid1 = 8 - 1; //bits;
110 ipu_channel_params.wid2 = 8 - 1; //bits;
111 ipu_channel_params.wid3 = 0; //bits;
112 ipu_channel_params.ofs0 = 0;
113 ipu_channel_params.ofs1 = 8;
114 ipu_channel_params.ofs2 = 16;
115 ipu_channel_params.ofs3 = 24;
118 ipu_channel_params.wid0 = 8 - 1; //bits
119 ipu_channel_params.wid1 = 8 - 1; //bits;
120 ipu_channel_params.wid2 = 8 - 1; //bits;
121 ipu_channel_params.wid3 = 8 - 1; //bits;
122 ipu_channel_params.ofs0 = 0;
123 ipu_channel_params.ofs1 = 8;
124 ipu_channel_params.ofs2 = 16;
125 ipu_channel_params.ofs3 = 24;
128 diag_printf("data format not supported!\n");
130 ipu_channel_params.bm = 0;
131 ipu_channel_params.hf = 0;
132 ipu_channel_params.vf = 1;
133 ipu_channel_params.id = 0;
134 ipu_idmac_interleaved_channel_config(ipu_channel_params);
136 ipu_idmac_channel_mode_sel(DISPLAY_CHANNEL, 0);
137 ipu_idmac_channel_enable(DISPLAY_CHANNEL, 1);
140 void fastlogo_dmfc(void)
142 ipu_dmfc_fifo_allocate(DISPLAY_CHANNEL, 1, 0, 4);
145 void fastlogo_dc(void)
147 //***************************************************/
149 //****************************************************/
151 dc_microcode_t microcode;
154 microcode.opcode = "WROD";
157 microcode.operand = 0;
158 microcode.mapping = 2;
159 microcode.waveform = 1;
160 microcode.gluelogic = 0;
162 ipu_dc_microcode_config(microcode);
164 ipu_dc_microcode_event(1, "NEW_DATA", 1, 4);
167 ipu_dc_write_channel_config(DISPLAY_CHANNEL, 2, 0, 0);
170 ipu_dc_display_config(2, 2 /*paralell */ , 0, display_buffer.width);
173 ipu_dc_map(1, RGB666);
176 void fastlogo_di(void)
178 di_sync_wave_gen_t syncWaveformGen = { 0 };
180 int hSyncStartWidth = 80;
182 int hSyncEndWidth = 41;
185 int vSyncStartWidth = 20;
187 int vSyncEndWidth = 5;;
189 int ipuClk = 133000000; // ipu clk is 133M
190 int typPixClk = 24000000; // typical value of pixel clock
191 int div = (int)((float)ipuClk / (float)typPixClk + 0.5); // get the nearest value of typical pixel clock
192 int pixClk = 133000000 / div;
194 //DI0_SCR, set the screen height
195 ipu_di_screen_set(0, vDisp + vSyncStartWidth + vSyncEndWidth - 1);
197 /* set DI_PIN15 to be waveform according to DI data wave set 3 */
198 ipu_di_pointer_config(0, 0, div - 1, div - 1, 0, 0, 0, 0, 0, 2, 0, 0);
200 /*set the up & down of data wave set 3. */
201 ipu_di_waveform_config(0, 0, 2, 0, div * 2); // one bit for fraction part
203 /* set clk for DI0, generate the base clock of DI0. */
206 ipu_di_bsclk_gen(0, div << 4, clkUp, clkDown);
218 syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncEndWidth - 1;
219 syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
220 syncWaveformGen.offsetValue = 0;
221 syncWaveformGen.offsetResolution = 0;
222 syncWaveformGen.cntAutoReload = 1;
223 syncWaveformGen.stepRepeat = 0;
224 syncWaveformGen.cntClrSel = 0;
225 syncWaveformGen.cntPolarityGenEn = 0;
226 syncWaveformGen.cntPolarityTrigSel = 0;
227 syncWaveformGen.cntPolarityClrSel = 0;
228 syncWaveformGen.cntUp = 0;
229 syncWaveformGen.cntDown = 1;
230 ipu_di_sync_config(0, DI_COUNTER_IHSYNC, syncWaveformGen);
233 syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncEndWidth - 1;
234 syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
235 syncWaveformGen.offsetValue = delayH2V;
236 syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1;
237 syncWaveformGen.cntAutoReload = 1;
238 syncWaveformGen.stepRepeat = 0;
239 syncWaveformGen.cntClrSel = 0;
240 syncWaveformGen.cntPolarityGenEn = 0;
241 syncWaveformGen.cntPolarityTrigSel = 0;
242 syncWaveformGen.cntPolarityClrSel = 0;
243 syncWaveformGen.cntUp = 0;
244 syncWaveformGen.cntDown = div * hSyncWidth;
245 ipu_di_sync_config(0, DI_COUNTER_OHSYNC, syncWaveformGen);
248 syncWaveformGen.runValue = vDisp + vSyncStartWidth + vSyncEndWidth - 1;
249 syncWaveformGen.runResolution = DI_COUNTER_IHSYNC + 1;
250 syncWaveformGen.offsetValue = 0;
251 syncWaveformGen.offsetResolution = 0;
252 syncWaveformGen.cntAutoReload = 1;
253 syncWaveformGen.stepRepeat = 0;
254 syncWaveformGen.cntClrSel = 0;
255 syncWaveformGen.cntPolarityGenEn = 1;
256 syncWaveformGen.cntPolarityTrigSel = 2;
257 syncWaveformGen.cntPolarityClrSel = 0;
258 syncWaveformGen.cntUp = 0;
259 syncWaveformGen.cntDown = vSyncWidth;
260 ipu_di_sync_config(0, DI_COUNTER_OVSYNC, syncWaveformGen);
262 /*Active Lines start points */
263 syncWaveformGen.runValue = 0;
264 syncWaveformGen.runResolution = DI_COUNTER_OHSYNC + 1;
265 syncWaveformGen.offsetValue = vSyncWidth;
266 syncWaveformGen.offsetResolution = DI_COUNTER_OHSYNC + 1;
267 syncWaveformGen.cntAutoReload = 0;
268 syncWaveformGen.stepRepeat = vDisp;
269 syncWaveformGen.cntClrSel = DI_COUNTER_OVSYNC + 1;
270 syncWaveformGen.cntPolarityGenEn = 0;
271 syncWaveformGen.cntPolarityTrigSel = 0;
272 syncWaveformGen.cntPolarityClrSel = 0;
273 syncWaveformGen.cntUp = 0;
274 syncWaveformGen.cntDown = 0;
275 ipu_di_sync_config(0, DI_COUNTER_ALINE, syncWaveformGen);
277 /*Active clock start points */
278 syncWaveformGen.runValue = 0;
279 syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
280 syncWaveformGen.offsetValue = hSyncWidth;
281 syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1;
282 syncWaveformGen.cntAutoReload = 0;
283 syncWaveformGen.stepRepeat = hDisp;
284 syncWaveformGen.cntClrSel = DI_COUNTER_ALINE + 1;
285 syncWaveformGen.cntPolarityGenEn = 0;
286 syncWaveformGen.cntPolarityTrigSel = 0;
287 syncWaveformGen.cntPolarityClrSel = 0;
288 syncWaveformGen.cntUp = 0;
289 syncWaveformGen.cntDown = 0;
290 ipu_di_sync_config(0, DI_COUNTER_ACLOCK, syncWaveformGen);
292 ipu_di_general_set(0, 1, 2, 1, 0);