1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
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30 // or inline functions from this file, or you compile this file and link it
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #define REMOVE_THIS_CRAP
51 #include <pkgconf/system.h> // System-wide configuration info
52 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
53 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
54 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
55 #include <cyg/hal/hal_mmu.h> // MMU definitions
56 #include <cyg/hal/karo_tx51.h> // Platform specific hardware definitions
57 #include CYGHWR_MEMORY_LAYOUT_H
59 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
60 #define PLATFORM_SETUP1 _platform_setup1
61 #define CYGHWR_HAL_ARM_HAS_MMU
63 #ifdef CYG_HAL_STARTUP_ROMRAM
64 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
67 #define TX51_NAND_PAGE_SIZE 2048
68 #define TX51_NAND_BLKS_PER_PAGE 64
71 #define DEBUG_LED_BIT 10
72 #define LED_GPIO_BASE GPIO4_BASE_ADDR
73 #define LED_MUX_OFFSET 0x1d0
74 #define LED_MUX_MODE 0x13
76 #define DEBUG_LED_BIT 0
77 #define LED_GPIO_BASE GPIO1_BASE_ADDR
78 #define LED_MUX_OFFSET 0x3ac
79 #define LED_MUX_MODE 0x11
82 #define LED_ON LED_CTRL #1
83 #define LED_OFF LED_CTRL #0
85 #ifndef CYGOPT_HAL_ARM_TX51_DEBUG
93 #define CYGHWR_LED_MACRO LED_BLINK #\x
109 // switch user LED (GPIO4_10) on STK5
110 ldr r10, =LED_GPIO_BASE
114 movne r9, #(1 << DEBUG_LED_BIT) @ LED ON
115 moveq r9, #0 @ LED OFF
116 str r9, [r10, #GPIO_DR]
135 // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
136 ldr r10, =LED_GPIO_BASE
138 ldr r9, [r10, #GPIO_GDIR]
139 orr r9, r9, #(1 << DEBUG_LED_BIT)
140 str r9, [r10, #GPIO_GDIR]
142 ldr r10, =IOMUXC_BASE_ADDR
143 mov r9, #LED_MUX_MODE
144 str r9, [r10, #LED_MUX_OFFSET]
146 mov r9, #(1 << DEBUG_LED_BIT) @ LED ON
147 str r9, [r10, #GPIO_DR]
150 #define DCDGEN(type, addr, data) .long type, addr, data
152 #define PLATFORM_PREAMBLE flash_header
154 // This macro represents the initial startup code for the platform
155 .macro _platform_setup1
157 KARO_TX51_SETUP_START:
164 ldr r1, =ROM_BASE_ADDR
165 ldr r11, [r1, #ROM_SI_REV_OFFSET]
169 ldr r0, =GPC_BASE_ADDR
170 cmp r11, #0x10 // r11 contains the silicon rev
171 ldrls r1, =0x1FC00000
172 ldrhi r1, =0x1A800000
175 // Explicitly disable L2 cache
176 mrc 15, 0, r0, c1, c0, 1
178 mcr 15, 0, r0, c1, c0, 1
180 // reconfigure L2 cache aux control reg
181 mov r0, #0xC0 // tag RAM
182 add r0, r0, #0x4 // data RAM
183 orr r0, r0, #(1 << 24) // disable write allocate delay
184 orr r0, r0, #(1 << 23) // disable write allocate combine
185 orr r0, r0, #(1 << 22) // disable write allocate
187 @ cc is still set from "cmp r11, #0x10" above
188 orrls r0, r0, #(1 << 25) @ disable write combine for TO 2 and lower revs
190 mcr 15, 1, r0, c9, c0, 2
198 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
200 #endif /* CYG_HAL_STARTUP_ROMRAM */
204 Normal_Boot_Continue:
207 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
210 @ Set up a stack [for calling C code]
211 ldr r1, =__startup_stack
212 ldr r2, =RAM_BANK0_BASE
219 /* Workaround for arm erratum #709718 */
220 @ Setup PRRR so device is always mapped to non-shared
221 mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
223 mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
227 mrc MMU_CP, 0, r1, MMU_Control, c0
228 orr r1, r1, #7 @ enable MMU bit
229 orr r1, r1, #0x800 @ enable z bit
230 orr r1, r1, #(1 << 28) @ Enable TEX remap, workaround for L1 cache issue
231 mcr MMU_CP, 0, r1, MMU_Control, c0
233 /* Workaround for arm errata #621766 */
234 mrc MMU_CP, 0, r1, MMU_Control, c0, 1
235 orr r1, r1, #(1 << 5) @ enable L1NEON bit
236 mcr MMU_CP, 0, r1, MMU_Control, c0, 1
238 mov pc, r2 @ Change address spaces
243 .endm @ _platform_setup1
245 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
248 * Set all MPROTx to be non-bufferable, trusted for R/W,
249 * not forced to user-mode.
251 ldr r0, =AIPS1_CTRL_BASE_ADDR
255 ldr r0, =AIPS2_CTRL_BASE_ADDR
258 .endm /* init_aips */
261 ldr r0, =WDOG_BASE_ADDR
269 ldr r0, =CCM_BASE_ADDR
270 ldr r1, [r0, #CLKCTL_CCR]
274 orr r1, r1, #(1 << 12)
275 str r1, [r0, #CLKCTL_CCR]
277 ldr r1, [r0, #CLKCTL_CCSR]
278 bic r1, #(1 << 9) /* switch lp_apm to OSC */
279 str r1, [r0, #CLKCTL_CCSR]
281 /* Gate off clocks to the peripherals first */
283 str r1, [r0, #CLKCTL_CCGR0]
285 str r1, [r0, #CLKCTL_CCGR1]
286 str r1, [r0, #CLKCTL_CCGR2]
287 str r1, [r0, #CLKCTL_CCGR3]
290 str r1, [r0, #CLKCTL_CCGR4]
292 str r1, [r0, #CLKCTL_CCGR5]
294 str r1, [r0, #CLKCTL_CCGR6]
296 /* Disable IPU and HSC dividers */
298 str r1, [r0, #CLKCTL_CCDR]
300 /* Make sure to switch the DDR away from PLL 1 */
301 ldr r1, CCM_CBCDR_VAL1
302 str r1, [r0, #CLKCTL_CBCDR]
303 /* make sure divider effective */
305 ldr r1, [r0, #CLKCTL_CDHIPR]
309 /* Switch ARM to step clock */
310 ldr r1, [r0, #CLKCTL_CCSR]
312 str r1, [r0, #CLKCTL_CCSR]
317 /* Switch peripheral to PLL 3 */
318 ldr r1, CCM_CBCMR_VAL1
319 str r1, [r0, #CLKCTL_CBCMR]
321 ldr r1, CCM_CBCDR_VAL2
322 str r1, [r0, #CLKCTL_CBCDR]
326 /* Switch peripheral to PLL 2 */
327 ldr r1, CCM_CBCDR_VAL1
328 str r1, [r0, #CLKCTL_CBCDR]
329 ldr r1, CCM_CBCMR_VAL2
330 str r1, [r0, #CLKCTL_CBCMR]
334 /* Set the platform clock dividers */
335 ldr r2, =PLATFORM_BASE_ADDR
336 ldr r1, PLATFORM_CLOCK_DIV
337 str r1, [r2, #PLATFORM_ICGC]
339 /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
343 str r1, [r0, #CLKCTL_CACRR]
345 /* Switch ARM back to PLL 1. */
347 str r1, [r0, #CLKCTL_CCSR]
350 /* Use lp_apm (24MHz) source for perclk */
351 ldr r1, CCM_CBCMR_VAL2
352 str r1, [r0, #CLKCTL_CBCMR]
353 @ ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
354 ldr r1, CCM_CBCDR_VAL3
356 str r1, [r0, #CLKCTL_CBCDR]
358 /* Restore the default values in the Gate registers */
360 str r1, [r0, #CLKCTL_CCGR0]
361 str r1, [r0, #CLKCTL_CCGR1]
362 str r1, [r0, #CLKCTL_CCGR2]
363 str r1, [r0, #CLKCTL_CCGR3]
364 str r1, [r0, #CLKCTL_CCGR4]
365 str r1, [r0, #CLKCTL_CCGR5]
366 str r1, [r0, #CLKCTL_CCGR6]
368 /* Use PLL 2 for UART's, get 66.5MHz from it */
369 ldr r1, CCM_VAL_0xA5A2A020
370 str r1, [r0, #CLKCTL_CSCMR1]
371 ldr r1, CCM_VAL_0x00C30321
372 str r1, [r0, #CLKCTL_CSCDR1]
374 /* make sure divider effective */
376 ldr r1, [r0, #CLKCTL_CDHIPR]
381 str r1, [r0, #CLKCTL_CCDR]
383 @ for cko - for ARM div by 8
385 orr r1, r1, #0x00000F0
386 str r1, [r0, #CLKCTL_CCOSR]
388 ldr r1, [r0, #CLKCTL_CCR]
389 bic r1, #(1 << 8) /* switch off FPM */
390 str r1, [r0, #CLKCTL_CCR]
394 .macro setup_pll pll_nr, mhz
395 ldr r2, BASE_ADDR_\pll_nr
396 ldr r1, PLL_VAL_0x1232
397 str r1, [r2, #PLL_DP_CTL] @ Set DPLL ON (set UPEN bit); BRMO=1
399 str r1, [r2, #PLL_DP_CONFIG] @ Enable auto-restart AREN bit
402 str r1, [r2, #PLL_DP_OP]
403 str r1, [r2, #PLL_DP_HFS_OP]
405 ldr r1, W_DP_MFD_\mhz
406 str r1, [r2, #PLL_DP_MFD]
407 str r1, [r2, #PLL_DP_HFS_MFD]
409 ldr r1, W_DP_MFN_\mhz
410 str r1, [r2, #PLL_DP_MFN]
411 str r1, [r2, #PLL_DP_HFS_MFN]
414 str r1, [r2, #PLL_DP_CONFIG] @ Assert LDREQ
417 ldr r1, PLL_VAL_0x1232
418 str r1, [r2, #PLL_DP_CTL]
420 ldr r1, [r2, #PLL_DP_CTL]
427 ldr r1, =M4IF_BASE_ADDR
428 ldr r0, M4IF_M4IF4_VAL
429 str r0, [r1, #M4IF_MIF4]
431 /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
432 ldr r0, M4IF_FBPM0_VAL
433 str r0, [r1, #M4IF_FBPM0]
434 .endm /* init_m4if */
437 cmp r11, #0x10 // r11 contains the silicon rev
440 /* Decrease the DRAM SDCLK to HIGH Drive strength */
441 ldr r0, =IOMUXC_BASE_ADDR
444 /* Change the delay line configuration */
445 ldr r0, =ESDCTL_BASE_ADDR
447 str r1, [r0, #ESDCTL_ESDCDLY1]
449 str r1, [r0, #ESDCTL_ESDCDLY2]
451 str r1, [r0, #ESDCTL_ESDCDLY3]
453 str r1, [r0, #ESDCTL_ESDCDLY4]
455 str r1, [r0, #ESDCTL_ESDCDLY5]
459 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
460 #define PLATFORM_SETUP1
463 #define PLATFORM_VECTORS _platform_vectors
464 .macro _platform_vectors
468 .globl _KARO_STRUCT_SIZE
470 .word 0 // reserve space structure length
472 .globl _KARO_CECFG_START
475 .word 0 // reserve space for CE configuration
478 .globl _KARO_CECFG_END
483 .ascii "KARO TX51 " __DATE__ " " __TIME__
486 /* SDRAM timing setup */
490 #define RA_BITS 2 /* row addr bits - 11 */
491 #define CA_BITS 2 /* 0-2: col addr bits - 8 3: rsrvd */
492 #define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
493 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
494 #define SRT 0 /* 0: disabled *: 1: self refr. ... */
495 #define PWDT 0 /* 0: disabled 1: precharge pwdn
496 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
497 #define ESDCTL0_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
498 (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
500 #define tRFC 17 /* clks - 1 (0..15) */ // 17
501 #define tXSR 19 /* clks - 1 (0..15) */ // 19
502 #define tXP 0 /* clks - 1 (0..7) */ // N/A
503 #define tWTR 0 /* clks - 1 (0..1) */ // N/A
504 #define tRP 1 /* clks - 2 (0..3) */ // 1
505 #define tMRD 1 /* clks - 1 (0..3) */ // 1
506 #define tWR 0 /* clks - 2 (0..1) */ // 0
507 #define tRAS 5 /* clks - 1 (0..15) */ // 5
508 #define tRRD 1 /* clks - 1 (0..3) */ // 1
509 #define tRCD 2 /* clks - 1 (0..7) */ // 2
510 #define tRC 8 /* 0: 20 *: clks - 1 (0..15) */ // 8
512 #define ESDCFG0_VAL ((((tRFC) - 10) << 28) | ((tXSR) << 24) | ((tXP) << 21) | \
513 ((tWTR) << 20) | ((tRP) << 18) | ((tMRD) << 16) | \
514 ((tRAS) << 12) | ((tRRD) << 10) | ((tWR) << 7) | \
515 ((tRCD) << 4) | ((tRC) << 0))
517 #define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
518 #define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
519 #define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
520 #define ESDMISC_AP(n) (((n) & 0xf) << 16)
521 #define ESDMISC_VAL (ESDMISC_AP(10) | ESDMISC_RALAT(RALAT) | \
522 (LHD << 5) | ESDMISC_DDR2_EN(0) | ESDMISC_DDR_EN(0))
532 .long 0 // 0x97f40000 - 0x1000
536 .long 0 // hab_super_root_key
540 #ifndef RAM_BANK1_SIZE
541 .long RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET
543 .long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
546 .long 0xB17219E9 // Fixed. can't change.
548 .long dcd_end - dcd_start
550 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
551 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
552 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
553 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
554 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
555 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL0_VAL)
556 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG0_VAL)
557 DCDGEN(4, ESDCTL_BASE_ADDR + 0x34, 0x00020000 | ((RALAT & 0x3) << 29))
558 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, ESDMISC_VAL)
559 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
562 .long REDBOOT_IMAGE_SIZE
565 SRC_BASE_ADDR_W: .long SRC_BASE_ADDR
566 WDOG_BASE_ADDR_W: .long WDOG_BASE_ADDR
567 AIPS1_PARAM: .word 0x77777777
568 M4IF_M4IF4_VAL: .word 0x00000203
569 M4IF_FIDBP_VAL: .word 0x00000a01
570 M4IF_FBPM0_VAL: .word 0x00000404
571 MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
572 CCM_CBCDR_VAL1: .word 0x19239145
573 CCM_CBCDR_VAL2: .word 0x13239145
574 CCM_CBCDR_VAL3: .word 0x61E35100
575 CCM_CBCMR_VAL1: .word 0x000010C0
576 CCM_CBCMR_VAL2: .word 0x000020C0
577 BASE_ADDR_PLL1: .long PLL1_BASE_ADDR
578 BASE_ADDR_PLL2: .long PLL2_BASE_ADDR
579 BASE_ADDR_PLL3: .long PLL3_BASE_ADDR
580 //PLL_VAL_0x222: .word 0x222
581 //PLL_VAL_0x232: .word 0x232
582 PLL_VAL_0x1232: .word 0x1232
583 W_DP_OP_800: .word DP_OP_800
584 W_DP_MFD_800: .word DP_MFD_800
585 W_DP_MFN_800: .word DP_MFN_800
586 W_DP_OP_700: .word DP_OP_700
587 W_DP_MFD_700: .word DP_MFD_700
588 W_DP_MFN_700: .word DP_MFN_700
589 W_DP_OP_400: .word DP_OP_400
590 W_DP_MFD_400: .word DP_MFD_400
591 W_DP_MFN_400: .word DP_MFN_400
592 W_DP_OP_532: .word DP_OP_532
593 W_DP_MFD_532: .word DP_MFD_532
594 W_DP_MFN_532: .word DP_MFN_532
595 W_DP_OP_665: .word DP_OP_665
596 W_DP_MFD_665: .word DP_MFD_665
597 W_DP_MFN_665: .word DP_MFN_665
598 W_DP_OP_216: .word DP_OP_216
599 W_DP_MFD_216: .word DP_MFD_216
600 W_DP_MFN_216: .word DP_MFN_216
601 PLATFORM_CLOCK_DIV: .word 0x00000124
603 #ifdef REMOVE_THIS_CRAP
604 CCM_VAL_0xA5A2A020: .word 0xA5A2A020
605 CCM_VAL_0x00C30321: .word 0x00C30321
608 /*----------------------------------------------------------------------*/
609 /* end of hal_platform_setup.h */
610 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */