1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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30 // or inline functions from this file, or you compile this file and link it
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/karo_tx51.h> // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #define CPU_CLK CYGNUM_HAL_ARM_TX51_CPU_CLK
54 #define SDRAM_CLK CYGNUM_HAL_ARM_TX51_SDRAM_CLK
56 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
57 #define PLATFORM_SETUP1 _platform_setup1
58 #define CYGHWR_HAL_ARM_HAS_MMU
60 #ifdef CYG_HAL_STARTUP_ROMRAM
61 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
64 #define TX51_NAND_PAGE_SIZE 2048
65 #define TX51_NAND_BLKS_PER_PAGE 64
67 #define DEBUG_LED_BIT 10
68 #define LED_GPIO_BASE GPIO4_BASE_ADDR
69 #define LED_MUX_OFFSET 0x1d0
70 #define LED_MUX_MODE 0x13
72 #define LED_ON LED_CTRL #1
73 #define LED_OFF LED_CTRL #0
75 #ifndef CYGOPT_HAL_ARM_TX51_DEBUG
83 #define CYGHWR_LED_MACRO LED_BLINK #\x
99 // switch user LED (GPIO4_10) on STK5
100 ldr r10, =LED_GPIO_BASE
104 movne r9, #(1 << DEBUG_LED_BIT) @ LED ON
105 moveq r9, #0 @ LED OFF
106 str r9, [r10, #GPIO_DR]
125 // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
126 ldr r10, =LED_GPIO_BASE
128 ldr r9, [r10, #GPIO_GDIR]
129 orr r9, r9, #(1 << DEBUG_LED_BIT)
130 str r9, [r10, #GPIO_GDIR]
132 ldr r10, =IOMUXC_BASE_ADDR
133 mov r9, #LED_MUX_MODE
134 str r9, [r10, #LED_MUX_OFFSET]
136 mov r9, #(1 << DEBUG_LED_BIT) @ LED ON
137 str r9, [r10, #GPIO_DR]
140 #define DCDGEN(type, addr, data) .long type, addr, data
142 #define PLATFORM_PREAMBLE flash_header
144 // This macro represents the initial startup code for the platform
145 .macro _platform_setup1
146 KARO_TX51_SETUP_START:
153 ldr r1, =ROM_BASE_ADDR
154 ldr r11, [r1, #ROM_SI_REV_OFFSET]
158 ldr r0, =GPC_BASE_ADDR
159 cmp r11, #0x10 // r11 contains the silicon rev
160 ldrls r1, =0x1FC00000
161 ldrhi r1, =0x1A800000
164 // Explicitly disable L2 cache
165 mrc 15, 0, r0, c1, c0, 1
167 mcr 15, 0, r0, c1, c0, 1
169 // reconfigure L2 cache aux control reg
170 mov r0, #0xC0 // tag RAM
171 add r0, r0, #0x4 // data RAM
172 orr r0, r0, #(1 << 24) // disable write allocate delay
173 orr r0, r0, #(1 << 23) // disable write allocate combine
174 orr r0, r0, #(1 << 22) // disable write allocate
176 @ cc is still set from "cmp r11, #0x10" above
177 orrls r0, r0, #(1 << 25) @ disable write combine for TO 2 and lower revs
179 mcr 15, 1, r0, c9, c0, 2
187 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
189 #endif /* CYG_HAL_STARTUP_ROMRAM */
193 Normal_Boot_Continue:
196 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
200 @ Set up a stack [for calling C code]
201 ldr r1, =__startup_stack
202 ldr r2, =RAM_BANK0_BASE
209 /* Workaround for arm erratum #709718 */
210 @ Setup PRRR so device is always mapped to non-shared
211 mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
213 mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
217 mrc MMU_CP, 0, r1, MMU_Control, c0
218 orr r1, r1, #7 @ enable MMU bit
219 orr r1, r1, #0x800 @ enable z bit
220 orr r1, r1, #(1 << 28) @ Enable TEX remap, workaround for L1 cache issue
221 mcr MMU_CP, 0, r1, MMU_Control, c0
223 /* Workaround for arm errata #621766 */
224 mrc MMU_CP, 0, r1, MMU_Control, c0, 1
225 orr r1, r1, #(1 << 5) @ enable L1NEON bit
226 mcr MMU_CP, 0, r1, MMU_Control, c0, 1
228 mov pc, r2 @ Change address spaces
232 .endm @ _platform_setup1
234 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
237 * Set all MPROTx to be non-bufferable, trusted for R/W,
238 * not forced to user-mode.
240 ldr r0, =AIPS1_CTRL_BASE_ADDR
244 ldr r0, =AIPS2_CTRL_BASE_ADDR
247 .endm /* init_aips */
250 ldr r0, =WDOG_BASE_ADDR
258 ldr r0, =CCM_BASE_ADDR
259 ldr r1, [r0, #CLKCTL_CCR]
263 orr r1, r1, #(1 << 12)
264 str r1, [r0, #CLKCTL_CCR]
266 ldr r1, [r0, #CLKCTL_CCSR]
267 bic r1, #(1 << 9) /* switch lp_apm to OSC */
268 str r1, [r0, #CLKCTL_CCSR]
270 /* Gate off clocks to the peripherals first */
272 str r1, [r0, #CLKCTL_CCGR0]
274 str r1, [r0, #CLKCTL_CCGR1]
275 str r1, [r0, #CLKCTL_CCGR2]
276 str r1, [r0, #CLKCTL_CCGR3]
279 str r1, [r0, #CLKCTL_CCGR4]
281 str r1, [r0, #CLKCTL_CCGR5]
283 str r1, [r0, #CLKCTL_CCGR6]
285 /* Disable IPU and HSC dividers */
287 str r1, [r0, #CLKCTL_CCDR]
289 /* Make sure to switch the DDR away from PLL 1 */
290 ldr r1, CCM_CBCDR_VAL1
291 str r1, [r0, #CLKCTL_CBCDR]
292 /* make sure divider effective */
294 ldr r1, [r0, #CLKCTL_CDHIPR]
298 /* Switch ARM to step clock */
299 ldr r1, [r0, #CLKCTL_CCSR]
301 str r1, [r0, #CLKCTL_CCSR]
312 /* Switch peripheral to PLL 3 */
313 ldr r1, CCM_CBCMR_VAL1
314 str r1, [r0, #CLKCTL_CBCMR]
316 ldr r1, CCM_CBCDR_VAL2
317 str r1, [r0, #CLKCTL_CBCDR]
321 /* Switch peripheral to PLL 2 */
322 ldr r1, CCM_CBCDR_VAL1
323 str r1, [r0, #CLKCTL_CBCDR]
324 /* Use lp_apm (24MHz) source for perclk */
325 ldr r1, CCM_CBCMR_VAL2
326 str r1, [r0, #CLKCTL_CBCMR]
330 /* Set the platform clock dividers */
331 ldr r2, =PLATFORM_BASE_ADDR
332 ldr r1, PLATFORM_CLOCK_DIV
333 str r1, [r2, #PLATFORM_ICGC]
335 /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
339 str r1, [r0, #CLKCTL_CACRR]
341 /* Switch ARM back to PLL 1. */
343 str r1, [r0, #CLKCTL_CCSR]
346 @ ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
347 ldr r1, CCM_CBCDR_VAL3
348 str r1, [r0, #CLKCTL_CBCDR]
350 /* Restore the default values in the Gate registers */
352 str r1, [r0, #CLKCTL_CCGR0]
353 str r1, [r0, #CLKCTL_CCGR1]
354 str r1, [r0, #CLKCTL_CCGR2]
355 str r1, [r0, #CLKCTL_CCGR3]
356 str r1, [r0, #CLKCTL_CCGR4]
357 str r1, [r0, #CLKCTL_CCGR5]
358 str r1, [r0, #CLKCTL_CCGR6]
360 /* Use PLL 2 for UART's, get 66.5MHz from it */
361 ldr r1, CCM_CSCMR1_VAL
362 str r1, [r0, #CLKCTL_CSCMR1]
363 ldr r1, CCM_CSCDR1_VAL
364 str r1, [r0, #CLKCTL_CSCDR1]
366 /* make sure divider effective */
368 ldr r1, [r0, #CLKCTL_CDHIPR]
373 str r1, [r0, #CLKCTL_CCDR]
375 @ for cko - for ARM div by 8
377 orr r1, r1, #0x00000F0
378 str r1, [r0, #CLKCTL_CCOSR]
380 ldr r1, [r0, #CLKCTL_CCR]
381 bic r1, #(1 << 8) /* switch off FPM */
382 str r1, [r0, #CLKCTL_CCR]
386 .macro setup_pll pll_nr, mhz
387 ldr r2, BASE_ADDR_\pll_nr
388 ldr r1, PLL_VAL_0x1232
389 str r1, [r2, #PLL_DP_CTL] @ Set DPLL ON (set UPEN bit); BRMO=1
391 str r1, [r2, #PLL_DP_CONFIG] @ Enable auto-restart AREN bit
394 str r1, [r2, #PLL_DP_OP]
395 str r1, [r2, #PLL_DP_HFS_OP]
397 ldr r1, W_DP_MFD_\mhz
398 str r1, [r2, #PLL_DP_MFD]
399 str r1, [r2, #PLL_DP_HFS_MFD]
401 ldr r1, W_DP_MFN_\mhz
402 str r1, [r2, #PLL_DP_MFN]
403 str r1, [r2, #PLL_DP_HFS_MFN]
406 str r1, [r2, #PLL_DP_CONFIG] @ Assert LDREQ
409 ldr r1, PLL_VAL_0x1232
410 str r1, [r2, #PLL_DP_CTL]
412 ldr r1, [r2, #PLL_DP_CTL]
419 ldr r1, =M4IF_BASE_ADDR
420 ldr r0, M4IF_M4IF4_VAL
421 str r0, [r1, #M4IF_MIF4]
423 /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
424 ldr r0, M4IF_FBPM0_VAL
425 str r0, [r1, #M4IF_FBPM0]
427 ldr r0, M4IF_FPWC_VAL
428 str r0, [r1, #M4IF_FPWC]
429 .endm /* init_m4if */
433 cmp r11, #0x10 // r11 contains the silicon rev
435 /* Decrease the DRAM SDCLK pads to HIGH Drive strength */
436 ldr r0, =IOMUXC_BASE_ADDR
439 /* Change the delay line configuration */
440 ldr r0, =ESDCTL_BASE_ADDR
442 str r1, [r0, #ESDCTL_ESDCDLY1]
444 str r1, [r0, #ESDCTL_ESDCDLY2]
446 str r1, [r0, #ESDCTL_ESDCDLY3]
448 str r1, [r0, #ESDCTL_ESDCDLY4]
450 str r1, [r0, #ESDCTL_ESDCDLY5]
454 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
455 #define PLATFORM_SETUP1
458 #define PLATFORM_VECTORS _platform_vectors
459 .macro _platform_vectors
463 .globl _KARO_STRUCT_SIZE
465 .word 0 // reserve space structure length
467 .globl _KARO_CECFG_START
470 .word 0 // reserve space for CE configuration
473 .globl _KARO_CECFG_END
478 .ascii "KARO TX51 " __DATE__ " " __TIME__
481 /* SDRAM timing setup */
485 #if SDRAM_SIZE <= SZ_128M
486 #define RA_BITS (13 - 11) /* row addr bits - 11 */
488 #define RA_BITS (14 - 11) /* row addr bits - 11 */
491 #define CA_BITS (10 - 8) /* 0-2: col addr bits - 8 3: rsrvd */
492 #define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
493 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
494 #define SRT 0 /* 0: disabled *: 1: self refr. ... */
495 #define PWDT 0 /* 0: disabled 1: precharge pwdn
496 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
497 #define ESDCTL_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
498 (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
500 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
502 .macro CK_VAL, name, clks, offs
506 .set \name, \clks - \offs
510 .macro NS_VAL, name, ns, offs
514 CK_VAL \name, NS_TO_CK(\ns), \offs
520 NS_VAL tRFC, 125, 10 /* clks - 10 (0..15) */
521 NS_VAL tXSR, 138, 25 /* clks - 25 (0..15) */
522 NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
523 CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
524 NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
525 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
526 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
527 NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
528 NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
529 NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
530 NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
532 /* MT46H64M32LF-5 or -6 */
533 NS_VAL tRFC, 72, 10 /* clks - 10 (0..15) */
534 NS_VAL tXSR, 113, 25 /* clks - 25 (0..15) */
535 CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
536 CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
537 NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
538 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
539 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
540 NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
541 NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
542 NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
543 NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
546 #define ESDCFG_VAL ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \
547 (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
548 (tRAS << 12) | (tRRD << 10) | (tWR << 7) | \
549 (tRCD << 4) | (tRC << 0))
553 #define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
554 #define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
555 #define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
556 #define ESDMISC_AP(n) (((n) & 0xf) << 16)
557 #define ESDMISC_VAL (ESDMISC_AP(10) | ESDMISC_RALAT(RALAT) | \
558 (LHD << 5) | ESDMISC_DDR2_EN(0) | ESDMISC_DDR_EN(0))
568 .long 0 // 0x97f40000 - 0x1000
572 .long 0 // hab_super_root_key
576 #ifndef RAM_BANK1_SIZE
577 .long RAM_BANK0_BASE + SDRAM_SIZE - REDBOOT_OFFSET
579 .long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
582 .long 0xB17219E9 // Fixed. can't change.
584 .long dcd_end - dcd_start
586 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
587 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
588 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
589 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
590 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
591 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL_VAL)
592 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG_VAL)
593 #ifdef RAM_BANK1_SIZE
594 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, ESDCTL_VAL)
595 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, ESDCFG_VAL)
597 DCDGEN(4, ESDCTL_BASE_ADDR + 0x34, 0x00020000 | ((RALAT & 0x3) << 29))
598 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, ESDMISC_VAL)
599 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
602 .long REDBOOT_IMAGE_SIZE
605 SRC_BASE_ADDR_W: .long SRC_BASE_ADDR
606 WDOG_BASE_ADDR_W: .long WDOG_BASE_ADDR
607 AIPS1_PARAM: .word 0x77777777
608 M4IF_FBPM0_VAL: .word 0x00000103
609 M4IF_M4IF4_VAL: .word 0x00230185
610 M4IF_FPWC_VAL: .word 0x00240126
611 MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
612 CCM_CBCDR_VAL1: .word 0x19239145
613 CCM_CBCDR_VAL2: .word 0x13239145
614 #if (CPU_CLK % SDRAM_CLK == 0)
615 CCM_CBCDR_VAL3: .word (((CPU_CLK + SDRAM_CLK - 1) / SDRAM_CLK - 1) << 27) | (1 << 30) | 0x01e35100
617 CCM_CBCDR_VAL3: .word 0x01e35100
623 CCM_CBCDR_VAL3: .word 0x59E35100
625 CCM_CBCDR_VAL3: .word 0x51E35100
629 #elif SDRAM_CLK == 166
631 CCM_CBCDR_VAL3: .word 0x01E35100
633 CCM_CBCDR_VAL3: .word 0x01E35100
642 CCM_CBCMR_VAL1: .word 0x000010C0
643 CCM_CBCMR_VAL2: .word 0x000020C0
644 CCM_CSCMR1_VAL: .word 0xA5A2A020
645 CCM_CSCDR1_VAL: .word 0x00C30321
646 BASE_ADDR_PLL1: .long PLL1_BASE_ADDR
647 BASE_ADDR_PLL2: .long PLL2_BASE_ADDR
648 BASE_ADDR_PLL3: .long PLL3_BASE_ADDR
649 PLL_VAL_0x1232: .word 0x1232
650 W_DP_OP_800: .word DP_OP_800
651 W_DP_MFD_800: .word DP_MFD_800
652 W_DP_MFN_800: .word DP_MFN_800
653 W_DP_OP_700: .word DP_OP_700
654 W_DP_MFD_700: .word DP_MFD_700
655 W_DP_MFN_700: .word DP_MFN_700
656 W_DP_OP_600: .word DP_OP_600
657 W_DP_MFD_600: .word DP_MFD_600
658 W_DP_MFN_600: .word DP_MFN_600
659 W_DP_OP_400: .word DP_OP_400
660 W_DP_MFD_400: .word DP_MFD_400
661 W_DP_MFN_400: .word DP_MFN_400
662 W_DP_OP_532: .word DP_OP_532
663 W_DP_MFD_532: .word DP_MFD_532
664 W_DP_MFN_532: .word DP_MFN_532
665 W_DP_OP_665: .word DP_OP_665
666 W_DP_MFD_665: .word DP_MFD_665
667 W_DP_MFN_665: .word DP_MFN_665
668 W_DP_OP_216: .word DP_OP_216
669 W_DP_MFD_216: .word DP_MFD_216
670 W_DP_MFN_216: .word DP_MFN_216
671 PLATFORM_CLOCK_DIV: .word 0x00000124
673 /*----------------------------------------------------------------------*/
674 /* end of hal_platform_setup.h */
675 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */