packages/hal/arm/mx51/karo/v1_0/src/mx51_fastlogo.c

   1 //==========================================================================
   2 //
   3 //      mx51_fastlogo.c
   4 //
   5 //      MX51 Fast Logo Implementation
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //==========================================================================
  41
  42 #include <cyg/io/ipu_common.h>
  43
  44 // DI counter definitions
  45 #define DI_COUNTER_BASECLK              0
  46 #define DI_COUNTER_IHSYNC               1
  47 #define DI_COUNTER_OHSYNC               2
  48 #define DI_COUNTER_OVSYNC               3
  49 #define DI_COUNTER_ALINE                4
  50 #define DI_COUNTER_ACLOCK               5
  51
  52 //extern display_buffer_info_t display_buffer;
  53 static display_buffer_info_t display_buffer;
  54
  55 void fastlogo_init(display_buffer_info_t *di)
  56 {
  57         display_buffer = *di;
  58 }
  59
  60 void fastlogo_dma(void)
  61 {
  62         ipu_channel_parameter_t ipu_channel_params;
  63
  64         ipu_idmac_channel_enable(display_buffer.channel, 0);
  65
  66         ipu_idmac_params_init(&ipu_channel_params);
  67         ipu_channel_params.channel = display_buffer.channel;
  68         ipu_channel_params.eba0 = display_buffer.startAddr / 8;
  69         ipu_channel_params.fw = display_buffer.width - 1;   /* frame width */
  70         ipu_channel_params.fh = display_buffer.height - 1;  /* frame height */
  71         ipu_channel_params.sl = (display_buffer.width * display_buffer.bpp) / 8 - 1;
  72         ipu_channel_params.npb = 31;    /* 16 pixels per burst */
  73         ipu_channel_params.pfs = 7;             /* 1->4:2:2 non-interleaved, 7->rgb */
  74
  75         switch (display_buffer.bpp) {
  76         case 32:
  77                 ipu_channel_params.bpp = 0;
  78                 break;
  79         case 24:
  80                 ipu_channel_params.bpp = 1;
  81                 break;
  82         case 18:
  83                 ipu_channel_params.bpp = 2;
  84                 break;
  85         case 16:
  86                 ipu_channel_params.bpp = 3;
  87                 break;
  88         default:
  89                 diag_printf("%s: unsupported bpp value: %d\n", __FUNCTION__,
  90                                         display_buffer.bpp);
  91                 return;
  92         }
  93
  94         switch (display_buffer.dataFormat) {
  95         case RGB565:
  96                 ipu_channel_params.wid0 = 5 - 1;
  97                 ipu_channel_params.wid1 = 6 - 1;
  98                 ipu_channel_params.wid2 = 5 - 1;
  99                 ipu_channel_params.wid3 = 0;
 100                 ipu_channel_params.ofs0 = 0;
 101                 ipu_channel_params.ofs1 = 5;
 102                 ipu_channel_params.ofs2 = 11;
 103                 ipu_channel_params.ofs3 = 16;
 104                 break;
 105
 106         case RGB666:
 107                 ipu_channel_params.wid0 = 6 - 1;
 108                 ipu_channel_params.wid1 = 6 - 1;
 109                 ipu_channel_params.wid2 = 6 - 1;
 110                 ipu_channel_params.wid3 = 0;
 111                 ipu_channel_params.ofs0 = 0;
 112                 ipu_channel_params.ofs1 = 6;
 113                 ipu_channel_params.ofs2 = 12;
 114                 ipu_channel_params.ofs3 = 18;
 115                 break;
 116
 117         case RGB888:
 118                 ipu_channel_params.wid0 = 8 - 1;
 119                 ipu_channel_params.wid1 = 8 - 1;
 120                 ipu_channel_params.wid2 = 8 - 1;
 121                 ipu_channel_params.wid3 = 0;
 122                 ipu_channel_params.ofs0 = 0;
 123                 ipu_channel_params.ofs1 = 8;
 124                 ipu_channel_params.ofs2 = 16;
 125                 ipu_channel_params.ofs3 = 24;
 126                 break;
 127
 128         case RGBA8888:
 129                 ipu_channel_params.wid0 = 8 - 1;
 130                 ipu_channel_params.wid1 = 8 - 1;
 131                 ipu_channel_params.wid2 = 8 - 1;
 132                 ipu_channel_params.wid3 = 8 - 1;
 133                 ipu_channel_params.ofs0 = 0;
 134                 ipu_channel_params.ofs1 = 8;
 135                 ipu_channel_params.ofs2 = 16;
 136                 ipu_channel_params.ofs3 = 24;
 137                 break;
 138
 139         default:
 140                 diag_printf("%s: unsupported data format: %d\n", __FUNCTION__,
 141                                         display_buffer.dataFormat);
 142                 return;
 143         }
 144         ipu_channel_params.bm = 0;
 145         ipu_channel_params.hf = 0;
 146         ipu_channel_params.vf = 0;
 147         ipu_channel_params.id = 0;
 148         ipu_idmac_interleaved_channel_config(ipu_channel_params);
 149
 150         ipu_idmac_channel_mode_sel(display_buffer.channel, 0);
 151         ipu_idmac_channel_enable(display_buffer.channel, 1);
 152 }
 153
 154 void fastlogo_dmfc(void)
 155 {
 156         ipu_dmfc_fifo_allocate(display_buffer.channel, 1, 0, 4);
 157 }
 158
 159 void fastlogo_dc(void)
 160 {
 161         const int display_port = 0;
 162
 163         //***************************************************/
 164         //DI CONFIGURATION
 165         //****************************************************/
 166         /* MICROCODE */
 167         dc_microcode_t microcode;
 168         microcode.addr = 4;
 169         microcode.stop = 1;
 170         microcode.opcode = "WROD";
 171         microcode.lf = 0;
 172         microcode.af = 0;
 173         microcode.operand = 0;
 174         microcode.mapping = 2;
 175         microcode.waveform = 1;
 176         microcode.gluelogic = 0;
 177         microcode.sync = 5;
 178         ipu_dc_microcode_config(microcode);
 179
 180         ipu_dc_microcode_event(1, "NEW_DATA", 1, 4);
 181
 182         /* WRITE_CHAN */
 183         ipu_dc_write_channel_config(display_buffer.channel, display_port, 0, 0);
 184
 185         /* DISP_CONF */
 186         ipu_dc_display_config(display_port, 2 /* paralell */, 0,
 187                                                 display_buffer.width);
 188
 189         /* output data pixel format */
 190         ipu_dc_map(1, RGB888);
 191 }
 192
 193 void fastlogo_di(void)
 194 {
 195         di_sync_wave_gen_t syncWaveformGen = { 0 };
 196         int clkUp, clkDown;
 197         int hSyncStartWidth = 36;
 198         int hSyncWidth = 96;
 199         int hSyncEndWidth = 76;
 200         int delayH2V = display_buffer.width;
 201         int hDisp = display_buffer.width;
 202         int vSyncStartWidth = 11;
 203         int vSyncWidth = 2;
 204         int vSyncEndWidth = 32;
 205         int vDisp = display_buffer.height;
 206         int ipuClk = 133000000;         // ipu clk is 133M
 207         int typPixClk = 24000000;//25175000;   // typical value of pixel clock
 208         int div = (int)((float)ipuClk / (float)typPixClk + 0.5);        // get the nearest value of typical pixel clock
 209
 210         /* DI0_SCR, set the screen height */
 211         ipu_di_screen_set(0, vDisp + vSyncStartWidth + vSyncWidth + vSyncEndWidth - 1);
 212
 213         /* set DI_PIN15 to be waveform according to DI data wave set 3 */
 214         ipu_di_pointer_config(0, 0, div - 1, div - 1, 0, 0, 0, 0, 0, 2, 0, 0);
 215
 216         /* set the up & down of data wave set 3. */
 217         ipu_di_waveform_config(0, 0, 2, 0, div * 2);    // one bit for fraction part
 218
 219         /* set clk for DI0, generate the base clock of DI0. */
 220         clkUp = div - 2;
 221         clkDown = clkUp * 2;
 222         ipu_di_bsclk_gen(0, div << 4, clkUp, clkDown);
 223
 224         /*
 225           DI0 configuration:
 226           hsync    -   DI0 pin 3
 227           vsync    -   DI0 pin 2
 228           data_en  -   DI0 pin 15
 229           clk      -   DI0 disp clk
 230           COUNTER 2  for VSYNC
 231           COUNTER 3  for HSYNC
 232         */
 233         /* internal HSYNC */
 234         syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncWidth + hSyncEndWidth - 1;
 235         syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
 236         syncWaveformGen.offsetValue = 0;
 237         syncWaveformGen.offsetResolution = 0;
 238         syncWaveformGen.cntAutoReload = 1;
 239         syncWaveformGen.stepRepeat = 0;
 240         syncWaveformGen.cntClrSel = 0;
 241         syncWaveformGen.cntPolarityGenEn = 0;
 242         syncWaveformGen.cntPolarityTrigSel = 0;
 243         syncWaveformGen.cntPolarityClrSel = 0;
 244         syncWaveformGen.cntUp = 0;
 245         syncWaveformGen.cntDown = 1;
 246         ipu_di_sync_config(0, DI_COUNTER_IHSYNC, syncWaveformGen);
 247
 248         /* OUTPUT HSYNC */
 249         syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncWidth + hSyncEndWidth - 1;
 250         syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
 251         syncWaveformGen.offsetValue = delayH2V;
 252         syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1;
 253         syncWaveformGen.cntAutoReload = 1;
 254         syncWaveformGen.stepRepeat = 0;
 255         syncWaveformGen.cntClrSel = 0;
 256         syncWaveformGen.cntPolarityGenEn = 0;
 257         syncWaveformGen.cntPolarityTrigSel = 0;
 258         syncWaveformGen.cntPolarityClrSel = 0;
 259         syncWaveformGen.cntUp = 0;
 260         syncWaveformGen.cntDown = div * hSyncWidth;
 261         ipu_di_sync_config(0, DI_COUNTER_OHSYNC, syncWaveformGen);
 262
 263         /* Output Vsync */
 264         syncWaveformGen.runValue = vDisp + vSyncStartWidth + vSyncWidth + vSyncEndWidth - 1;
 265         syncWaveformGen.runResolution = DI_COUNTER_IHSYNC + 1;
 266         syncWaveformGen.offsetValue = 0;
 267         syncWaveformGen.offsetResolution = 0;
 268         syncWaveformGen.cntAutoReload = 1;
 269         syncWaveformGen.stepRepeat = 0;
 270         syncWaveformGen.cntClrSel = 0;
 271         syncWaveformGen.cntPolarityGenEn = 1;
 272         syncWaveformGen.cntPolarityTrigSel = 2;
 273         syncWaveformGen.cntPolarityClrSel = 0;
 274         syncWaveformGen.cntUp = 0;
 275         syncWaveformGen.cntDown = vSyncWidth;
 276         ipu_di_sync_config(0, DI_COUNTER_OVSYNC, syncWaveformGen);
 277
 278         /* Active Lines start points */
 279         syncWaveformGen.runValue = 0;
 280         syncWaveformGen.runResolution = DI_COUNTER_OHSYNC + 1;
 281         syncWaveformGen.offsetValue = vSyncWidth;
 282         syncWaveformGen.offsetResolution = DI_COUNTER_OHSYNC + 1;
 283         syncWaveformGen.cntAutoReload = 0;
 284         syncWaveformGen.stepRepeat = vDisp;
 285         syncWaveformGen.cntClrSel = DI_COUNTER_OVSYNC + 1;
 286         syncWaveformGen.cntPolarityGenEn = 0;
 287         syncWaveformGen.cntPolarityTrigSel = 0;
 288         syncWaveformGen.cntPolarityClrSel = 0;
 289         syncWaveformGen.cntUp = 0;
 290         syncWaveformGen.cntDown = 0;
 291         ipu_di_sync_config(0, DI_COUNTER_ALINE, syncWaveformGen);
 292
 293         /* Active clock start points */
 294         syncWaveformGen.runValue = 0;
 295         syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
 296         syncWaveformGen.offsetValue = hSyncWidth;
 297         syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1;
 298         syncWaveformGen.cntAutoReload = 0;
 299         syncWaveformGen.stepRepeat = hDisp;
 300         syncWaveformGen.cntClrSel = DI_COUNTER_ALINE + 1;
 301         syncWaveformGen.cntPolarityGenEn = 0;
 302         syncWaveformGen.cntPolarityTrigSel = 0;
 303         syncWaveformGen.cntPolarityClrSel = 0;
 304         syncWaveformGen.cntUp = 0;
 305         syncWaveformGen.cntDown = 0;
 306         ipu_di_sync_config(0, DI_COUNTER_ACLOCK, syncWaveformGen);
 307
 308         ipu_di_general_set(0, 1, 2, 1, 0);
 309 }