packages/hal/arm/mx53/var/v2_0/include/hal_soc.h

   1 //==========================================================================
   2 //
   3 //      hal_soc.h
   4 //
   5 //      SoC chip definitions
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 // Copyright (C) 2002 Gary Thomas
  13 //
  14 // eCos is free software; you can redistribute it and/or modify it under
  15 // the terms of the GNU General Public License as published by the Free
  16 // Software Foundation; either version 2 or (at your option) any later version.
  17 //
  18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  21 // for more details.
  22 //
  23 // You should have received a copy of the GNU General Public License along
  24 // with eCos; if not, write to the Free Software Foundation, Inc.,
  25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  26 //
  27 // As a special exception, if other files instantiate templates or use macros
  28 // or inline functions from this file, or you compile this file and link it
  29 // with other works to produce a work based on this file, this file does not
  30 // by itself cause the resulting work to be covered by the GNU General Public
  31 // License. However the source code for this file must still be made available
  32 // in accordance with section (3) of the GNU General Public License.
  33 //
  34 // This exception does not invalidate any other reasons why a work based on
  35 // this file might be covered by the GNU General Public License.
  36 //
  37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  38 // at http://sources.redhat.com/ecos/ecos-license/
  39 // -------------------------------------------
  40 //####ECOSGPLCOPYRIGHTEND####
  41 //========================================================================*/
  42
  43 #ifndef __HAL_SOC_H__
  44 #define __HAL_SOC_H__
  45
  46 #ifdef __ASSEMBLER__
  47 #define UL(a)                           (a)
  48 #define VA(a)                           (a)
  49 #define REG8(a)                         (a)
  50 #define REG16(a)                        (a)
  51 #define REG32(a)                        (a)
  52
  53 #else /* __ASSEMBLER__ */
  54 #define UL(a)                           (a##UL)
  55 #define VA(a)                           ((void *)(a))
  56
  57 extern char HAL_PLATFORM_EXTRA[40];
  58 externC void plf_hardware_init(void);
  59 extern void increase_core_voltage(bool i);
  60
  61 #define REG8(a)                         (*(volatile unsigned char *)(a))
  62 #define REG16(a)                        (*(volatile unsigned short *)(a))
  63 #define REG32(a)                        (*(volatile unsigned int *)(a))
  64
  65 #define readb(a)                        (*(volatile unsigned char *)(a))
  66 #define readw(a)                        (*(volatile unsigned short *)(a))
  67 #define readl(a)                        (*(volatile unsigned int *)(a))
  68 #define writeb(v,a)                     (*(volatile unsigned char *)(a) = (v))
  69 #define writew(v,a)                     (*(volatile unsigned short *)(a) = (v))
  70 #define writel(v,a)                     (*(volatile unsigned int *)(a) = (v))
  71
  72 #endif /* __ASSEMBLER__ */
  73
  74 #include <cyg/hal/mx53_iomux.h>
  75
  76 /*
  77  * Default Memory Layout Definitions
  78  */
  79
  80 #define MXC_NAND_BASE_DUMMY 0
  81
  82 /*
  83  * UART Chip level Configuration that a user may not have to edit. These
  84  * configuration vary depending on how the UART module is integrated with
  85  * the ARM core
  86  */
  87 #define MXC_UART_NR 3
  88 /*!
  89  * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
  90  * Certain platforms need this bit to be set in order to receive Irda data.
  91  */
  92 #define MXC_UART_IR_RXDMUX                      0x0004
  93 /*!
  94  * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
  95  * Certain platforms need this bit to be set in order to receive UART data.
  96  */
  97 #define MXC_UART_RXDMUX                         0x0004
  98
  99 /*
 100    * ROM address
 101    */
 102 #define ROM_BASE_ADDR                           UL(0x00000000)
 103 //#define ROM_BASE_ADDR_VIRT                    VA(0x20000000)
 104
 105 //#define ROM_SI_REV_OFFSET                     0x48
 106
 107 #define PLATFORM_BASE_ADDR                      ARM_ELBOW_BASE_ADDR
 108 #define PLATFORM_ICGC                           0x14
 109
 110 /*
 111  * GPU control registers
 112  */
 113 #define IPU_CTRL_BASE_ADDR                      UL(0x18000000)
 114 #define GPU_2D_BASE_ADDR                        UL(0x20000000)
 115 #define GPU_3D_BASE_ADDR                        UL(0x30000000)
 116
 117 #define TZIC_BASE_ADDR                          UL(0x0FFFC000)
 118
 119 #define DEBUG_BASE_ADDR                         UL(0x40000000)
 120 #define DEBUG_ROM_ADDR                          (DEBUG_BASE_ADDR + 0x0)
 121 #define ETB_BASE_ADDR                           (DEBUG_BASE_ADDR + 0x00001000)
 122 #define ETM_BASE_ADDR                           (DEBUG_BASE_ADDR + 0x00002000)
 123 #define TPIU_BASE_ADDR                          (DEBUG_BASE_ADDR + 0x00003000)
 124 #define CTI0_BASE_ADDR                          (DEBUG_BASE_ADDR + 0x00004000)
 125 #define CTI1_BASE_ADDR                          (DEBUG_BASE_ADDR + 0x00005000)
 126 #define CTI2_BASE_ADDR                          (DEBUG_BASE_ADDR + 0x00006000)
 127 #define CTI3_BASE_ADDR                          (DEBUG_BASE_ADDR + 0x00007000)
 128 #define CORTEX_DBG_BASE_ADDR            (DEBUG_BASE_ADDR + 0x00008000)
 129
 130 /*
 131  * SPBA global module enabled #0
 132  */
 133 #define SPBA0_BASE_ADDR                         UL(0x50000000)
 134
 135 #define MMC_SDHC1_BASE_ADDR                     (SPBA0_BASE_ADDR + 0x00004000)
 136 #define ESDHC1_REG_BASE                         MMC_SDHC1_BASE_ADDR
 137 #define MMC_SDHC2_BASE_ADDR                     (SPBA0_BASE_ADDR + 0x00008000)
 138 #define UART3_BASE_ADDR                         (SPBA0_BASE_ADDR + 0x0000C000)
 139 //eCSPI1
 140 #define CSPI1_BASE_ADDR                         (SPBA0_BASE_ADDR + 0x00010000)
 141 #define SSI2_BASE_ADDR                          (SPBA0_BASE_ADDR + 0x00014000)
 142 #define ESAI1_BASE_ADDR                         (SPBA0_BASE_ADDR + 0x00018000)
 143 #define MMC_SDHC3_BASE_ADDR                     (SPBA0_BASE_ADDR + 0x00020000)
 144 #define MMC_SDHC4_BASE_ADDR                     (SPBA0_BASE_ADDR + 0x00024000)
 145 #define SPDIF_BASE_ADDR                         (SPBA0_BASE_ADDR + 0x00028000)
 146 #define ASRC_BASE_ADDR                          (SPBA0_BASE_ADDR + 0x0002C000)
 147 #define ATA_DMA_BASE_ADDR                       (SPBA0_BASE_ADDR + 0x00030000)
 148 #define SPBA_CTRL_BASE_ADDR                     (SPBA0_BASE_ADDR + 0x0003C000)
 149
 150 /*
 151  * AIPS 1
 152  */
 153 #define AIPS1_BASE_ADDR                         UL(0x53F00000)
 154 #define AIPS1_CTRL_BASE_ADDR            AIPS1_BASE_ADDR
 155 #define USBOH3_BASE_ADDR                        (AIPS1_BASE_ADDR + 0x00080000)
 156 #define GPIO1_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x00084000)
 157 #define GPIO2_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x00088000)
 158 #define GPIO3_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x0008C000)
 159 #define GPIO4_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x00090000)
 160 #define KPP_BASE_ADDR                           (AIPS1_BASE_ADDR + 0x00094000)
 161 #define WDOG1_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x00098000)
 162 #define WDOG_BASE_ADDR                          WDOG1_BASE_ADDR
 163 #define WDOG2_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x0009C000)
 164 #define GPT_BASE_ADDR                           (AIPS1_BASE_ADDR + 0x000A0000)
 165 #define SRTC_BASE_ADDR                          (AIPS1_BASE_ADDR + 0x000A4000)
 166 #define IOMUXC_BASE_ADDR                        (AIPS1_BASE_ADDR + 0x000A8000)
 167 #define EPIT1_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x000AC000)
 168 #define EPIT2_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x000B0000)
 169 #define PWM1_BASE_ADDR                          (AIPS1_BASE_ADDR + 0x000B4000)
 170 #define PWM2_BASE_ADDR                          (AIPS1_BASE_ADDR + 0x000B8000)
 171 #define UART1_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x000BC000)
 172 #define UART2_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x000C0000)
 173
 174 #define SRC_BASE_ADDR                           (AIPS1_BASE_ADDR + 0x000D0000)
 175 #define CCM_BASE_ADDR                           (AIPS1_BASE_ADDR + 0x000D4000)
 176 #define GPC_BASE_ADDR                           (AIPS1_BASE_ADDR + 0x000D8000)
 177 #define GPIO5_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x000DC000)
 178 #define GPIO6_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x000E0000)
 179 #define GPIO7_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x000E4000)
 180 #define PATA_BASE_ADDR                          (AIPS1_BASE_ADDR + 0x000E8000)
 181 #define I2C3_BASE_ADDR                          (AIPS1_BASE_ADDR + 0x000EC000)
 182
 183 #define UART4_BASE_ADDR                         (AIPS1_BASE_ADDR + 0x000F0000)
 184
 185 /*
 186  * AIPS 2
 187  */
 188 #define AIPS2_BASE_ADDR                         UL(0x63F00000)
 189 #define AIPS2_CTRL_BASE_ADDR            AIPS2_BASE_ADDR
 190 #define PLL1_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x00080000)
 191 #define PLL2_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x00084000)
 192 #define PLL3_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x00088000)
 193 #define PLL4_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x0008C000)
 194 #define UART5_BASE_ADDR                         (AIPS2_BASE_ADDR + 0x00090000)
 195 #define AHBMAX_BASE_ADDR                        (AIPS2_BASE_ADDR + 0x00094000)
 196 #define MAX_BASE_ADDR                           AHBMAX_BASE_ADDR
 197 #define IIM_BASE_ADDR                           (AIPS2_BASE_ADDR + 0x00098000)
 198 #define CSU_BASE_ADDR                           (AIPS2_BASE_ADDR + 0x0009C000)
 199 #define ARM_ELBOW_BASE_ADDR                     (AIPS2_BASE_ADDR + 0x000A0000)
 200 #define OWIRE_BASE_ADDR                         (AIPS2_BASE_ADDR + 0x000A4000)
 201 #define FIRI_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000A8000)
 202 // eCSPI2
 203 #define CSPI2_BASE_ADDR                         (AIPS2_BASE_ADDR + 0x000AC000)
 204 #define SDMA_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000B0000)
 205 #define SCC_BASE_ADDR                           (AIPS2_BASE_ADDR + 0x000B4000)
 206 #define ROMCP_BASE_ADDR                         (AIPS2_BASE_ADDR + 0x000B8000)
 207 #define RTIC_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000BC000)
 208 // actually cspi1
 209 #define CSPI3_BASE_ADDR                         (AIPS2_BASE_ADDR + 0x000C0000)
 210 #define I2C2_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000C4000)
 211 #define I2C1_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000C8000)
 212 #define I2C_BASE_ADDR                           I2C1_BASE_ADDR
 213 #define SSI1_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000CC000)
 214 #define AUDMUX_BASE_ADDR                        (AIPS2_BASE_ADDR + 0x000D0000)
 215
 216 #define M4IF_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000D8000)
 217 #define ESDCTL_BASE_ADDR                        (AIPS2_BASE_ADDR + 0x000D9000)
 218 #define WEIM_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000DA000)
 219 #define NFC_IP_BASE                                     (AIPS2_BASE_ADDR + 0x000DB000)
 220 #define EMI_BASE_ADDR                           (AIPS2_BASE_ADDR + 0x000DBF00)
 221 //#define MIPI_HSC_BASE_ADDR                    (AIPS2_BASE_ADDR + 0x000DC000)
 222 //#define ATA_BASE_ADDR                         (AIPS2_BASE_ADDR + 0x000E0000)
 223 //#define SIM_BASE_ADDR                         (AIPS2_BASE_ADDR + 0x000E4000)
 224 #define SSI3_BASE_ADDR                          (AIPS2_BASE_ADDR + 0x000E8000)
 225 #define FEC_BASE_ADDR                           (AIPS2_BASE_ADDR + 0x000EC000)
 226 #define SOC_FEC_BASE                            FEC_BASE_ADDR
 227 #define TVE_BASE_ADDR                           (AIPS2_BASE_ADDR + 0x000F0000)
 228 #define VPU_BASE_ADDR                           (AIPS2_BASE_ADDR + 0x000F4000)
 229 #define SAHARA_BASE_ADDR                        (AIPS2_BASE_ADDR + 0x000F8000)
 230
 231 /*
 232  * Memory regions and CS
 233  */
 234 #define CSD0_BASE_ADDR                          UL(0x70000000)
 235 #define CSD1_BASE_ADDR                          UL(0xB0000000)
 236 #define CS0_BASE_ADDR                           UL(0xF0000000)
 237 #define CS1_BASE_ADDR                           UL(0xF4000000)
 238
 239 /*
 240  * NFC internal RAM
 241  */
 242 #define NFC_BASE_ADDR_AXI                       UL(0xF7FF0000)
 243 #define NFC_BASE                                        NFC_BASE_ADDR_AXI
 244
 245 /*
 246  * IRAM
 247  */
 248 #define IRAM_BASE_ADDR                          UL(0xF8000000)  /* 128K internal ram */
 249
 250 /*
 251  * Graphics Memory of GPU
 252  */
 253 #define GPU_MEM_BASE_ADDR                       UL(0xF8020000)
 254
 255 /*
 256  * Number of GPIO ports as defined in the IC Spec
 257  */
 258 #define GPIO_PORT_NUM                           7
 259 /*
 260  * Number of GPIO pins per port
 261  */
 262 #define GPIO_NUM_PIN                            32
 263
 264 /* CCM */
 265 #define CLKCTL_CCR                                      0x00
 266 #define CLKCTL_CCDR                                     0x04
 267 #define CLKCTL_CSR                                      0x08
 268 #define CLKCTL_CCSR                                     0x0C
 269 #define CLKCTL_CACRR                            0x10
 270 #define CLKCTL_CBCDR                            0x14
 271 #define CLKCTL_CBCMR                            0x18
 272 #define CLKCTL_CSCMR1                           0x1C
 273 #define CLKCTL_CSCMR2                           0x20
 274 #define CLKCTL_CSCDR1                           0x24
 275 #define CLKCTL_CS1CDR                           0x28
 276 #define CLKCTL_CS2CDR                           0x2C
 277 #define CLKCTL_CDCDR                            0x30
 278 #define CLKCTL_CHSCCDR                          0x34
 279 #define CLKCTL_CSCDR2                           0x38
 280 #define CLKCTL_CSCDR3                           0x3C
 281 #define CLKCTL_CSCDR4                           0x40
 282 #define CLKCTL_CWDR                                     0x44
 283 #define CLKCTL_CDHIPR                           0x48
 284 #define CLKCTL_CDCR                                     0x4C
 285 #define CLKCTL_CTOR                                     0x50
 286 #define CLKCTL_CLPCR                            0x54
 287 #define CLKCTL_CISR                                     0x58
 288 #define CLKCTL_CIMR                                     0x5C
 289 #define CLKCTL_CCOSR                            0x60
 290 #define CLKCTL_CGPR                                     0x64
 291 #define CLKCTL_CCGR0                            0x68
 292 #define CLKCTL_CCGR1                            0x6C
 293 #define CLKCTL_CCGR2                            0x70
 294 #define CLKCTL_CCGR3                            0x74
 295 #define CLKCTL_CCGR4                            0x78
 296 #define CLKCTL_CCGR5                            0x7C
 297 #define CLKCTL_CCGR6                            0x80
 298 #define CLKCTL_CCGR7                            0x84
 299 #define CLKCTL_CMEOR                            0x88
 300
 301 #define FREQ_24MHZ                                      24000000
 302 #define FREQ_32768HZ                            (32768 * 1024)
 303 #define FREQ_38400HZ                            (38400 * 1024)
 304 #define FREQ_32000HZ                            (32000 * 1024)
 305 #define PLL_REF_CLK                                     FREQ_24MHZ
 306 #define CKIH                                            22579200
 307 //#define PLL_REF_CLK  FREQ_32768HZ
 308 //#define PLL_REF_CLK  FREQ_32000HZ
 309
 310 /* WEIM registers */
 311 #define CSGCR1                                          0x00
 312 #define CSGCR2                                          0x04
 313 #define CSRCR1                                          0x08
 314 #define CSRCR2                                          0x0C
 315 #define CSWCR1                                          0x10
 316
 317 /* M4IF */
 318 #define M4IF_FBPM0                                      0x40
 319 #define M4IF_FBPM1                                      0x44
 320 #define M4IF_FIDBP                                      0x48
 321 #define M4IF_MIF4                                       0x48
 322 #define M4IF_FPWC                                       0x9C
 323
 324 /* ESDCTL */
 325 #define ESDCTL_ESDCTL0                          0x00
 326 #define ESDCTL_ESDCFG0                          0x04
 327 #define ESDCTL_ESDCTL1                          0x08
 328 #define ESDCTL_ESDCFG1                          0x0C
 329 #define ESDCTL_ESDMISC                          0x10
 330 #define ESDCTL_ESDSCR                           0x14
 331 #define ESDCTL_ESDCDLY1                         0x20
 332 #define ESDCTL_ESDCDLY2                         0x24
 333 #define ESDCTL_ESDCDLY3                         0x28
 334 #define ESDCTL_ESDCDLY4                         0x2C
 335 #define ESDCTL_ESDCDLY5                         0x30
 336 #define ESDCTL_ESDCDLYGD                        0x34
 337
 338 /* DPLL */
 339 #define PLL_DP_CTL                                      0x00
 340 #define PLL_DP_CONFIG                           0x04
 341 #define PLL_DP_OP                                       0x08
 342 #define PLL_DP_MFD                                      0x0C
 343 #define PLL_DP_MFN                                      0x10
 344 #define PLL_DP_MFNMINUS                         0x14
 345 #define PLL_DP_MFNPLUS                          0x18
 346 #define PLL_DP_HFS_OP                           0x1C
 347 #define PLL_DP_HFS_MFD                          0x20
 348 #define PLL_DP_HFS_MFN                          0x24
 349 #define PLL_DP_TOGC                                     0x28
 350 #define PLL_DP_DESTAT                           0x2C
 351
 352 #define CHIP_REV_1_0                            0x0              /* PASS 1.0 */
 353 #define CHIP_REV_1_1                            0x1              /* PASS 1.1 */
 354 #define CHIP_REV_2_0                            0x2              /* PASS 2.0 */
 355 #define CHIP_LATEST                                     CHIP_REV_1_1
 356
 357 #define IIM_STAT_OFF                            0x00
 358 #define IIM_STAT_BUSY                           (1 << 7)
 359 #define IIM_STAT_PRGD                           (1 << 1)
 360 #define IIM_STAT_SNSD                           (1 << 0)
 361 #define IIM_STATM_OFF                           0x04
 362 #define IIM_ERR_OFF                                     0x08
 363 #define IIM_ERR_PRGE                            (1 << 7)
 364 #define IIM_ERR_WPE                                     (1 << 6)
 365 #define IIM_ERR_OPE                                     (1 << 5)
 366 #define IIM_ERR_RPE                                     (1 << 4)
 367 #define IIM_ERR_WLRE                            (1 << 3)
 368 #define IIM_ERR_SNSE                            (1 << 2)
 369 #define IIM_ERR_PARITYE                         (1 << 1)
 370 #define IIM_EMASK_OFF                           0x0C
 371 #define IIM_FCTL_OFF                            0x10
 372 #define IIM_UA_OFF                                      0x14
 373 #define IIM_LA_OFF                                      0x18
 374 #define IIM_SDAT_OFF                            0x1C
 375 #define IIM_PREV_OFF                            0x20
 376 #define IIM_SREV_OFF                            0x24
 377 #define IIM_PREG_P_OFF                          0x28
 378 #define IIM_SCS0_OFF                            0x2C
 379 #define IIM_SCS1_P_OFF                          0x30
 380 #define IIM_SCS2_OFF                            0x34
 381 #define IIM_SCS3_P_OFF                          0x38
 382
 383 #define IIM_PROD_REV_SH                         3
 384 #define IIM_PROD_REV_LEN                        5
 385 #define IIM_SREV_REV_SH                         4
 386 #define IIM_SREV_REV_LEN                        4
 387 #define PROD_SIGNATURE_MX53                     0x1
 388
 389 #define EPIT_BASE_ADDR                          EPIT1_BASE_ADDR
 390 #define EPITCR                                          0x00
 391 #define EPITSR                                          0x04
 392 #define EPITLR                                          0x08
 393 #define EPITCMPR                                        0x0C
 394 #define EPITCNR                                         0x10
 395
 396 #define GPTCR                                           0x00
 397 #define GPTPR                                           0x04
 398 #define GPTSR                                           0x08
 399 #define GPTIR                                           0x0C
 400 #define GPTOCR1                                         0x10
 401 #define GPTOCR2                                         0x14
 402 #define GPTOCR3                                         0x18
 403 #define GPTICR1                                         0x1C
 404 #define GPTICR2                                         0x20
 405 #define GPTCNT                                          0x24
 406
 407 /* Assuming 24MHz input clock with doubler ON */
 408 /*                                                                        MFI             PDF */
 409 #define DP_OP_1000                                      ((10 << 4) + ((1 - 1) << 0))
 410 #define DP_MFD_1000                                     (12 - 1)
 411 #define DP_MFN_1000                                     5
 412
 413 #define DP_OP_850                                       ((8 << 4) + ((1 - 1) << 0))
 414 #define DP_MFD_850                                      (48 - 1)
 415 #define DP_MFN_850                                      41
 416
 417 #define DP_OP_800                                       ((8 << 4) + ((1 - 1) << 0))
 418 #define DP_MFD_800                                      (3 - 1)
 419 #define DP_MFN_800                                      1
 420
 421 #define DP_OP_700                                       ((7 << 4) + ((1 - 1) << 0))
 422 #define DP_MFD_700                                      (24 - 1)
 423 #define DP_MFN_700                                      7
 424
 425 #define DP_OP_400                                       ((8 << 4) + ((2 - 1) << 0))
 426 #define DP_MFD_400                                      (3 - 1)
 427 #define DP_MFN_400                                      1
 428
 429 #define DP_OP_532                                       ((5 << 4) + ((1 - 1) << 0))
 430 #define DP_MFD_532                                      (24 - 1)
 431 #define DP_MFN_532                                      13
 432
 433 #define DP_OP_665                                       ((6 << 4) + ((1 - 1) << 0))
 434 #define DP_MFD_665                                      (96 - 1)
 435 #define DP_MFN_665                                      89
 436
 437 #define DP_OP_666                                       ((6 << 4) + ((1 - 1) << 0))
 438 #define DP_MFD_666                                      (16 - 1)
 439 #define DP_MFN_666                                      15
 440
 441 #define DP_OP_333                                       ((6 << 4) + ((2 - 1) << 0))
 442 #define DP_MFD_333                                      (16 - 1)
 443 #define DP_MFN_333                                      15
 444
 445 #define DP_OP_266                                       ((5 << 4) + ((2 - 1) << 0))
 446 #define DP_MFD_266                                      (24 - 1)
 447 #define DP_MFN_266                                      13
 448
 449 #define DP_OP_216                                       ((9 << 4) + ((4 - 1) << 0))
 450 #define DP_MFD_216                                      (1 - 1)
 451 #define DP_MFN_216                                      0
 452
 453 #define PROD_SIGNATURE_SUPPORTED  PROD_SIGNATURE_MX51
 454
 455 #define CHIP_VERSION_NONE                       0xFFFFFFFF              // invalid product ID
 456 #define CHIP_VERSION_UNKNOWN            0xDEADBEEF              // invalid chip rev
 457
 458 #define PART_NUMBER_OFFSET                      12
 459 #define MAJOR_NUMBER_OFFSET                     4
 460 #define MINOR_NUMBER_OFFSET                     0
 461
 462 //#define BARKER_CODE_SWAP_LOC          0x404
 463 #define BARKER_CODE_VAL                         0xB1
 464 #define NFC_V3_0
 465
 466 // This defines the register base for the NAND AXI registers
 467 #define NAND_REG_BASE                           (NFC_BASE_ADDR_AXI + 0x1E00)
 468
 469 #define NAND_CMD_REG                            (NAND_REG_BASE + 0x00)
 470 #define NAND_ADD0_REG                           (NAND_REG_BASE + 0x04)
 471 #define NAND_ADD1_REG                           (NAND_REG_BASE + 0x08)
 472 #define NAND_ADD2_REG                           (NAND_REG_BASE + 0x0C)
 473 #define NAND_ADD3_REG                           (NAND_REG_BASE + 0x10)
 474 #define NAND_ADD4_REG                           (NAND_REG_BASE + 0x14)
 475 #define NAND_ADD5_REG                           (NAND_REG_BASE + 0x18)
 476 #define NAND_ADD6_REG                           (NAND_REG_BASE + 0x1C)
 477 #define NAND_ADD7_REG                           (NAND_REG_BASE + 0x20)
 478 #define NAND_ADD8_REG                           (NAND_REG_BASE + 0x24)
 479 #define NAND_ADD9_REG                           (NAND_REG_BASE + 0x28)
 480 #define NAND_ADD10_REG                          (NAND_REG_BASE + 0x2C)
 481 #define NAND_ADD11_REG                          (NAND_REG_BASE + 0x30)
 482
 483 #define NAND_CONFIGURATION1_REG         (NAND_REG_BASE + 0x34)
 484 #define NAND_CONFIGURATION1_NFC_RST     (1 << 2)
 485 #define NAND_CONFIGURATION1_NF_CE       (1 << 1)
 486 #define NAND_CONFIGURATION1_SP_EN       (1 << 0)
 487
 488 #define NAND_ECC_STATUS_RESULT_REG      (NAND_REG_BASE + 0x38)
 489
 490 #define NAND_STATUS_SUM_REG                     (NAND_REG_BASE + 0x3C)
 491
 492 #define NAND_LAUNCH_REG                         (NAND_REG_BASE + 0x40)
 493 #define NAND_LAUNCH_FCMD                        (1 << 0)
 494 #define NAND_LAUNCH_FADD                        (1 << 1)
 495 #define NAND_LAUNCH_FDI                         (1 << 2)
 496 #define NAND_LAUNCH_AUTO_PROG           (1 << 6)
 497 #define NAND_LAUNCH_AUTO_READ           (1 << 7)
 498 #define NAND_LAUNCH_AUTO_READ_CONT      (1 << 8)
 499 #define NAND_LAUNCH_AUTO_ERASE          (1 << 9)
 500 #define NAND_LAUNCH_COPY_BACK0          (1 << 10)
 501 #define NAND_LAUNCH_COPY_BACK1          (1 << 11)
 502 #define NAND_LAUNCH_AUTO_STAT           (1 << 12)
 503
 504 #define NFC_WR_PROT_REG                         (NFC_IP_BASE + 0x00)
 505 #define UNLOCK_BLK_ADD0_REG                     (NFC_IP_BASE + 0x04)
 506 #define UNLOCK_BLK_ADD1_REG                     (NFC_IP_BASE + 0x08)
 507 #define UNLOCK_BLK_ADD2_REG                     (NFC_IP_BASE + 0x0C)
 508 #define UNLOCK_BLK_ADD3_REG                     (NFC_IP_BASE + 0x10)
 509 #define UNLOCK_BLK_ADD4_REG                     (NFC_IP_BASE + 0x14)
 510 #define UNLOCK_BLK_ADD5_REG                     (NFC_IP_BASE + 0x18)
 511 #define UNLOCK_BLK_ADD6_REG                     (NFC_IP_BASE + 0x1C)
 512 #define UNLOCK_BLK_ADD7_REG                     (NFC_IP_BASE + 0x20)
 513
 514 #define NFC_FLASH_CONFIG2_REG           (NFC_IP_BASE + 0x24)
 515 #define NFC_FLASH_CONFIG2_ECC_EN        (1 << 3)
 516
 517 #define NFC_FLASH_CONFIG3_REG           (NFC_IP_BASE + 0x28)
 518
 519 #define NFC_IPC_REG                                     (NFC_IP_BASE + 0x2C)
 520 #define NFC_IPC_INT                                     (1 << 31)
 521 #define NFC_IPC_AUTO_DONE                       (1 << 30)
 522 #define NFC_IPC_LPS                                     (1 << 29)
 523 #define NFC_IPC_RB_B                            (1 << 28)
 524 #define NFC_IPC_CACK                            (1 << 1)
 525 #define NFC_IPC_CREQ                            (1 << 0)
 526 #define NFC_AXI_ERR_ADD_REG                     (NFC_IP_BASE + 0x30)
 527
 528 #define MXC_MMC_BASE_DUMMY                      0x00000000
 529
 530 #define NAND_FLASH_BOOT                         (1 << 28)
 531 #define FROM_NAND_FLASH                         NAND_FLASH_BOOT
 532
 533 #define SDRAM_NON_FLASH_BOOT            (1 << 29)
 534
 535 #define MMC_FLASH_BOOT                          (1 << 30)
 536 #define FROM_MMC_FLASH                          MMC_FLASH_BOOT
 537
 538 #define SPI_NOR_FLASH_BOOT                      0x80000000
 539 #define FROM_SPI_NOR_FLASH                      SPI_NOR_FLASH_BOOT
 540
 541 #define IS_BOOTING_FROM_NAND()          1
 542 #define IS_BOOTING_FROM_SPI_NOR()       0
 543 #define IS_BOOTING_FROM_NOR()           0
 544 #define IS_BOOTING_FROM_SDRAM()         0
 545 #define IS_BOOTING_FROM_MMC()           0
 546
 547 #define IS_FIS_FROM_NAND()                      1
 548 #define IS_FIS_FROM_NOR()                       0
 549
 550 #define SOC_MAC_ADDR_FUSE_BANK          1
 551 #define SOC_MAC_ADDR_FUSE                       9
 552 #define SOC_MAC_ADDR_LOCK_FUSE          0
 553 #define SOC_MAC_ADDR_LOCK_BIT           4
 554
 555 /*
 556  * This macro is used to get certain bit field from a number
 557  */
 558 #define MXC_GET_FIELD(val, len, sh)     ((val >> sh) & ((1 << len) - 1))
 559
 560 /*
 561  * This macro is used to set certain bit field inside a number
 562  */
 563 #define MXC_SET_FIELD(val, len, sh, nval)       ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
 564
 565 #define L2CC_ENABLED
 566 #define UART_WIDTH_32             /* internal UART is 32bit access only */
 567
 568 #if !defined(__ASSEMBLER__)
 569 extern void fuse_blow_row(int bank, int row, int value);
 570 extern unsigned int sense_fuse(int bank, int row, int bit);
 571
 572 void cyg_hal_plf_serial_init(void);
 573 void cyg_hal_plf_serial_stop(void);
 574 void hal_delay_us(unsigned int usecs);
 575 #define HAL_DELAY_US(n)         hal_delay_us(n)
 576 extern int _mxc_fis;
 577 extern unsigned int system_rev;
 578
 579 enum plls {
 580         PLL1,
 581         PLL2,
 582         PLL3,
 583         PLL4,
 584 };
 585
 586 enum main_clocks {
 587         CPU_CLK,
 588         AHB_CLK,
 589         IPG_CLK,
 590         IPG_PER_CLK,
 591         DDR_CLK,
 592         NFC_CLK,
 593         USB_CLK,
 594         AXI_A_CLK,
 595         AXI_B_CLK,
 596         EMI_SLOW_CLK,
 597 };
 598
 599 enum peri_clocks {
 600         UART1_BAUD,
 601         UART2_BAUD,
 602         UART3_BAUD,
 603         SSI1_BAUD,
 604         SSI2_BAUD,
 605         CSI_BAUD,
 606         MSTICK1_CLK,
 607         MSTICK2_CLK,
 608         SPI1_CLK = CSPI1_BASE_ADDR,
 609         SPI2_CLK = CSPI2_BASE_ADDR,
 610 };
 611
 612 extern unsigned int pll_clock(enum plls pll);
 613
 614 extern unsigned int get_main_clock(enum main_clocks clk);
 615
 616 extern unsigned int get_peri_clock(enum peri_clocks clk);
 617
 618 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
 619
 620 extern void increase_core_voltage(bool);
 621
 622 #endif //#if !defined(__ASSEMBLER__)
 623
 624 #endif /* __HAL_SOC_H__ */