1 #ifndef CYGONCE_FSL_BOARD_H
2 #define CYGONCE_FSL_BOARD_H
4 //=============================================================================
6 // Platform specific support (register layout, etc)
8 //=============================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
10 // -------------------------------------------
11 // This file is part of eCos, the Embedded Configurable Operating System.
12 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
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19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
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38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //===========================================================================
43 #include <cyg/hal/hal_soc.h> // Hardware definitions
45 #define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
46 #define PBC_VERSION PBC_BASE
47 #define PBC_BSTAT (PBC_BASE + 0x2)
48 #define PBC_BCTL1_SET (PBC_BASE + 0x4)
49 #define PBC_BCTL1_CLR (PBC_BASE + 0x6)
50 #define PBC_BCTL2_SET (PBC_BASE + 0x8)
51 #define PBC_BCTL2_CLR (PBC_BASE + 0xA)
53 #define BOARD_CS_LAN_BASE (PBC_BASE + 0x00020000 + 0x300)
54 #define BOARD_CS_UART_BASE (PBC_BASE + 0x00010000)
56 //#define APCLK_399_133_66 /* AP_CLK: 399 MHz, AP_AHB_CLK = 133 MHz, AP_IP_CLK = 66.5 MHz */
57 #define APCLK_532_133_66 /* AP_CLK: 532 MHz, AP_AHB_CLK = 133 MHz, AP_IP_CLK = 66.5 MHz */
58 #define USB_PLL_CLK_48 /* USB_PLL_CLK: 48 MHz */
61 * Following definitions assume CKIH_X2 PLL reference (33.6 MHz). PLL factor
62 * values come from Example PLL settings table in IC spec.
65 #ifdef APCLK_532_133_66
68 #define ADPLL_MFN (-140)
69 #define ADPLL_MFD (1680 - 1)
70 #define ARM_DIV 8 /* 8 => /1 */
73 #define NFC_DIV 5 /* 5 => /6 */
76 #ifdef APCLK_399_133_66
79 #define ADPLL_MFN (-105)
80 #define ADPLL_MFD (1680 - 1)
81 #define ARM_DIV 8 /* 8 => /1 */
84 #define NFC_DIV 5 /* 5 => /6 */
87 #ifdef APCLK_266_133_66
90 #define ADPLL_MFN (-140)
91 #define ADPLL_MFD (1680 - 1)
92 #define ARM_DIV 8 /* 8 => /1 */
95 #define NFC_DIV 5 /* 5 => /6 */
98 #define ADPLL_OP ((ADPLL_MFI << 4) | (ADPLL_PDF - 1))
99 #define CRM_AP_DIV ((ARM_DIV << 8) | (AHB_DIV << 4) | (IP_DIV))
101 * Following definitions assume CKIH PLL reference (16.8 MHz).
103 #ifdef USB_PLL_CLK_48
104 #define UDPLL_PDF (1)
105 #define UDPLL_MFI (5)
106 #define UDPLL_MFN (7142)
107 #define UDPLL_MFD (10000 - 1)
108 #define UDPLL_OP ((UDPLL_MFI << 4) | (UDPLL_PDF - 1))
109 #define USB_DIV 2 /* 2 => /4 */
110 #define FIRI_DIV 1 /* 1 => /2 */
111 #define CS_DIV 0x19 /* 0x19 => /12.5 */
114 #define REDBOOT_IMAGE_SIZE 0x40000
115 #define BOARD_FLASH_START CS0_BASE_ADDR
117 #define SDRAM_BASE_ADDR CSD0_BASE_ADDR
118 #define SDRAM_SIZE 0x04000000
119 #define RAM_BANK0_BASE SDRAM_BASE_ADDR
121 #define LED_MAX_NUM 2
122 #define LED_IS_ON(n) (readw(PBC_BCTL1_CLR) & (1 << (n+6)))
123 #define TURN_LED_ON(n) writew((readw(PBC_BCTL1_CLR) | (1 << (n+6))), PBC_BCTL1_SET)
124 #define TURN_LED_OFF(n) writew((1<<(n+6)), PBC_BCTL1_CLR)
126 #define BOARD_DEBUG_LED(n) \
128 if (n >= 0 && n < LED_MAX_NUM) { \
136 #endif /* CYGONCE_FSL_BOARD_H */