packages/hal/arm/mxc91131/evb/v2_0/src/board_diag.c

   1 /*=============================================================================
   2 //
   3 //      board_diag.c
   4 //
   5 //      HAL diagnostic output code
   6 //
   7 //=============================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //===========================================================================*/
  41
  42 #include <pkgconf/hal.h>
  43
  44 #include <cyg/infra/cyg_type.h>         // base types
  45 #include <cyg/infra/cyg_trac.h>         // tracing macros
  46 #include <cyg/infra/cyg_ass.h>          // assertion macros
  47
  48 #include <cyg/hal/hal_arch.h>           // basic machine info
  49 #include <cyg/hal/hal_intr.h>           // interrupt macros
  50 #include <cyg/hal/hal_io.h>             // IO macros
  51 #include <cyg/hal/hal_diag.h>
  52 #include <cyg/hal/hal_if.h>             // Calling-if API
  53 #include <cyg/hal/drv_api.h>            // driver API
  54 #include <cyg/hal/hal_misc.h>           // Helper functions
  55 #include <cyg/hal/hal_soc.h>            // Hardware definitions
  56 #include <cyg/hal/fsl_board.h>          // Platform specifics
  57
  58 static void cyg_hal_plf_duart_init(void);
  59 extern void cyg_hal_plf_serial_init(void);
  60
  61 #define CHECK_BOARD_VERSION(ret)
  62 #define CHECK_BOARD_VERSION_RET_VOID
  63
  64 #if 0
  65 #define CHECK_BOARD_VERSION(ret)     \
  66     do {                             \
  67         if (((*(volatile unsigned short*)0xB4000000) >> 8) < 0x15) \
  68                     return ret;      \
  69     } while (0);
  70
  71 #define CHECK_BOARD_VERSION_RET_VOID \
  72     do {                             \
  73         if (((*(volatile unsigned short*)0xB4000000) >> 8) < 0x15) \
  74                     return;          \
  75     } while (0);
  76 #endif
  77
  78 void cyg_hal_plf_comms_init(void)
  79 {
  80     static int initialized = 0;
  81
  82     if (initialized)
  83         return;
  84
  85     initialized = 1;
  86
  87     /* Setup GPIO and enable transceiver for UARTs */
  88     cyg_hal_plf_duart_init();
  89     cyg_hal_plf_serial_init();
  90 }
  91
  92 //=============================================================================
  93 // ST16552 DUART driver
  94 //=============================================================================
  95
  96 //-----------------------------------------------------------------------------
  97 // There are two serial ports.
  98 #define CYG_DEV_SERIAL_BASE_A    (BOARD_CS_UART_BASE + 0x0000) // port A
  99 #define CYG_DEV_SERIAL_BASE_B    (BOARD_CS_UART_BASE + 0x0010) // port B
 100
 101 //-----------------------------------------------------------------------------
 102 // Based on 14.7456 MHz xtal
 103 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
 104 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 105 #define CYG_DEV_SERIAL_BAUD_LSB        0x60
 106 #endif
 107 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
 108 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 109 #define CYG_DEV_SERIAL_BAUD_LSB        0x30
 110 #endif
 111 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
 112 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 113 #define CYG_DEV_SERIAL_BAUD_LSB        0x18
 114 #endif
 115 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
 116 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 117 #define CYG_DEV_SERIAL_BAUD_LSB        0x10
 118 #endif
 119 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
 120 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 121 #define CYG_DEV_SERIAL_BAUD_LSB        0x08
 122 #endif
 123
 124 #ifndef CYG_DEV_SERIAL_BAUD_MSB
 125 #error Missing/incorrect serial baud rate defined - CDL error?
 126 #endif
 127
 128 //-----------------------------------------------------------------------------
 129 // Define the serial registers. The board is equipped with a 16552
 130 // serial chip.
 131
 132 #ifdef EXT_UART_x16
 133 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
 134 #define HAL_READ_UINT_UART HAL_READ_UINT16
 135 typedef cyg_uint16 uart_width;
 136 #else  //_x8
 137 typedef cyg_uint8 uart_width;
 138 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
 139 #define HAL_READ_UINT_UART HAL_READ_UINT8
 140 #endif
 141
 142 #define CYG_DEV_SERIAL_RHR   0x00 // receiver buffer register, read, dlab = 0
 143 #define CYG_DEV_SERIAL_THR   0x00 // transmitter holding register, write, dlab = 0
 144 #define CYG_DEV_SERIAL_DLL   0x00 // divisor latch (LS), read/write, dlab = 1
 145 #define CYG_DEV_SERIAL_IER   0x01 // interrupt enable register, read/write, dlab = 0
 146 #define CYG_DEV_SERIAL_DLM   0x01 // divisor latch (MS), read/write, dlab = 1
 147 #define CYG_DEV_SERIAL_IIR   0x02 // interrupt identification register, read, dlab = 0
 148 #define CYG_DEV_SERIAL_FCR   0x02 // fifo control register, write, dlab = 0
 149 #define CYG_DEV_SERIAL_AFR   0x02 // alternate function register, read/write, dlab = 1
 150 #define CYG_DEV_SERIAL_LCR   0x03 // line control register, read/write
 151 #define CYG_DEV_SERIAL_MCR   0x04
 152 #define CYG_DEV_SERIAL_MCR_A 0x04
 153 #define CYG_DEV_SERIAL_MCR_B 0x04
 154 #define CYG_DEV_SERIAL_LSR   0x05 // line status register, read
 155 #define CYG_DEV_SERIAL_MSR   0x06 // modem status register, read
 156 #define CYG_DEV_SERIAL_SCR   0x07 // scratch pad register
 157
 158 // The interrupt enable register bits.
 159 #define SIO_IER_ERDAI   0x01            // enable received data available irq
 160 #define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
 161 #define SIO_IER_ELSI    0x04            // enable receiver line status irq
 162 #define SIO_IER_EMSI    0x08            // enable modem status interrupt
 163
 164 // The interrupt identification register bits.
 165 #define SIO_IIR_IP      0x01            // 0 if interrupt pending
 166 #define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
 167 #define ISR_Tx          0x02
 168 #define ISR_Rx          0x04
 169
 170 // The line status register bits.
 171 #define SIO_LSR_DR      0x01            // data ready
 172 #define SIO_LSR_OE      0x02            // overrun error
 173 #define SIO_LSR_PE      0x04            // parity error
 174 #define SIO_LSR_FE      0x08            // framing error
 175 #define SIO_LSR_BI      0x10            // break interrupt
 176 #define SIO_LSR_THRE    0x20            // transmitter holding register empty
 177 #define SIO_LSR_TEMT    0x40            // transmitter register empty
 178 #define SIO_LSR_ERR     0x80            // any error condition
 179
 180 // The modem status register bits.
 181 #define SIO_MSR_DCTS    0x01            // delta clear to send
 182 #define SIO_MSR_DDSR    0x02            // delta data set ready
 183 #define SIO_MSR_TERI    0x04            // trailing edge ring indicator
 184 #define SIO_MSR_DDCD    0x08            // delta data carrier detect
 185 #define SIO_MSR_CTS     0x10            // clear to send
 186 #define SIO_MSR_DSR     0x20            // data set ready
 187 #define SIO_MSR_RI      0x40            // ring indicator
 188 #define SIO_MSR_DCD     0x80            // data carrier detect
 189
 190 // The line control register bits.
 191 #define SIO_LCR_WLS0   0x01             // word length select bit 0
 192 #define SIO_LCR_WLS1   0x02             // word length select bit 1
 193 #define SIO_LCR_STB    0x04             // number of stop bits
 194 #define SIO_LCR_PEN    0x08             // parity enable
 195 #define SIO_LCR_EPS    0x10             // even parity select
 196 #define SIO_LCR_SP     0x20             // stick parity
 197 #define SIO_LCR_SB     0x40             // set break
 198 #define SIO_LCR_DLAB   0x80             // divisor latch access bit
 199
 200 // The FIFO control register
 201 #define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
 202 #define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
 203 #define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
 204
 205 //-----------------------------------------------------------------------------
 206
 207 typedef struct {
 208     uart_width* base;
 209     cyg_int32 msec_timeout;
 210     int isr_vector;
 211 } channel_data_t;
 212
 213 static channel_data_t channels[] = {
 214 #if CYGHWR_HAL_ARM_DUART_UARTA != 0
 215     {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
 216 #endif
 217 #if CYGHWR_HAL_ARM_DUART_UARTB != 0
 218     {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
 219 #endif
 220 };
 221
 222 //-----------------------------------------------------------------------------
 223
 224 static void init_duart_channel(channel_data_t* __ch_data)
 225 {
 226     uart_width* base = __ch_data->base;
 227     uart_width lcr;
 228
 229     CHECK_BOARD_VERSION_RET_VOID;
 230
 231     // 8-1-no parity.
 232     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
 233                         SIO_LCR_WLS0 | SIO_LCR_WLS1);
 234
 235     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 236     lcr |= SIO_LCR_DLAB;
 237     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 238     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
 239     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
 240     lcr &= ~SIO_LCR_DLAB;
 241     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 242     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07);  // Enable & clear FIFO
 243 }
 244
 245 void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
 246 {
 247     uart_width* base = ((channel_data_t*)__ch_data)->base;
 248     uart_width lsr;
 249
 250     CHECK_BOARD_VERSION_RET_VOID;
 251
 252     CYGARC_HAL_SAVE_GP();
 253
 254     do {
 255         HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 256     } while ((lsr & SIO_LSR_THRE) == 0);
 257
 258     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
 259
 260     // Hang around until the character has been safely sent.
 261     do {
 262         HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 263     } while ((lsr & SIO_LSR_THRE) == 0);
 264
 265     CYGARC_HAL_RESTORE_GP();
 266 }
 267
 268 static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
 269 {
 270     uart_width* base = ((channel_data_t*)__ch_data)->base;
 271     uart_width lsr, ch16;
 272
 273     CHECK_BOARD_VERSION(false);
 274
 275     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 276     if ((lsr & SIO_LSR_DR) == 0)
 277         return false;
 278
 279     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
 280
 281     *ch = (cyg_uint8) (ch16 & 0x00FF);
 282
 283     return true;
 284 }
 285
 286 cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
 287 {
 288     cyg_uint8 ch;
 289
 290     CYGARC_HAL_SAVE_GP();
 291
 292     while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
 293
 294     CYGARC_HAL_RESTORE_GP();
 295     return ch;
 296 }
 297
 298 static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
 299                                     cyg_uint32 __len)
 300 {
 301     CHECK_BOARD_VERSION_RET_VOID;
 302
 303     CYGARC_HAL_SAVE_GP();
 304
 305     while (__len-- > 0)
 306         cyg_hal_plf_duart_putc(__ch_data, *__buf++);
 307
 308     CYGARC_HAL_RESTORE_GP();
 309 }
 310
 311 static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
 312                                    cyg_uint32 __len)
 313 {
 314     CHECK_BOARD_VERSION_RET_VOID;
 315
 316     CYGARC_HAL_SAVE_GP();
 317
 318     while (__len-- > 0)
 319         *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
 320
 321     CYGARC_HAL_RESTORE_GP();
 322 }
 323
 324 cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
 325 {
 326     int delay_count;
 327     channel_data_t* chan = (channel_data_t*)__ch_data;
 328     cyg_bool res;
 329
 330     CHECK_BOARD_VERSION(false);
 331
 332     CYGARC_HAL_SAVE_GP();
 333
 334     delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 335     for (;;) {
 336         res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
 337         if (res || 0 == delay_count--)
 338             break;
 339
 340         CYGACC_CALL_IF_DELAY_US(100);
 341     }
 342
 343     CYGARC_HAL_RESTORE_GP();
 344     return res;
 345 }
 346
 347 static int cyg_hal_plf_duart_control(void *__ch_data,
 348                                      __comm_control_cmd_t __func, ...)
 349 {
 350     static int irq_state = 0;
 351     channel_data_t* chan = (channel_data_t*)__ch_data;
 352     uart_width ier;
 353     int ret = 0;
 354
 355     CHECK_BOARD_VERSION(-1);
 356
 357     CYGARC_HAL_SAVE_GP();
 358
 359     switch (__func) {
 360     case __COMMCTL_IRQ_ENABLE:
 361         HAL_INTERRUPT_UNMASK(chan->isr_vector);
 362         HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
 363         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 364         ier |= SIO_IER_ERDAI;
 365         HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 366         irq_state = 1;
 367         break;
 368     case __COMMCTL_IRQ_DISABLE:
 369         ret = irq_state;
 370         irq_state = 0;
 371         HAL_INTERRUPT_MASK(chan->isr_vector);
 372         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 373         ier &= ~SIO_IER_ERDAI;
 374         HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 375         break;
 376     case __COMMCTL_DBG_ISR_VECTOR:
 377         ret = chan->isr_vector;
 378         break;
 379     case __COMMCTL_SET_TIMEOUT:
 380         {
 381             va_list ap;
 382
 383             va_start(ap, __func);
 384
 385             ret = chan->msec_timeout;
 386             chan->msec_timeout = va_arg(ap, cyg_uint32);
 387
 388             va_end(ap);
 389         }
 390         break;
 391     default:
 392         break;
 393     }
 394     CYGARC_HAL_RESTORE_GP();
 395     return ret;
 396 }
 397
 398 static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
 399                                  CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
 400 {
 401     channel_data_t* chan = (channel_data_t*)__ch_data;
 402     uart_width _iir;
 403     int res = 0;
 404     CYGARC_HAL_SAVE_GP();
 405
 406     HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
 407     _iir &= SIO_IIR_ID_MASK;
 408
 409     *__ctrlc = 0;
 410     if ( ISR_Rx == _iir ) {
 411         uart_width c, lsr;
 412         cyg_uint8 c8;
 413         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
 414         if (lsr & SIO_LSR_DR) {
 415
 416             HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
 417
 418             c8 = (cyg_uint8) (c & 0x00FF);
 419
 420             if (cyg_hal_is_break( &c8 , 1 ))
 421                 *__ctrlc = 1;
 422         }
 423
 424         // Acknowledge the interrupt
 425         HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
 426         res = CYG_ISR_HANDLED;
 427     }
 428
 429     CYGARC_HAL_RESTORE_GP();
 430     return res;
 431 }
 432
 433 static void cyg_hal_plf_duart_init(void)
 434 {
 435     hal_virtual_comm_table_t* comm;
 436     int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 437     int i;
 438
 439     CHECK_BOARD_VERSION_RET_VOID;
 440
 441     // Init channels
 442 #define NUMOF(x) (sizeof(x)/sizeof(x[0]))
 443     for (i = 0;  i < NUMOF(channels);  i++) {
 444         HAL_INTERRUPT_MASK(channels[i].isr_vector);
 445         init_duart_channel(&channels[i]);
 446         CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
 447         comm = CYGACC_CALL_IF_CONSOLE_PROCS();
 448         CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
 449         CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
 450         CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
 451         CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
 452         CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
 453         CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
 454         CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
 455         CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
 456     }
 457
 458     // Restore original console
 459     CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
 460 }
 461
 462 //=============================================================================
 463 // Compatibility with older stubs
 464 //=============================================================================
 465
 466 //=============================================================================
 467 // Compatibility with older stubs
 468 //=============================================================================
 469
 470 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 471
 472 #include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
 473
 474 #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
 475 #define __BASE   CMA101_DUARTA
 476 #define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_A
 477 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
 478 #define __BASE   CMA101_DUARTB
 479 #define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_B
 480 #endif
 481
 482 #ifdef __BASE
 483
 484 #ifdef CYGSEM_HAL_ROM_MONITOR
 485 #define CYG_HAL_STARTUP_ROM
 486 #define CYG_HAL_STARTUP_ROMRAM
 487 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 488 #endif
 489
 490 #if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 491 #define HAL_DIAG_USES_HARDWARE
 492 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
 493 #define HAL_DIAG_USES_HARDWARE
 494 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
 495 #define HAL_DIAG_USES_HARDWARE
 496 #endif
 497
 498 static channel_data_t channel = {
 499     (uart_width*) _BASE, 0, 0
 500 };
 501
 502 #ifdef HAL_DIAG_USES_HARDWARE
 503
 504 void hal_diag_init(void)
 505 {
 506     static int init = 0;
 507     char *msg = "\n\rARM eCos\n\r";
 508     uart_width lcr;
 509
 510     if (init++) return;
 511
 512     init_duart_channel(&channel);
 513
 514     while (*msg) hal_diag_write_char(*msg++);
 515 }
 516
 517 #ifdef DEBUG_DIAG
 518 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 519 #define DIAG_BUFSIZE 32
 520 #else
 521 #define DIAG_BUFSIZE 2048
 522 #endif
 523 static char diag_buffer[DIAG_BUFSIZE];
 524 static int diag_bp = 0;
 525 #endif
 526
 527 void hal_diag_write_char(char c)
 528 {
 529     uart_width lsr;
 530
 531     hal_diag_init();
 532
 533     cyg_hal_plf_duart_putc(&channel, c)
 534
 535 #ifdef DEBUG_DIAG
 536     diag_buffer[diag_bp++] = c;
 537     if (diag_bp == DIAG_BUFSIZE) {
 538         while (1) ;
 539         diag_bp = 0;
 540     }
 541 #endif
 542 }
 543
 544 void hal_diag_read_char(char *c)
 545 {
 546     *c = cyg_hal_plf_duart_getc(&channel);
 547 }
 548
 549 #else // HAL_DIAG relies on GDB
 550
 551 // Initialize diag port - assume GDB channel is already set up
 552 void hal_diag_init(void)
 553 {
 554     if (0) init_duart_channel(&channel); // avoid warning
 555 }
 556
 557 // Actually send character down the wire
 558 static void hal_diag_write_char_serial(char c)
 559 {
 560     cyg_hal_plf_duart_putc(&channel, c);
 561 }
 562
 563 static bool hal_diag_read_serial(char *c)
 564 {
 565     long timeout = 1000000000;  // A long time...
 566
 567     while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
 568         if (0 == --timeout) return false;
 569
 570     return true;
 571 }
 572
 573 void hal_diag_read_char(char *c)
 574 {
 575     while (!hal_diag_read_serial(c)) ;
 576 }
 577
 578 void hal_diag_write_char(char c)
 579 {
 580     static char line[100];
 581     static int pos = 0;
 582
 583     // No need to send CRs
 584     if (c == '\r') return;
 585
 586     line[pos++] = c;
 587
 588     if (c == '\n' || pos == sizeof(line)) {
 589         CYG_INTERRUPT_STATE old;
 590
 591         // Disable interrupts. This prevents GDB trying to interrupt us
 592         // while we are in the middle of sending a packet. The serial
 593         // receive interrupt will be seen when we re-enable interrupts
 594         // later.
 595
 596 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 597         CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
 598 #else
 599         HAL_DISABLE_INTERRUPTS(old);
 600 #endif
 601
 602         while (1) {
 603             static char hex[] = "0123456789ABCDEF";
 604             cyg_uint8 csum = 0;
 605             int i;
 606             char c1;
 607
 608             hal_diag_write_char_serial('$');
 609             hal_diag_write_char_serial('O');
 610             csum += 'O';
 611             for (i = 0; i < pos; i++) {
 612                 char ch = line[i];
 613                 char h = hex[(ch>>4)&0xF];
 614                 char l = hex[ch&0xF];
 615                 hal_diag_write_char_serial(h);
 616                 hal_diag_write_char_serial(l);
 617                 csum += h;
 618                 csum += l;
 619             }
 620             hal_diag_write_char_serial('#');
 621             hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
 622             hal_diag_write_char_serial(hex[csum&0xF]);
 623
 624             // Wait for the ACK character '+' from GDB here and handle
 625             // receiving a ^C instead.  This is the reason for this clause
 626             // being a loop.
 627             if (!hal_diag_read_serial(&c1))
 628                 continue;   // No response - try sending packet again
 629
 630             if ( c1 == '+' )
 631                 break;          // a good acknowledge
 632
 633 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 634             cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
 635             if ( c1 == 3 ) {
 636                 // Ctrl-C: breakpoint.
 637                 cyg_hal_gdb_interrupt (__builtin_return_address(0));
 638                 break;
 639             }
 640 #endif
 641             // otherwise, loop round again
 642         }
 643
 644         pos = 0;
 645
 646         // And re-enable interrupts
 647 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 648         CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
 649 #else
 650         HAL_RESTORE_INTERRUPTS(old);
 651 #endif
 652
 653     }
 654 }
 655 #endif
 656
 657 #endif // __BASE
 658
 659 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 660
 661 /*---------------------------------------------------------------------------*/