1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
48 #define REG8_VAL(a) (a)
49 #define REG16_VAL(a) (a)
50 #define REG32_VAL(a) (a)
52 #define REG8_PTR(a) (a)
53 #define REG16_PTR(a) (a)
54 #define REG32_PTR(a) (a)
56 #else /* __ASSEMBLER__ */
58 extern char HAL_PLATFORM_EXTRA[];
59 #define REG8_VAL(a) ((unsigned char)(a))
60 #define REG16_VAL(a) ((unsigned short)(a))
61 #define REG32_VAL(a) ((unsigned int)(a))
63 #define REG8_PTR(a) ((volatile unsigned char *)(a))
64 #define REG16_PTR(a) ((volatile unsigned short *)(a))
65 #define REG32_PTR(a) ((volatile unsigned int *)(a))
66 #define readb(a) (*(volatile unsigned char *)(a))
67 #define readw(a) (*(volatile unsigned short *)(a))
68 #define readl(a) (*(volatile unsigned int *)(a))
69 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
70 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
71 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
73 #endif /* __ASSEMBLER__ */
76 * Default Memory Layout Definitions
82 #define AIPS1_BASE_ADDR 0x43F00000
83 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
84 #define MAX_BASE_ADDR 0x43F04000
85 #define CLKCTL_BASE_ADDR 0x43F08000
86 #define ETB_SLOT4_BASE_ADDR 0x43F0C000
87 #define ETB_SLOT5_BASE_ADDR 0x43F10000
88 #define AAPE_BASE_ADDR 0x43F14000
89 #define I2C_BASE_ADDR 0x43F80000
90 #define MU_BASE_ADDR 0x43F88000
91 #define DSM_BASE_ADDR 0x43F98000
92 #define OWIRE_BASE_ADDR 0x43F9C000
93 #define KPP_BASE_ADDR 0x43FA8000
94 #define IOMUX_AP_BASE_ADDR 0x43FAC000
95 #define CTI_AP_BASE_ADDR 0x43FB8000
96 #define CTI_ARM_BASE_ADDR 0x43FBC000
97 #define MMC_SDHC1_BASE_ADDR 0x50004000
98 #define UART1_BASE_ADDR 0x5000C000
99 #define UART2_BASE_ADDR 0x50010000
100 #define SSI1_BASE_ADDR 0x50014000
101 #define SIM_BASE_ADDR 0x50018000
102 #define IIM_BASE_ADDR 0x5001C000
103 #define CTI_SDMA_BASE_ADDR 0x50020000
104 #define USBOTG_CTRL_BASE_ADDR 0x50024000
105 #define USBOTG_DATA_BASE_ADDR 0x50028000
106 #define CSPI1_BASE_ADDR 0x50030000
107 #define SPBA_CTRL_BASE_ADDR 0x5003C000
108 #define IOMUX_COM_BASE_ADDR 0x50040000
109 #define SRC_BASE_ADDR 0x50044000
110 #define CRM_AP_BASE_ADDR 0x50048000
111 #define PLL0_BASE_ADDR 0x5004C000
112 #define PLL1_BASE_ADDR 0x50050000
113 #define PLL2_BASE_ADDR 0x50054000
114 #define GPIO4_SH_BASE_ADDR 0x50058000
115 #define RTIC_BASE_ADDR 0x5005C000
116 #define RNGC_BASE_ADDR 0x50064000
121 #define AIPS2_BASE_ADDR 0x53F00000
122 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
123 #define GPT_AP_BASE_ADDR 0x53F90000
124 #define EPIT_AP_BASE_ADDR 0x53F94000
125 #define SCC_AP_BASE_ADDR 0x53FAC000
126 #define IPU_CTRL_BASE_ADDR 0x53FC0000
127 #define AUDMUX_BASE_ADDR 0x53FC4000
128 #define EDIO_BASE_ADDR 0x53FC8000
129 #define GPIO1_AP_BASE_ADDR 0x53FCC000
130 #define SDMA_BASE_ADDR 0x53FD4000
131 #define RTC_BASE_ADDR 0x53FD8000
132 #define WDOG1_AP_BASE_ADDR 0x53FDC000
133 #define LPMC_BASE_ADDR 0x53FF0000
134 #define WDOG_BASE_ADDR WDOG1_AP_BASE_ADDR
140 #define DSP_EPIC_BASE_ADDR 0xFFF00400
143 * DSP Peripheral registers
145 #define DSP_CRM_BP 0xFFFC8000
150 #define ROMPATCH_BASE_ADDR 0x60000000
151 #define AVIC_BASE_ADDR 0x68000000
154 * NAND, SDRAM, WEIM, M3IF, EMI controllers
156 #define EXT_MEM_CTRL_BASE 0xB8000000
157 #define NFC_BASE EXT_MEM_CTRL_BASE
158 #define ESDCTL_BASE 0xB8001000
159 #define WEIM_BASE_ADDR 0xB8002000
160 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR
161 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
162 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
163 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
164 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
165 #define M3IF_BASE 0xB8003000
166 #define EMI_CTL_BASE 0xB8004000
169 * Memory regions and CS
171 #define IPU_MEM_BASE_ADDR 0x70000000
172 #define CSD0_BASE_ADDR 0x80000000
173 #define CSD1_BASE_ADDR 0x90000000
174 #define CS0_BASE_ADDR 0xA0000000
175 #define CS1_BASE_ADDR 0xA8000000
176 #define CS2_BASE_ADDR 0xB0000000
177 #define CS3_BASE_ADDR 0xB2000000
178 #define CS4_BASE_ADDR 0xB4000000
179 #define CS5_BASE_ADDR 0xB6000000
180 #define MAX_S0_BASE_ADDR 0xC0000000
182 #define INTERNAL_ROM_VA 0xF0000000
185 * IRQ Controller Register Definitions.
187 #define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04))
188 #define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18))
189 #define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C))
192 #define CRM_AP_ASCSR 0x00
193 #define CRM_AP_ACSR 0x04
194 #define CRM_AP_ACDR 0x08
195 #define CRM_AP_ACDER 0x0C
196 #define CRM_AP_APR 0x10
197 #define CRM_AP_ACGCR 0x14
198 #define CRM_AP_ARCGR 0x18
199 #define CRM_AP_L1CGR0 0x1C
200 #define CRM_AP_L1CGR1 0x20
201 #define CRM_AP_L1CGR2 0x24
202 #define CRM_AP_L1CGR3 0x28
203 #define CRM_AP_L2CGR0 0x2C
204 #define CRM_AP_L2CGR1 0x30
205 #define CRM_AP_L2CGR2 0x34
206 #define CRM_AP_L2CGR3 0x38
207 #define CRM_AP_L2CGR4 0x3C
208 #define CRM_AP_L2CGR5 0x40
209 #define CRM_AP_L2CGR6 0x44
210 #define CRM_AP_L2CGR7 0x48
211 #define CRM_AP_L2CGR8 0x4C
212 #define CRM_AP_AMORA 0x50
213 #define CRM_AP_AMORB 0x54
214 #define CRM_AP_AMORC 0x58
215 #define CRM_AP_APOR 0x5C
216 #define CRM_AP_AMCR 0x60
217 #define CRM_AP_ADFMR 0x64
218 #define CRM_AP_ACR 0x68
219 #define CRM_AP_APCR 0x6C
220 #define CRM_AP_AGPR 0x70
223 #define SRC_SBMR 0x00
224 #define SRC_SRSR 0x04
225 #define SRC_SCRCR 0x08
226 #define SRC_SSCR 0x0C
227 #define SRC_SGPR 0x14
233 /* ESDRAM parameters */
234 #define SDRAM_CSD0 0x80000000
235 #define SDRAM_CSD1 0x90000000
238 #define ESDCTL_ESDCTL0 0x00
239 #define ESDCTL_ESDCFG0 0x04
240 #define ESDCTL_ESDCTL1 0x08
241 #define ESDCTL_ESDCFG1 0x0C
242 #define ESDCTL_ESDMISC 0x10
245 #define PLL_DP_CTL 0x00
246 #define PLL_DP_CONFIG 0x04
247 #define PLL_DP_OP 0x08
248 #define PLL_DP_MFD 0x0C
249 #define PLL_DP_MFN 0x10
250 #define PLL_DP_MFNMINUS 0x14
251 #define PLL_DP_MFNPLUS 0x18
252 #define PLL_DP_HFS_OP 0x1C
253 #define PLL_DP_HFS_MFD 0x20
254 #define PLL_DP_HFS_MFN 0x24
255 #define PLL_DP_TOGC 0x28
256 #define PLL_DP_DESTAT 0x2C
271 #define CHIP_REV_1_0 0x0 /* PASS 1.0 */
272 #define CHIP_REV_2_0 0x1 /* PASS 2.0 */
273 #define CHIP_REV_2_1 0x2 /* PASS 2.1 */
274 #define CHIP_REV_2_2 0x3 /* PASS 2.2 */
275 #define CHIP_REV_2_3 0x4 /* PASS 2.3 */
276 #define CHIP_LATEST CHIP_REV_1_0
278 #define IIM_STAT_OFF 0x00
279 #define IIM_STAT_BUSY (1 << 7)
280 #define IIM_STAT_PRGD (1 << 1)
281 #define IIM_STAT_SNSD (1 << 0)
282 #define IIM_STATM_OFF 0x04
283 #define IIM_ERR_OFF 0x08
284 #define IIM_ERR_PRGE (1 << 7)
285 #define IIM_ERR_WPE (1 << 6)
286 #define IIM_ERR_OPE (1 << 5)
287 #define IIM_ERR_RPE (1 << 4)
288 #define IIM_ERR_WLRE (1 << 3)
289 #define IIM_ERR_SNSE (1 << 2)
290 #define IIM_ERR_PARITYE (1 << 1)
291 #define IIM_EMASK_OFF 0x0C
292 #define IIM_FCTL_OFF 0x10
293 #define IIM_UA_OFF 0x14
294 #define IIM_LA_OFF 0x18
295 #define IIM_SDAT_OFF 0x1C
296 #define IIM_PREV_OFF 0x20
297 #define IIM_SREV_OFF 0x24
298 #define IIM_PREG_P_OFF 0x28
299 #define IIM_SCS0_OFF 0x2C
300 #define IIM_SCS1_P_OFF 0x30
301 #define IIM_SCS2_OFF 0x34
302 #define IIM_SCS3_P_OFF 0x38
303 #define IIM_HAB1 0x814
304 #define IIM_FB1UC28 0xC78
305 #define IIM_FB1UC29 0xC79
306 #define IIM_FB1UC30 0xC7A
307 #define IIM_FB1UC31 0xC7B
308 #define IIM_FB1UC32 0xC7C
310 /* DSP EPIC - only available from the DSP, or through MU */
311 #define EPIC_IPR0 0x120
313 /* DSP CRM_BP - only available from the DSP, or through MU */
314 #define CRM_BP_BSCSR 0x00
315 #define CRM_BP_BCDR 0x04
316 #define CRM_BP_BCGCR 0x08
317 #define CRM_BP_BMLPMRA 0x0C
318 #define CRM_BP_BMLPMRB 0x10
319 #define CRM_BP_BMLPMRC 0x14
320 #define CRM_BP_BMLPMRD 0x18
321 #define CRM_BP_BMLPMRE 0x1C
322 #define CRM_BP_BCSR 0x20
323 #define CRM_BP_BDCR 0x24
324 #define CRM_BP_BCR 0x28
325 #define CRM_BP_BMCR 0x2C
326 #define CRM_BP_BPCR 0x30
328 #define FREQ_CKIH_26M 26000000
330 #define EPIT_BASE_ADDR EPIT_AP_BASE_ADDR
334 #define EPITCMPR 0x0C
337 #define MXC_PERCLK1 26000000 /* Peripheral Clock 1 */
338 #define DelayTimerPresVal 3
340 #define HAL_DELAY_US(n) hal_delay_us(n)
342 #define NAND_REG_BASE (NFC_BASE + 0xE00)
343 #define NFC_BUFSIZE_REG_OFF (0 + 0x00)
344 #define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
345 #define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
346 #define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
347 #define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
348 #define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
349 #define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
350 #define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
351 #define NF_WR_PROT_REG_OFF (0 + 0x12)
352 #define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x14)
353 #define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x16)
354 #define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
355 #define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
356 #define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
357 #define RAM_BUFFER_ADDRESS_RBA_3 0x3
358 #define NFC_BUFSIZE_1KB 0x0
359 #define NFC_BUFSIZE_2KB 0x1
360 #define NFC_CONFIGURATION_UNLOCKED 0x2
361 #define ECC_STATUS_RESULT_NO_ERR 0x0
362 #define ECC_STATUS_RESULT_1BIT_ERR 0x1
363 #define ECC_STATUS_RESULT_2BIT_ERR 0x2
364 #define NF_WR_PROT_UNLOCK 0x4
365 #define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
366 #define NAND_FLASH_CONFIG1_RST (1 << 6)
367 #define NAND_FLASH_CONFIG1_BIG (1 << 5)
368 #define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
369 #define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
370 #define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
371 #define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
372 #define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
373 #define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
374 #define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
375 #define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
376 #define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
377 #define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
378 #define FDO_PAGE_SPARE_VAL 0x8
380 #define MXC_NAND_BASE_DUMMY 0xE0000000
381 #define NOR_FLASH_BOOT 0
382 #define NAND_FLASH_BOOT 0x10000000
383 #define SDRAM_NON_FLASH_BOOT 0x20000000
384 #define MXCBOOT_FLAG_REG (AVIC_BASE_ADDR + 0x20)
385 #define MXCFIS_NOTHING 0x00000000
386 #define MXCFIS_NAND 0x10000000
387 #define MXCFIS_NOR 0x20000000
388 #define MXCFIS_FLAG_REG (AVIC_BASE_ADDR + 0x24)
390 #define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
391 #define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
392 #define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
394 #ifndef MXCFLASH_SELECT_NAND
395 #define IS_FIS_FROM_NAND() 0
397 #define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
400 #ifndef MXCFLASH_SELECT_NOR
401 #define IS_FIS_FROM_NOR() 0
403 #define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
406 #define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
407 #define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
410 * This macro is used to get certain bit field from a number
412 #define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
415 * This macro is used to set certain bit field inside a number
417 #define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
419 #define UART_WIDTH_32 /* internal UART is 32bit access only */
422 #if !defined(__ASSEMBLER__)
423 void cyg_hal_plf_serial_init(void);
424 void cyg_hal_plf_serial_stop(void);
425 void hal_delay_us(unsigned int usecs);
426 #define HAL_DELAY_US(n) hal_delay_us(n)
449 unsigned int pll_clock(enum plls pll);
451 unsigned int get_main_clock(enum main_clocks clk);
453 unsigned int get_peri_clock(enum peri_clocks clk);
455 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
457 #endif //#if !defined(__ASSEMBLER__)
459 #define HAL_MMU_OFF() \
463 "mrc p15, 0, r15, c7, c14, 3;" /*test clean and inval*/ \
466 "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
467 "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
468 "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
469 "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
470 "bic r0, r0, #0x1000;" /* disable ICache */ \
471 "mcr p15, 0, r0, c1, c0, 0;" /* */ \
472 "nop;" /* flush i+d-TLBs */ \
473 "nop;" /* flush i+d-TLBs */ \
474 "nop;" /* flush i+d-TLBs */ \
477 : "r0","memory" /* clobber list */); \
480 #endif // __HAL_SOC_H__