1 //==========================================================================
5 // HAL misc board support code
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
42 #include <pkgconf/hal.h>
43 #include <pkgconf/system.h>
44 #include CYGBLD_HAL_PLATFORM_H
46 #include <cyg/infra/cyg_type.h> // base types
47 #include <cyg/infra/cyg_trac.h> // tracing macros
48 #include <cyg/infra/cyg_ass.h> // assertion macros
50 #include <cyg/hal/hal_io.h> // IO macros
51 #include <cyg/hal/hal_arch.h> // Register state info
52 #include <cyg/hal/hal_diag.h>
53 #include <cyg/hal/hal_intr.h> // Interrupt names
54 #include <cyg/hal/hal_cache.h>
55 #include <cyg/hal/hal_soc.h> // Hardware definitions
56 #include <cyg/hal/fsl_board.h> // Platform specifics
58 #include <cyg/infra/diag.h> // diag_printf
60 // All the MM table layout is here:
61 #include <cyg/hal/hal_mm.h>
63 externC void* memset(void *, int, size_t);
65 void hal_mmu_init(void)
67 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
71 * Set the TTB register
73 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
76 * Set the Domain Access Control Register
78 i = ARM_ACCESS_DACR_DEFAULT;
79 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
82 * First clear all TT entries - ie Set them to Faulting
84 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
86 /* Actual Virtual Size Attributes Function */
87 /* Base Base MB cached? buffered? access permissions */
88 /* xxx00000 xxx00000 */
89 X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
90 X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
91 X_ARM_MMU_SECTION(0x43F, 0x43F, 0x3C1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
92 X_ARM_MMU_SECTION(0x800, 0x000, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
93 X_ARM_MMU_SECTION(0x800, 0x800, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
94 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
95 X_ARM_MMU_SECTION(0xB40, 0xB40, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
96 X_ARM_MMU_SECTION(0xB50, 0xB50, 0x8, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PSRAM */
97 X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EIM control*/
101 // Platform specific initialization
104 void plf_hardware_init(void)
106 volatile unsigned int *pMuxCtl, *pMuxComCtl;
107 volatile unsigned short *pPBCCtl;
110 // Setup IOMUX for UARTs
111 pMuxCtl = (volatile unsigned int *)(IOMUX_AP_BASE_ADDR);
112 pMuxComCtl = (volatile unsigned int *)(IOMUX_COM_BASE_ADDR);
114 pMuxCtl[1] = (pMuxCtl[1] & (0x00FFFFFF)) | 0x10000000;
115 pMuxCtl[2] = (pMuxCtl[2] & (0xFF000000)) | 0x00101010;
116 // For UART2 - complicated since the pins muxed with USB pins
117 // USB_RXD -> U2_RTS_B
118 // USB_SE0_VM -> U2_TXD
119 // USB_DAT_VP -> U2_RXD
120 pMuxComCtl[1] = (pMuxComCtl[1] & (0x000000FF)) | 0x20202000;
121 pMuxCtl[12] = 0x10101010;
124 pPBCCtl = (volatile unsigned short *)(PBC_BASE + 0x4);
126 //Enable UART transceivers also reset the Ethernet/external UART
128 for (i = 0; i < 100000; i++) {
131 writew(0x3, PBC_BCTL1_CLR);
132 for (i = 0; i < 1000000; i++) {
135 readb(BOARD_CS_UART_BASE + 0x8);
136 readb(BOARD_CS_UART_BASE + 0x7);
137 readb(BOARD_CS_UART_BASE + 0x8);
138 readb(BOARD_CS_UART_BASE + 0x7);
141 #include CYGHWR_MEMORY_LAYOUT_H
143 typedef void code_fun(void);
145 void board_program_new_stack(void *func)
147 register CYG_ADDRESS stack_ptr asm("sp");
148 register CYG_ADDRESS old_stack asm("r4");
149 register code_fun *new_func asm("r0");
150 old_stack = stack_ptr;
151 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
152 new_func = (code_fun*)func;
154 stack_ptr = old_stack;