1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
48 #define REG8_VAL(a) (a)
49 #define REG16_VAL(a) (a)
50 #define REG32_VAL(a) (a)
52 #define REG8_PTR(a) (a)
53 #define REG16_PTR(a) (a)
54 #define REG32_PTR(a) (a)
56 #else /* __ASSEMBLER__ */
58 extern char HAL_PLATFORM_EXTRA[];
59 #define REG8_VAL(a) ((unsigned char)(a))
60 #define REG16_VAL(a) ((unsigned short)(a))
61 #define REG32_VAL(a) ((unsigned int)(a))
63 #define REG8_PTR(a) ((volatile unsigned char *)(a))
64 #define REG16_PTR(a) ((volatile unsigned short *)(a))
65 #define REG32_PTR(a) ((volatile unsigned int *)(a))
66 #define readb(a) (*(volatile unsigned char *)(a))
67 #define readw(a) (*(volatile unsigned short *)(a))
68 #define readl(a) (*(volatile unsigned int *)(a))
69 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
70 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
71 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
73 #endif /* __ASSEMBLER__ */
76 * Default Memory Layout Definitions
79 #define L2CC_BASE_ADDR 0x30000000
84 #define AIPS1_BASE_ADDR 0x43F00000
85 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
86 #define MAX_BASE_ADDR 0x43F04000
87 #define EVTMON_BASE_ADDR 0x43F08000
88 #define CLKCTL_BASE_ADDR 0x43F0C000
89 #define ETB_SLOT4_BASE_ADDR 0x43F10000
90 #define ETB_SLOT5_BASE_ADDR 0x43F14000
91 #define ECT_CTIO_BASE_ADDR 0x43F18000
92 #define I2C_BASE_ADDR 0x43F80000
93 #define MU_BASE_ADDR 0x43F88000
94 #define UART1_BASE_ADDR 0x43F90000
95 #define UART2_BASE_ADDR 0x43F94000
96 #define DSM_BASE_ADDR 0x43F98000
97 #define OWIRE_BASE_ADDR 0x43F9C000
98 #define SSI1_BASE_ADDR 0x43FA0000
99 #define KPP_BASE_ADDR 0x43FA8000
100 #define IOMUX_AP_BASE_ADDR 0x43FAC000
101 #define CTI_AP_BASE_ADDR 0x43FB8000
104 * SPBA global module enabled #0
106 #define SPBA_MOD0_BASE_ADDR 0x50000000
107 #define MMC_SDHC1_BASE_ADDR 0x50004000
108 #define MMC_SDHC2_BASE_ADDR 0x50008000
109 #define UART3_BASE_ADDR 0x5000C000
110 #define CSPI2_BASE_ADDR 0x50010000
111 #define SSI2_BASE_ADDR 0x50014000
112 #define SIM_BASE_ADDR 0x50018000
113 #define IIM_BASE_ADDR 0x5001C000
114 #define CTI_SDMA_BASE_ADDR 0x50020000
115 #define USBOTG_CTRL_BASE_ADDR 0x50024000
116 #define USBOTG_DATA_BASE_ADDR 0x50028000
117 #define CSPI1_BASE_ADDR 0x50030000
118 #define SPBA_CTRL_BASE_ADDR 0x5003C000
119 #define IOMUX_COM_BASE_ADDR 0x50040000
120 #define CRM_COM_BASE_ADDR 0x50044000
121 #define CRM_AP_BASE_ADDR 0x50048000
122 #define PLL0_BASE_ADDR 0x5004C000
123 #define PLL1_BASE_ADDR 0x50050000
124 #define PLL2_BASE_ADDR 0x50054000
125 #define GPIO4_SH_BASE_ADDR 0x50058000
126 #define HAC_BASE_ADDR 0x5005C000
127 #define PLL3_BASE_ADDR 0x50060000
130 * SPBA global module enabled #1
132 #define SPBA_MOD1_BASE_ADDR 0x52000000
133 #define MQSPI_BASE_ADDR 0x52034000
134 #define EL1T_BASE_ADDR 0x52038000
139 #define AIPS2_BASE_ADDR 0x53F00000
140 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
141 #define GEMK_BASE_ADDR 0x53F8C000
142 #define GPT_AP_BASE_ADDR 0x53F90000
143 #define EPIT_AP_BASE_ADDR 0x53F94000
144 #define SCC_AP_BASE_ADDR 0x53FAC000
145 #define RNGA_BASE_ADDR 0x53FB0000
146 #define IPU_CTRL_BASE_ADDR 0x53FC0000
147 #define AUDMUX_BASE_ADDR 0x53FC4000
148 #define EDIO_BASE_ADDR 0x53FC8000
149 #define GPIO1_AP_BASE_ADDR 0x53FCC000
150 #define GPIO2_AP_BASE_ADDR 0x53FD0000
151 #define SDMA_BASE_ADDR 0x53FD4000
152 #define RTC_BASE_ADDR 0x53FD8000
153 #define WDOG1_AP_BASE_ADDR 0x53FDC000
154 #define WDOG_BASE_ADDR WDOG1_AP_BASE_ADDR
155 #define PWM_BASE_ADDR 0x53FE0000
156 #define GPIO3_AP_BASE_ADDR 0x53FE4000
157 #define WDOG2_AP_BASE_ADDR 0x53FE8000
158 #define RTIC_BASE_ADDR 0x53FEC000
159 #define LPMC_BASE_ADDR 0x53FF0000
164 #define DSP_EPIC_BASE_ADDR 0xFFF00400
167 * DSP Peripheral registers
169 #define DSP_CRM_BP 0xFFFC8000
174 #define ROMPATCH_BASE_ADDR 0x60000000
175 #define AVIC_BASE_ADDR 0x68000000
178 * NAND, SDRAM, WEIM, M3IF, EMI controllers
180 #define EXT_MEM_CTRL_BASE 0xB8000000
181 #define NFC_BASE EXT_MEM_CTRL_BASE
182 #define ESDCTL_BASE 0xB8001000
183 #define WEIM_BASE_ADDR 0xB8002000
184 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR
185 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
186 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
187 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
188 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
189 #define M3IF_BASE 0xB8003000
190 #define EMI_CTL_BASE 0xB8004000
193 * Memory regions and CS
195 #define IPU_MEM_BASE_ADDR 0x70000000
196 #define CSD0_BASE_ADDR 0x80000000
197 #define CSD1_BASE_ADDR 0x90000000
198 #define CS0_BASE_ADDR 0xA0000000
199 #define CS1_BASE_ADDR 0xA8000000
200 #define CS2_BASE_ADDR 0xB0000000
201 #define CS3_BASE_ADDR 0xB2000000
202 #define CS4_BASE_ADDR 0xB4000000
203 #define CS5_BASE_ADDR 0xB6000000
204 #define MAX_S0_BASE_ADDR 0xC0000000
206 #define INTERNAL_ROM_VA 0xF0000000
209 * IRQ Controller Register Definitions.
211 #define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04))
212 #define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18))
213 #define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C))
216 #define L2CC_BASE_ADDR 0x30000000
217 #define L2_CACHE_LINE_SIZE 32
218 #define L2_CACHE_CTL_REG 0x100
219 #define L2_CACHE_AUX_CTL_REG 0x104
220 #define L2_CACHE_SYNC_REG 0x730
221 #define L2_CACHE_INV_LINE_REG 0x770
222 #define L2_CACHE_INV_WAY_REG 0x77C
223 #define L2_CACHE_CLEAN_LINE_REG 0x7B0
224 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
227 #define CRM_COM_CBMR 0x00
228 #define CRM_COM_CRSRBP 0x04
229 #define CRM_COM_CCRCR 0x08
230 #define CRM_COM_CSCR 0x0C
231 #define CRM_COM_CCCR 0x10
232 #define CRM_COM_CRSRAP 0x14
235 #define CRM_AP_ASCSR 0x00
236 #define CRM_AP_ACDR 0x04
237 #define CRM_AP_ACDER1 0x08
238 #define CRM_AP_ACDER2 0x0C
239 #define CRM_AP_ACGCR 0x10
240 #define CRM_AP_ACCGCR 0x14
241 #define CRM_AP_AMLPMRA 0x18
242 #define CRM_AP_AMLPMRB 0x1C
243 #define CRM_AP_AMLPMRC 0x20
244 #define CRM_AP_AMLPMRD 0x24
245 #define CRM_AP_AMLPMRE1 0x28
246 #define CRM_AP_AMLPMRE2 0x2C
247 #define CRM_AP_AMLPMRF 0x30
248 #define CRM_AP_AMLPMRG 0x34
249 #define CRM_AP_APGCR 0x38
250 #define CRM_AP_ACSR 0x3C
251 #define CRM_AP_ADCR 0x40
252 #define CRM_AP_ACR 0x44
253 #define CRM_AP_AMCR 0x48
254 #define CRM_AP_APCR 0x4C
255 #define CRM_AP_AMORA 0x50
256 #define CRM_AP_AMORB 0x54
257 #define CRM_AP_AGPR 0x58
258 #define CRM_AP_APRA 0x5C
259 #define CRM_AP_APRB 0x60
260 #define CRM_AP_APOR 0x64
266 /* ESDRAM parameters */
267 #define SDRAM_CSD0 0x80000000
268 #define SDRAM_CSD1 0x90000000
271 #define ESDCTL_ESDCTL0 0x00
272 #define ESDCTL_ESDCFG0 0x04
273 #define ESDCTL_ESDCTL1 0x08
274 #define ESDCTL_ESDCFG1 0x0C
275 #define ESDCTL_ESDMISC 0x10
278 #define PLL_DP_CTL 0x00
279 #define PLL_DP_CONFIG 0x04
280 #define PLL_DP_OP 0x08
281 #define PLL_DP_MFD 0x0C
282 #define PLL_DP_MFN 0x10
283 #define PLL_DP_MFNMINUS 0x14
284 #define PLL_DP_MFNPLUS 0x18
285 #define PLL_DP_HFS_OP 0x1C
286 #define PLL_DP_HFS_MFD 0x20
287 #define PLL_DP_HFS_MFN 0x24
288 #define PLL_DP_TOGC 0x28
289 #define PLL_DP_DESTAT 0x2C
304 #define CHIP_REV_1_0 0x0 /* PASS 1.0 */
305 #define CHIP_REV_2_0 0x1 /* PASS 2.0 */
306 #define CHIP_REV_2_1 0x2 /* PASS 2.1 */
307 #define CHIP_REV_2_2 0x3 /* PASS 2.2 */
308 #define CHIP_REV_2_3 0x4 /* PASS 2.3 */
309 #define CHIP_LATEST CHIP_REV_2_1
311 #define IIM_STAT_OFF 0x00
312 #define IIM_STAT_BUSY (1 << 7)
313 #define IIM_STAT_PRGD (1 << 1)
314 #define IIM_STAT_SNSD (1 << 0)
315 #define IIM_STATM_OFF 0x04
316 #define IIM_ERR_OFF 0x08
317 #define IIM_ERR_PRGE (1 << 7)
318 #define IIM_ERR_WPE (1 << 6)
319 #define IIM_ERR_OPE (1 << 5)
320 #define IIM_ERR_RPE (1 << 4)
321 #define IIM_ERR_WLRE (1 << 3)
322 #define IIM_ERR_SNSE (1 << 2)
323 #define IIM_ERR_PARITYE (1 << 1)
324 #define IIM_EMASK_OFF 0x0C
325 #define IIM_FCTL_OFF 0x10
326 #define IIM_UA_OFF 0x14
327 #define IIM_LA_OFF 0x18
328 #define IIM_SDAT_OFF 0x1C
329 #define IIM_PREV_OFF 0x20
330 #define IIM_SREV_OFF 0x24
331 #define IIM_PREG_P_OFF 0x28
332 #define IIM_SCS0_OFF 0x2C
333 #define IIM_SCS1_P_OFF 0x30
334 #define IIM_SCS2_OFF 0x34
335 #define IIM_SCS3_P_OFF 0x38
336 #define IIM_HAB1 0x814
337 #define IIM_FB1UC28 0xC78
338 #define IIM_FB1UC29 0xC79
339 #define IIM_FB1UC30 0xC7A
340 #define IIM_FB1UC31 0xC7B
341 #define IIM_FB1UC32 0xC7C
343 /* DSP EPIC - only available from the DSP, or through MU */
344 #define EPIC_IPR0 0x120
346 /* DSP CRM_BP - only available from the DSP, or through MU */
347 #define CRM_BP_BSCSR 0x00
348 #define CRM_BP_BCDR 0x04
349 #define CRM_BP_BCGCR 0x08
350 #define CRM_BP_BMLPMRA 0x0C
351 #define CRM_BP_BMLPMRB 0x10
352 #define CRM_BP_BMLPMRC 0x14
353 #define CRM_BP_BMLPMRD 0x18
354 #define CRM_BP_BMLPMRE 0x1C
355 #define CRM_BP_BCSR 0x20
356 #define CRM_BP_BDCR 0x24
357 #define CRM_BP_BCR 0x28
358 #define CRM_BP_BMCR 0x2C
359 #define CRM_BP_BPCR 0x30
361 #define FREQ_CKIH_26M 26000000
363 #define EPIT_BASE_ADDR EPIT_AP_BASE_ADDR
367 #define EPITCMPR 0x0C
370 #define MXC_PERCLK1 26000000 /* Peripheral Clock 1 */
371 #define DelayTimerPresVal 3
373 #define HAL_DELAY_US(n) hal_delay_us(n)
375 #define NAND_REG_BASE (NFC_BASE + 0xE00)
376 #define NFC_BUFSIZE_REG_OFF (0 + 0x00)
377 #define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
378 #define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
379 #define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
380 #define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
381 #define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
382 #define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
383 #define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
384 #define NF_WR_PROT_REG_OFF (0 + 0x12)
385 #define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x14)
386 #define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x16)
387 #define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
388 #define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
389 #define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
390 #define RAM_BUFFER_ADDRESS_RBA_3 0x3
391 #define NFC_BUFSIZE_1KB 0x0
392 #define NFC_BUFSIZE_2KB 0x1
393 #define NFC_CONFIGURATION_UNLOCKED 0x2
394 #define ECC_STATUS_RESULT_NO_ERR 0x0
395 #define ECC_STATUS_RESULT_1BIT_ERR 0x1
396 #define ECC_STATUS_RESULT_2BIT_ERR 0x2
397 #define NF_WR_PROT_UNLOCK 0x4
398 #define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
399 #define NAND_FLASH_CONFIG1_RST (1 << 6)
400 #define NAND_FLASH_CONFIG1_BIG (1 << 5)
401 #define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
402 #define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
403 #define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
404 #define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
405 #define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
406 #define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
407 #define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
408 #define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
409 #define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
410 #define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
411 #define FDO_PAGE_SPARE_VAL 0x8
413 #define MXC_NAND_BASE_DUMMY 0xE0000000
414 #define NOR_FLASH_BOOT 0
415 #define NAND_FLASH_BOOT 0x10000000
416 #define SDRAM_NON_FLASH_BOOT 0x20000000
417 #define MXCBOOT_FLAG_REG (AVIC_BASE_ADDR + 0x100)
418 #define MXCFIS_NOTHING 0x00000000
419 #define MXCFIS_NAND 0x10000000
420 #define MXCFIS_NOR 0x20000000
421 #define MXCFIS_FLAG_REG (AVIC_BASE_ADDR + 0x104)
423 #define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
424 #define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
425 #define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
427 #ifndef MXCFLASH_SELECT_NAND
428 #define IS_FIS_FROM_NAND() 0
430 #define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
433 #ifndef MXCFLASH_SELECT_NOR
434 #define IS_FIS_FROM_NOR() 0
436 #define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
439 #define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
440 #define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
443 * This macro is used to get certain bit field from a number
445 #define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
448 * This macro is used to set certain bit field inside a number
450 #define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
452 #define UART_WIDTH_32 /* internal UART is 32bit access only */
456 #if !defined(__ASSEMBLER__)
457 void cyg_hal_plf_serial_init(void);
458 void cyg_hal_plf_serial_stop(void);
459 void hal_delay_us(unsigned int usecs);
460 #define HAL_DELAY_US(n) hal_delay_us(n)
485 unsigned int pll_clock(enum plls pll);
487 unsigned int get_main_clock(enum main_clocks clk);
489 unsigned int get_peri_clock(enum peri_clocks clk);
491 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
493 #endif //#if !defined(__ASSEMBLER__)
495 #define HAL_MMU_OFF() \
498 "mcr p15, 0, r0, c7, c14, 0;" \
499 "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
500 "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
501 "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
502 "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
503 "bic r0, r0, #0x1000;" /* disable ICache */ \
504 "mcr p15, 0, r0, c1, c0, 0;" /* */ \
505 "nop;" /* flush i+d-TLBs */ \
506 "nop;" /* flush i+d-TLBs */ \
507 "nop;" /* flush i+d-TLBs */ \
510 : "r0","memory" /* clobber list */); \
513 #endif // __HAL_SOC_H__