1 #ifndef CYGONCE_HAL_VAR_INTS_H
2 #define CYGONCE_HAL_VAR_INTS_H
3 //==========================================================================
7 // HAL Interrupt and clock support
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
44 #include <cyg/hal/hal_soc.h> // registers
45 #include <cyg/hal/hal_cache.h>
47 // NOTE: These interrupt definitions are not used by redboot. The
48 // defines are provided to fulfill build requirements.
49 #define CYGNUM_HAL_INTERRUPT_GPIO0 0
50 #define CYGNUM_HAL_INTERRUPT_GPIO1 1
51 #define CYGNUM_HAL_INTERRUPT_GPIO2 2
52 #define CYGNUM_HAL_INTERRUPT_GPIO3 3
53 #define CYGNUM_HAL_INTERRUPT_GPIO4 4
54 #define CYGNUM_HAL_INTERRUPT_GPIO5 5
55 #define CYGNUM_HAL_INTERRUPT_GPIO6 6
56 #define CYGNUM_HAL_INTERRUPT_GPIO7 7
57 #define CYGNUM_HAL_INTERRUPT_GPIO8 8
58 #define CYGNUM_HAL_INTERRUPT_GPIO9 9
59 #define CYGNUM_HAL_INTERRUPT_GPIO10 10
60 #define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly!
61 #define CYGNUM_HAL_INTERRUPT_LCD 12
62 #define CYGNUM_HAL_INTERRUPT_UDC 13
63 #define CYGNUM_HAL_INTERRUPT_UART2 15
64 #define CYGNUM_HAL_INTERRUPT_UART3 16
65 #define CYGNUM_HAL_INTERRUPT_MCP 18
66 #define CYGNUM_HAL_INTERRUPT_SSP 19
67 #define CYGNUM_HAL_INTERRUPT_TIMER0 26
68 #define CYGNUM_HAL_INTERRUPT_TIMER1 27
69 #define CYGNUM_HAL_INTERRUPT_TIMER2 28
70 #define CYGNUM_HAL_INTERRUPT_TIMER3 29
71 #define CYGNUM_HAL_INTERRUPT_HZ 30
72 #define CYGNUM_HAL_INTERRUPT_ALARM 31
74 // GPIO bits 31..11 can generate interrupts as well, but they all
75 // end up clumped into interrupt signal #11. Using the symbols
76 // below allow for detection of these separately.
78 #define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
79 #define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
80 #define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
81 #define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
82 #define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
83 #define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
84 #define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
85 #define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
86 #define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
87 #define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
88 #define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
89 #define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
90 #define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
91 #define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
92 #define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
93 #define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
94 #define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
96 #define CYGNUM_HAL_INTERRUPT_NONE -1
98 #define CYGNUM_HAL_ISR_MIN 0
99 #define CYGNUM_HAL_ISR_MAX (27+32)
101 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
103 // The vector used by the Real time clock
104 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
106 // The vector used by the Ethernet
107 #define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0
109 // method for reading clock interrupt latency
110 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
111 externC void hal_clock_latency(cyg_uint32 *);
112 # define HAL_CLOCK_LATENCY( _pvalue_ ) \
113 hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
116 //----------------------------------------------------------------------------
118 #define HAL_PLATFORM_RESET() \
120 *(volatile unsigned short *)WDOG1_BASE_ADDR |= 0x4; \
121 /* hang here forever if reset fails */ \
125 // Fallback (never really used)
126 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
128 #endif // CYGONCE_HAL_VAR_INTS_H