1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
4 //=============================================================================
8 // HAL cache control API
10 //=============================================================================
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43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
49 // Purpose: Cache control API
50 // Description: The macros defined here provide the HAL APIs for handling
51 // cache control operations.
53 // #include <cyg/hal/hal_cache.h>
57 //####DESCRIPTIONEND####
59 //=============================================================================
61 #include <cyg/infra/cyg_type.h>
62 //#include <cyg/hal/hal_mmu.h>
64 //-----------------------------------------------------------------------------
67 #define HAL_DCACHE_SIZE 0x8000 // Size of data cache in bytes
68 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
69 #define HAL_DCACHE_WAYS 32 // Associativity of the cache
70 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
72 #define HAL_ICACHE_SIZE 0x8000 // Size of icache in bytes
73 #define HAL_ICACHE_LINE_SIZE 32 // Size of ins cache line
74 #define HAL_ICACHE_WAYS 32 // Associativity of the cache
75 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
77 //-----------------------------------------------------------------------------
78 // Global control of data cache
80 // Enable the data cache
81 #define HAL_DCACHE_ENABLE() \
84 "mrc p15,0,r1,c7,c10,4;" /* drain write buffer */ \
85 "mrc p15,0,r1,c1,c0,0;" \
86 "orr r1,r1,#0x0007;" /* enable DCache (also ensures the */ \
87 /* MMU and alignment faults are */ \
89 "mcr p15,0,r1,c1,c0,0;" \
92 : "r1" /* Clobber list */ \
96 // Disable the data cache (and invalidate it, required semanitcs)
97 #define HAL_DCACHE_DISABLE() \
100 "mrc p15,0,r1,c1,c0,0;" \
102 "mcr p15,0,r1,c1,c0,0;" \
104 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
107 "mcr p15,0,r1,c7,c6,0;" /* invalidate data cache */ \
109 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
114 : "r1" /* Clobber list */ \
118 // Invalidate the entire cache (and both TLBs, just in case)
119 #define HAL_DCACHE_INVALIDATE_ALL() \
121 /* this macro can discard dirty cache lines. */ \
123 "mcr p15,0,r1,c7,c6,0;" /* invalidate data cache */ \
124 "mcr p15,0,r1,c8,c7,0;" /* flush I+D TLBs */ \
127 : "r1" /* Clobber list */ \
132 // Synchronize the contents of the cache with memory.
133 #define HAL_DCACHE_SYNC() \
135 /* The best way to evict a dirty line is by using the */ \
136 /* line allocate operation on non-existent memory. */ \
138 "mov r0, #0xa4000000;" /* cache flush region */ \
139 "add r1, r0, #0x8000;" /* 32KB cache */ \
141 "mcr p15,0,r0,c7,c2,5;" /* allocate a line */ \
142 "add r0, r0, #32;" /* 32 bytes/line */ \
145 "mcr p15,0,r0,c7,c6,0;" /* invalidate data cache */ \
147 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
150 "mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
152 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
158 : "r0","r1" /* Clobber list */ \
162 // Query the state of the data cache
163 #define HAL_DCACHE_IS_ENABLED(_state_) \
166 asm volatile ("mrc p15,0,%0,c1,c0,0" \
171 (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
174 // Set the data cache refill burst size
175 //#define HAL_DCACHE_BURST_SIZE(_size_)
177 // Set the data cache write mode
178 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
180 #define HAL_DCACHE_WRITETHRU_MODE 0
181 #define HAL_DCACHE_WRITEBACK_MODE 1
183 // Get the current writeback mode - or only writeback mode if fixed
184 #define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
185 _mode_ = HAL_DCACHE_WRITEBACK_MODE; \
189 //-----------------------------------------------------------------------------
190 // Global control of Instruction cache
192 // Enable the instruction cache
193 #define HAL_ICACHE_ENABLE() \
196 "mrc p15,0,r1,c1,c0,0;" \
197 "orr r1,r1,#0x1000;" /* enable ICache */ \
198 "mcr p15,0,r1,c1,c0,0;" \
201 : "r1" /* Clobber list */ \
205 // Disable the instruction cache (and invalidate it, required semanitcs)
206 #define HAL_ICACHE_DISABLE() \
209 "mrc p15,0,r1,c1,c0,0;" \
210 "bic r1,r1,#0x1000;" /* disable Icache */ \
211 "mcr p15,0,r1,c1,c0,0;" \
212 "mcr p15,0,r1,c7,c5,0;" /* invalidate instruction cache */ \
213 "nop;" /* next few instructions may be via cache */ \
221 : "r1" /* Clobber list */ \
225 // Invalidate the entire cache
226 #define HAL_ICACHE_INVALIDATE_ALL() \
229 "mcr p15,0,r1,c7,c5,0;" /* clear instruction cache */ \
230 "mcr p15,0,r1,c8,c5,0;" /* flush I TLB only */ \
232 "mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
235 "nop;" /* next few instructions may be via cache */ \
243 : "r1" /* Clobber list */ \
248 // Synchronize the contents of the cache with memory.
249 // (which includes flushing out pending writes)
250 #define HAL_ICACHE_SYNC() \
252 HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
253 HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
256 // Query the state of the instruction cache
257 #define HAL_ICACHE_IS_ENABLED(_state_) \
259 /* SA-110 manual states clearly that the control reg is readable */ \
260 register cyg_uint32 reg; \
261 asm volatile ("mrc p15,0,%0,c1,c0,0" \
266 (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
270 //-----------------------------------------------------------------------------
271 #endif // ifndef CYGONCE_HAL_CACHE_H
272 // End of hal_cache.h