1 #ifndef CYGONCE_HAL_ARCH_INC
2 #define CYGONCE_HAL_ARCH_INC
3 ##=============================================================================
7 ## fr30 assembler header file
9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN####
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41 ## -------------------------------------------
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43 ##=============================================================================
44 #######DESCRIPTIONBEGIN####
47 ## Contributors: larsi
49 ## Purpose: Architecture definitions.
50 ## Description: This file contains various definitions and macros that are
51 ## useful for writing assembly code for the fr30 CPU family.
53 ## #include <cyg/hal/arch.inc>
57 ######DESCRIPTIONEND####
59 ##=============================================================================
61 #include <cyg/hal/fr30.inc>
63 #include <cyg/hal/variant.inc>
65 ##-----------------------------------------------------------------------------
66 ## define some .equ's to access c-code #define's from assembler code
67 .equ CYGNUM_ASM_CALL_IF_TABLE_SIZE, CYGNUM_CALL_IF_TABLE_SIZE
69 ##-----------------------------------------------------------------------------
70 ## CPU specific macros. These provide a common assembler interface to
71 ## operations that may have CPU specific implementations on different
72 ## variants of the architecture
74 #ifndef CYGPKG_HAL_FR30_CPU_INIT_DEFINED
78 #endif /* !CYGPKG_HAL_FR30_CPU_INIT_DEFINED */
80 .macro hal_cpu_int_enable
84 .macro hal_cpu_int_disable
89 # Merge the interrupt enable state of the status register in
90 # \sr with the current sr.
92 .macro hal_cpu_int_merge sr
93 FIXME hal_cpu_int_merge not implemented yet
96 ##-----------------------------------------------------------------------------
97 # Default FR30 interrupt controller macros. Every FR30 has an integrated
98 # interrupt controller, which we use here. This should be enough if there is
99 # no special external interrupt controller (which I did not see yet).
101 #ifndef CYGPKG_HAL_FR30_INTC_DEFINED
103 #ifndef CYGPKG_HAL_FR30_INTC_INIT_DEFINED
104 # initialize all interrupts to disabled. This is done automatically during
105 # CPU reset and the macro is not used during ECOS startup. It is not
106 # supplied here but would be setting all ICRs to 31 (to disable the particular
107 # interrupt and maybe setting ILM in PS to 0.
113 # Normally interrupts are decoded by hardware and can not be software decoded,
114 # so this is empty here.
116 .macro hal_intc_decode vnum
119 # Also translation interrupt number <--> vector number is done automatically
120 # in hardware, so the macros are not supplied here.
124 #------------------------------------------------------------------------------
125 # These defines are for the ISR and VSR tables which are defined in assembler
126 # code. (currently in variant.S / vectors.S) and have to be the same like in
129 #define CYGNUM_HAL_VECTOR_INTRFIRST 15
130 #define CYGNUM_HAL_VECTOR_INTRLAST 63
131 #define CYGNUM_HAL_VECTOR_NUMINTRS (CYGNUM_HAL_VECTOR_INTRLAST-CYGNUM_HAL_VECTOR_INTRFIRST+1)
133 // Common interrupt vectors
134 #ifndef CYGNUM_HAL_ISR_MIN
135 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_VECTOR_INTRFIRST
136 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_INTRLAST
137 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_VECTOR_NUMINTRS)
140 // The default size of the VSR table is 256 entries.
141 #ifndef CYGNUM_HAL_VSR_MIN
142 #define CYGNUM_HAL_VSR_MIN 0
143 #define CYGNUM_HAL_VSR_MAX 255
144 #define CYGNUM_HAL_VSR_COUNT 256
147 #------------------------------------------------------------------------------
148 # Register save and restore macros. These expect a pointer to a CPU save state
149 # area in the register \ptr. The GPR indicated by \reg will be saved into its
150 # slot in that structure.
152 # TODO do this macros if needed, look at MIPS arch.inc for inspiration
155 #------------------------------------------------------------------------------
156 # Stack switching macros
160 #------------------------------------------------------------------------------
164 #------------------------------------------------------------------------------
167 #ifndef CYGPKG_HAL_FR30_CACHE_DEFINED
169 .macro hal_cache_init
175 #------------------------------------------------------------------------------
176 # Diagnostics macros.
178 #------------------------------------------------------------------------------
179 # Timer initialization.
181 #ifndef CYGPKG_HAL_FR30_TIMER_DEFINED
183 .macro hal_timer_init
188 #------------------------------------------------------------------------------
189 # Difference of the flash memory from the linkers LMA (loadmemoryaddress) after
190 # the new mapping in (mapping is done in hal_fr30_ram_startup_trampoline).
192 #ifndef CYGPKG_HAL_FR30_LMA_OFFSET
194 #define CYGPKG_HAL_FR30_LMA_OFFSET 0x0
199 #endif // ifndef CYGONCE_HAL_ARCH_INC